IS31FL3730 AUDIO MODULATED MATRIX LED DRIVER December 2011 GENERAL DESCRIPTION FEATURES IS31FL3730 is a LED matrix driver which features an audio modulation display mode and a general LED dot matrix display mode. The default configuration of IS31FL3730 is to drive a single 8×8 LED matrix. However, IS31FL3730 may be configured to drive either one or two 8×8, 7×9, 6×10, or 5×11 dot matrix display(s). The intensity of any matrix picture can be modulated by an audio signal. In matrix display mode, the rows and columns of the matrix are internally scanned, requiring only one time programming of the individual LED on or off state, thus eliminating the need for real time system resource utilization to perform the row and column scanning function. In the general purpose mode, the ON or OFF condition of each individual LED in the display matrix is programmed via an I2C interface. IS31FL3730 is available in QFN-24 (4mm × 4mm). It operates from 2.7V to 5.5V over the temperature range of -40°C to +85°C. 2.7V to 5.5V supply I2C interface, automatic address increment function Internal reset register Programmable single or dual 8×8, 7×9, 6×10, or 5×11 LED matrix display mode One-time programming, internal scan Audio modulated display intensity with digitally programmable input gain Internal registers to digitally adjust display intensity Modulate LED brightness with 128 different items in PWM One address pin with 4 logic levels to allow four I2C slave addresses Over-temperature protection QFN-24 (4mm × 4mm) package APPLICATIONS Mobile phones and other hand-held devices for LED display LED in home appliances TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit Dual 8×8 Note: The IC should be placed far away from the mobile antenna in order to prevent the EMI. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 1 IS31FL3730 Figure 2 Typical Application Circuit Dual 7×9 Figure 3 Typical Application Circuit Dual 6×10 Figure 4 Typical Application Circuit Dual 5×11 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 2 IS31FL3730 PIN CONFIGURATION Package Pin Configuration (Top View) QFN-24 PIN DESCRIPTION No. Pin Description 1 SDA I2C serial data. 2 SCL I2C serial clock. 3 SDB Shutdown the chip when pull to low. 4 IN Audio input. 5 C_FILT Filter cap for audio control. 6 AD I2C address setting. 7~10, 12 R1~R5 Row control. 11 VCC Power supply. 13~15 R6/C11, R7/C10, R8/C9 Row/column control. 16~19, 21~24 C8~C5, C4~C1 Column control. 20 GND Ground. Thermal Pad Connect to GND. Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 3 IS31FL3730 ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31FL3730-QFLS2-TR QFN-24, Lead-free 2500 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 4 IS31FL3730 ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at any input pin Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA -0.3V ~ +6.0V -0.3V ~ VCC+0.3V 150°C -65°C ~ +150°C −40°C ~ +85°C Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C, VCC =2.7V to 5.5V, unless otherwise noted. Typical value are TA = 25°C, VCC = 3.6V. Symbol Parameter Condition VCC Supply voltage ICC Quiescent power supply VIN = 0V, without audio input, all LEDs off current ISD Shutdown current IOUT Min. Typ. 2.7 Max. Unit 5.5 V 7.0 VSDB = 0V VSDB = VCC, software shutdown Matrix display mode without audio modulation Lighting Effect Register(0Dh) = 0xxx Output current of R1~R8, 0000 C1~C8 Matrix display mode with audio modulation VIN =2.5VP-P, 1kHz square wave Audio Gain = 0dB mA 0.2 1.0 1.7 3.0 μA 40 (Note 1) mA 40 (Note 1) Current sink headroom Isink = 320mA (Note 2) voltageR1~R8,C1~C8 300 Current source headroom Isource = 40mA voltage R1~R8,C1~C8 200 tSCAN Period of row and column scanning (Figure 10) 32 µs tSCANOL Non-overlap blanking time during row and column scan (Figure 10) 1 µs VHR mV Logic Electrical Characteristics (SDA, SCL, AD) VIL Logic “0” input voltage VCC = 2.7V VIH Logic “1” input voltage VCC = 5.5V IIL Logic “0” input current VIN = 0V (Note 3) IIH Logic “1” input current VIN = VCC (Note 3) Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 0.4 1.4 V V 5 5 nA nA 5 IS31FL3730 DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 3) Symbol Parameter Condition Min. Typ. Max. Units 400 kHz fSCL Serial-Clock frequency tBUF Bus free time between a STOP and a START condition 1.3 μs tHD, STA Hold time (repeated) START condition 0.6 μs tSU, STA Repeated START condition setup time 0.6 μs tSU, STO STOP condition setup time 0.6 μs tHD, DAT Data hold time tSU, DAT Data setup time 100 ns tLOW SCL clock low period 1.3 μs tHIGH SCL clock high period 0.7 μs 0.9 μs tR Rise time of both SDA and SCL signals, receiving (Note 4) 20+0.1Cb 300 ns tF Fall time of both SDA and SCL signals, receiving (Note 4) 20+0.1Cb 300 ns Note 1: Due to the row and column scanning sequence, the average current of an individual LED in the display is IOUT/8 when configured to drive a single matrix. When configured to drive two matrices, the average current of an individual LED in the display is IOUT/16. Note 2: All row drivers are on. Note 3: Guaranteed by design. Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 6 IS31FL3730 DETAILED DESCRIPTION After the last bit of the chip address is sent, the master checks for the IS31FL3730’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3730 has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. I2C INTERFACE The IS31FL3730 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS31FL3730 has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Since IS31FL3730 only supports write operations, A0 must always be 0. The value of bits A1 and A2 are decided by the connection of the AD pin. Following acknowledge of IS31FL3730, the register address byte is sent, most significant bit first. IS31FL3730 must generate another acknowledge indicating that the register address has been received. The complete slave address is: Table1 Slave Address (Write only): Bit A7:A3 A2:A1 A0 Value 11000 AD 0 Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3730 must generate another acknowledge to indicate that the data was received. AD connected to GND, AD=00; AD connected to VCC, AD=11; AD connected to SCL, AD=01; AD connected to SDA, AD=10; The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. The SCL line is uni-directional. The SDA line is bi-directional (open-collector) with a pull-up resistor (typically 4.7kΩ). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3730. Address Auto Increment To write multiple bytes of data into IS31FL3730, load the address of the data register that the first data byte is intended for. During the IS31FL3730 acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS31FL3730 will be placed in the new address, and so on. The auto increment of the address will continue as long as data continues to be written to IS31FL3730. This feature is useful for loading the LED on/off condition for each of the display matrices as a burst of data. Pay careful attention when loading data for dual LED matrix displays since the register addressing is not continuous. The timing diagram for the I2C is shown in Figure 5. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. Figure 5 Interface Timing SDA SCL DATA LINE STABLE; CHANGE OF DATA DATA VALID ALLOWED Figure 6 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 Bit Transfer 7 IS31FL3730 Figure 7 Writing to IS31FL3730(Typical) Figure 8 Writing to IS31FL3730(Automatic Address Increment) REGISTER DEFINITION Table2 Register Function Address Name Table Default 00h Configuration Register Set operation mode of IS31FL3730 3 0000 0000 01h~0Bh Matrix 1 Data Register Store the on or off state of each LED 4 0Eh~18h Matrix 2 Data Register Store the on or off state of each LED 5 0Ch Update Column Register Make the Data Register update the data - xxxx xxxx 0Dh Lighting Effect Register Store the intensity control settings 6 0000 0000 19h PWM Register Modulate LED light with 128 different items 7 1000 0000 FFh Reset Register Reset all registers to default value - xxxx xxxx Table3 Function 00h Configuration Register Bit D7 D6:D5 D4:D3 D2 Name SSD Reserved DM A_EN Default 0 00 00 0 D1 D0 ADM 0 0 The Configuration Register sets operation mode of IS31FL3730. SSD 0 1 Software Shutdown Enable Normal operation Software shutdown mode DM 00 01 11 Display Mode Matrix 1 only Matrix 2 only Matrix 1 and Matrix 2 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 0000 0000 A_EN Audio Input Enable 0 Matrix intensity is controlled by the current setting in the Lighting Effect Register (0Dh) 1 Enable audio signal to modulate the intensity of the matrix ADM 00 01 10 11 Matrix Mode Selection 8×8 dot matrix display mode 7×9 dot matrix display mode 6×10 dot matrix display mode 5×11 dot matrix display mode 8 IS31FL3730 Table4 01h~0Bh Matrix 1 Data Register(C1~C11) Bit D7:D0 Name R8:R1 Default 00000000 Table5 0Eh~18h Matrix 2 Data Register(C1~C11) Bit D7:D0 Name R8:R1 Default 00000000 Full Current Setting for Each Row Output 40mA 45mA CS 0000: 0001: ... ... 0111: 1000: 1001: ... ... 1110: 75mA 5mA 10mA 35mA Table7 19h PWM Register The Data Registers (Matrix 1/Matrix 2) store the on or off state of each LED in the Matrix. Rx LED State 0 LED off 1 LED on 11×2 registers are assigned to C1~C11 columns respectively; the LED at a particular (row, column) location will be turned on when the respective data is set to “1”. When configured for more than 8 column operation, only the required numbers of LSBs are used in each data register. For example, in 5×11 dot matrix mode, only bits R1 thru R5 are used, and bits R6 thru R8 are ignored. Bit D7 D6:D0 Default 1 0000000 The PWM Register can modulate LED light with 128 different items. When the D7 set to “1”, the PWM is the 128 item. When the D7 set to “0”, D6:D0 set the PWM from the 0 item to the 127 item. For example, if the data in PWM Register is 0000 0100, then the PWM is the 4 item. 0Ch Update Column Register The data sent to the Data Registers will be stored in temporary registers. A write operation of any 8-bit value to the Update Column Register is required to update the Data Registers (01h~0Bh, 0Eh~18h). Figure 9 Table6 0Dh Lighting Effect Register Bit D7 D6:D4 D3:D0 Name Reserved AGS CS Default 0 000 0000 The Lighting Effect Register stores the intensity control settings for all of the LEDs in the Matrix. AGS 000: 001: 010: 011: 100: 101: 110: 111: PWM Timing Diagram FFh Reset Register Once user writes any 8-bit data to the Reset Register, IS31FL3730 will reset all registers to default value. On initial power-up, the IS31FL3730 registers are reset to their default values for a blank display. Audio Input Gain Selection Gain= 0dB Gain= +3dB Gain= +6dB Gain= +9dB Gain= +12dB Gain= +15dB Gain= +18dB Gain= -6dB Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 9 IS31FL3730 APPLICATION INFORMATION GENERAL PURPOSE DOT MATRIX DISPLAY MODE DUAL 5×11 DOT MATRIX DISPLAY MODE The general purpose dot matrix display timing diagram is shown in Figure 10. IS31FL3730 may be configured to drive displays of different dimensions from 8×8 to 5×11. Furthermore, IS31FL3730 may be configured to drive one or two LED matrices of the same dimension. Therefore, the overall row and column scan time can vary based on the final LED matrix configuration. By setting the ADM bits of the Configuration Register (00h) to “11” and the DM bits to “11”, the IS31FL3730 will operate in the dual 5×11 LED dot matrix display mode. In any LED matrix configuration, a single line (column or row) of LEDs is illuminated for 32µs before IS31FL3730 moves on to the next line of LEDs (Figure 10). Example 1: When the IS31FL3730 is configured in the general purpose dual 8×8 dot matrix display mode, column controls C8:C1 scans the eight columns of Matrix 1 then row controls R8:R1 scans the eight rows of Matrix 2 at a rate of 1.89kHz, or 528µs per frame. Each line is active for 32µs. The non-overlap interval between adjacent lines is 1µs. Example 2: When configured to drive a single 7×9 dot matrix display (Matrix 1), the column controls C9:C1 scan the nine columns every 297µs. Also note that in this case, the Data Registers’ MSB will be ignored. The Matrix 1 LED columns have common cathodes and are connected to the C1:C11 outputs. The rows are connected to the row drivers. The Matrix 2 LED rows have common cathodes and are connected to the R1:R5 outputs. The columns are connected to the column drivers. Each of the 110 LEDs can be addressed separately. The three MSBs (D7:D5) of each Data Register (01h~0Bh, 0Eh~18h) are ignored. DOT MATRIX DISPLAY MODE WITH AUDIO MODULATION When the IS31FL3730 operates in any of the dot matrix modes, if the bit A_EN in Configuration Register (00h) is set to “1”, the brightness of LED image can be modulated by audio signal not controlled by the CS bit in Lighting Effect Register (0Dh). An external capacitor, C_FILT is required to control the rate at which the display intensity will change. The rate of change is computed using the formula: ∆T = C×500kΩ. A value of 0.1µF provides a good effect by allowing the display to fade from full intensity to off in approximately 50ms. Smaller capacitance will cause the intensity to change more quickly, and, conversely, a larger capacitance will cause the display intensity to change at a slower rate. SHUTDOWN MODE Figure 10 Dot Matrix Display Timing Diagram Shutdown mode can either be used as a means of reducing power consumption or generating a flashing display (repeatedly entering and leaving shutdown mode). During shutdown mode all registers retain their data. DUAL 8×8 DOT MATRIX DISPLAY MODE SOFTWARE SHUTDOWN The application example in Figure 1 shows the IS31FL3730 in the dual 8×8 LED dot matrix display mode. By setting SSD bit of the Configuration Register (00h) to “1”, the IS31FL3730 will operate in software shutdown mode, wherein they consume only 1.7μA (Typ.) current. When the IS31FL3730 is in software shutdown mode, all current sources and digital drivers are switched off, so that the matrix is blanked. The Matrix 1 LED columns have common cathodes and are connected to the C1:C8 outputs. The rows are connected to the row drivers. The Matrix 2 LED rows have common cathodes and connected to the R1:R8. The columns are connected to the C1:C8. Each of the 128 LEDs can be addressed separately. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 HARDWARE SHUTDOWN The chip enters hardware shutdown mode when the SDB pin is pulled low. 10 IS31FL3730 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 11 Classification profile Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 11 IS31FL3730 TAPE AND REEL INFORMATION Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 12 IS31FL3730 PACKAGE INFORMATION QFN-24 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 13