IS61LV256AL 32K x 8 LOW VOLTAGE CMOS STATIC RAM AUGUST 2009 FEATURES • High-speed access times: — 10 ns • Automatic power-down when chip is deselected • CMOS low power operation — 60 µW (typical) CMOS standby — 65 mW (typical) operating • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three-state outputs • Lead-free available DESCRIPTION The ISSI IS61LV256AL is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 150 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE).The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256AL is available in the JEDEC standard 28-pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32KX8 MEMORYARRAY I/O DATA CIRCUIT COLUMNI/O VDD GND I/O0-I/O7 CE OE WE CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 1 IS61LV256AL PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOJ 28-Pin TSOP (Type I) A14 1 28 VDD A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7Input/Output Vdd Power GND Ground OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X CE H OE X H H L L L L H L X I/O Operation Vdd Current High-Z Isb1, Isb2 High-Z Dout Din Icc Icc Icc ABSOLUTE MAXIMUM RATINGS(1) Symbol Vdd Vterm Tstg Pd Iout Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current Value Unit –0.5 to +4.6 V –0.5 to +4.6 V –65 to +150 °C 1 W ±20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 IS61LV256AL OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C Speed (ns) 10 10 Vdd(1) 3.3V, +10%, –5% 3.3V + 10%, –5% Note: 1. If operated at 12ns, Vdd range is 3.3V + 10%. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –2.0 mA Vdd = Min., Iol = 4.0 mA GND ≤ Vin ≤ Vdd Com. Ind. GND ≤ Vout ≤ Vdd, Outputs Disabled Com. Ind. Min. 2.4 — 2.2 –0.3 –1 –2 –1 –2 Max. — 0.4 Vdd + 0.3 0.8 1 2 1 2 Unit V V V V µA µA Notes: 1. Vil (min.) = –0.3V (DC); Vil (min.) = –2.0V (pulse width ≤ 2.0 ns). Vih (max.) = Vdd + 0.5V (DC); Vih (max.) = Vdd + 2.0V (pulse width ≤ 2.0 ns). 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 3 IS61LV256AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Sym. Parameter Test Conditions Icc1 Vdd Operating Vdd = Max., CE = Vil Supply Current Iout = 0 mA, f = 1 MHz Icc2 Vdd Dynamic Operating Vdd = Max., CE = Vil Supply Current Iout = 0 mA, f = fmax Isb1 TTL Standby Current Vdd = Max., (TTL Inputs) Vin = Vih or Vil CE ≥ Vih, f = 0 Isb2 CMOS Standby Vdd = Max., Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0 -10 ns Min. Com. Ind. Com. Ind. typ.(2) Com. Ind. — — — — Max. Unit — — 1 1 mA Com. Ind. typ.(2) — — 40 50 µA 20 mA 25 30 mA 35 20 2 Notes: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 5 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 IS61LV256AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -10 ns Symbol Parameter Min. Max. trc Read Cycle Time 10 — taa Address Access Time — 10 toha Output Hold Time 2 — tace CE Access Time — 10 tdoe OE Access Time — 5 (2) tlzoe OE to Low-Z Output 0 — thzoe(2) OE to High-Z Output — 5 (2) tlzce CE to Low-Z Output 3 — (2) thzce CE to High-Z Output — 5 (3) tpu CE to Power-Up 0 — tpd(3) CE to Power-Down — 10 -12 ns Min. 12 — 2 — — 0 — 3 — 0 — Max. — 12 — 12 5 — 5 — 6 — 12 Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 Ω 319 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF Including jig and scope 353 Ω 353 Ω Figure 1. Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 5 pF Including jig and scope 5 IS61LV256AL AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t OHA DOUT t AA t OHA DATAVALID PREVIOUSDATAVALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATAVALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 IS61LV256AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc tsce taw tha tsa tpwe1 tpwe2 tsd thd thzwe(3) tlzwe(3) -10 ns Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE HIGH) WE Pulse Width (OE LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -12 ns Min. Max. Min. Max. Unit 10 8 8 — — — 12 8 8 — — — ns ns ns 0 — 0 — ns 0 7 10 6.5 0 — 0 — — — — — 3.5 — 0 8 12 7 0 — 0 — — — — — 5 — ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALIDADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATAUNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAINVALID CE_WR1.eps Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 7 IS61LV256AL WRITE CYCLE NO. 2 (WE Controlled, OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALIDADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATAUNDEFINED t SD t HD DATAINVALID DIN CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) (1) t WC ADDRESS VALIDADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATAUNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAINVALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > Vih. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 IS61LV256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Vdr Vdd for Data Retention Idr Data Retention Current tsdr Data Retention Setup Time trdr Recovery Time Note: Test Condition See Data Retention Waveform Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. Vin ≥ Vdd – 0.2V, or Vin ≤ Vss + 0.2V Ind. See Data Retention Waveform See Data Retention Waveform Min. Typ.(1) 2.0 — 2 — — 0 trc Max. Unit 3.6 V 40 µA 50 — ns — ns 1. Typical Values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 CE ≥ VDD - 0.2V 9 IS61LV256AL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 10 Order Part No. IS61LV256AL-10T IS61LV256AL-10TL IS61LV256AL-10J IS61LV256AL-10JL Package TSOP - Type I TSOP - Type I, Lead-free 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 10 10 Order Part No. IS61LV256AL-10TI IS61LV256AL-10TLI IS61LV256AL-10JI IS61LV256AL-10JLI Package TSOP - Type I TSOP - Type I, Lead-free 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 IS61LV256AL Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 07/29/09 11 IS61LV256AL 0.1 Y NOTE : 1. Controlling dimension : mm 2. Dimension D1 adn E do not include mold protrusion . 3. Dimension b2 does not include dambar protrusion/intrusion. 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. Package Outline 07/05/2006 Rev. C 07/29/09 Integrated Silicon Solution, Inc. — 1-800-379-4774 12