IS61WV20488ALL IS61/64WV20488BLL 2M x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply – Vdd 1.65V to 2.2V (IS61WV20488ALL) speed = 20ns for Vcc = 1.65V to 2.2V – Vdd 2.4V to 3.6V (IS61/64WV20488BLL) speed = 10ns for Vcc = 2.4V to 3.6V speed = 8ns for Vcc = 3.3V + 5% • Packages available: – 48-ball miniBGA (9mm x 11mm) – 44-pin TSOP (Type II) • Industrial and Automotive Temperature Support • Lead-free available AUGUST 2010 DESCRIPTION The ISSI IS61WV20488ALL/BLL and IS64WV20488BLL are very high-speed, low power, 2M-word by 8-bit CMOS static RAM. The IS61WV20488ALL/BLL and IS64WV20488BLL are fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. The IS61WV20488ALL/BLL and IS64WV20488BLL operate from a single power supply and all inputs are TTL-compatible. The IS61WV20488ALL/BLL and IS64WV20488BLL are available in 48 ball mini BGA and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A20 DECODER 2MX8 MEMORYARRAY I/O DATA CIRCUIT COLUMNI/O VDD GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 1 IS61WV20488ALL, IS61/64WV20488BLL PIN CONFIGURATION 48-pin Mini BGA (M ) (9mm x 11mm) 1 2 3 4 5 44-pin TSOP (Type II ) 6 A NC OE A0 A1 A2 NC B NC NC A3 A4 CE I/O0 C NC NC A5 A6 I/O1 I/O2 D GND NC A17 A7 I/O3 VDD E VDD NC NC A16 I/O4 GND F NC NC A14 A15 I/O5 I/O6 G NC A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 A20 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC A20 A18 A17 A16 A15 OE I/O7 I/O6 GND VDD I/O5 I/O4 A14 A13 A12 A11 A10 A19 NC NC PIN DESCRIPTIONS A0-A20 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7Data Input / Output Vdd Power GND Ground NC No Connection 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL TRUTH TABLE Mode WE Not Selected X (Power-down) Output DisabledH Read H Write L CE H L L L OE I/O Operation Vdd Current X High-Z Isb1, Isb2 H L X High-Z Dout Din Icc Icc Icc ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Relates to GND Storage Temperature Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 3 IS61WV20488ALL, IS61/64WV20488BLL OPERATING RANGE (Vdd) (IS61WV20488ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd (20 ns) 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (Vdd) (IS61WV20488BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (8 ns) 3.3V + 5% 3.3V + 5% Vdd (10 ns) 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (Vdd) (IS64WV20488BLL) Range Ambient Temperature Automotive –40°C to +125°C 4 Vdd (10 ns) 2.4V-3.6V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –4.0 mA Output LOW Voltage Vdd = Min., Iol = 8.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Min. 1.8 — 2.0 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA Output LOW Voltage Vdd = Min., Iol = 1.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Test Conditions Vdd Output HIGH Voltage Ioh = -0.1 mA 1.65-2.2V Output LOW Voltage Iol = 0.1 mA 1.65-2.2V Input HIGH Voltage 1.65-2.2V Input LOW Voltage 1.65-2.2V Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 Vdd + 0.2 0.4 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 5 IS61WV20488ALL, IS61/64WV20488BLL AC TEST CONDITIONS (HIGH SPEED) Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0.4V to Vdd-0.3V 1.5ns Vdd/2 Unit (3.3V + 5%) 0.4V to Vdd-0.3V 1.5ns Vdd/2 + 0.05 Unit (1.65V-2.2V) 0.4V to Vdd-0.2V 1.5ns Vdd/2 See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 50Ω 1.5V OUTPUT 30pF Including jig and scope Figure 1. 6 3.3V OUTPUT 5 pF Including jig and scope 353 Ω Figure 2. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Test Conditions Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 120 Supply Current Iout = 0 mA, f = fmax Ind. — 125 Auto. — — typ.(2) Icc1 Operating Vdd = Max., Com. — 35 Supply Current Iout = 0 mA, f = 0 Ind. — 35 Auto. — — Isb1 TTL Standby Current Vdd = Max., Com. — 30 (TTL Inputs) Vin = Vih or Vil Ind. — 35 CE ≥ Vih, f = 0 Auto. — — Isb2 CMOS Standby Vdd = Max., Com. — 20 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 25 Vin ≥ Vdd – 0.2V, or Auto. — — Vin ≤ 0.2V, f = 0 typ.(2) -10 Min. Max. — 95 — 100 — 140 60 — 30 — 40 — 60 — 30 — 35 — 70 — 20 — 25 — 70 4 -20 Min. Max. Unit — 90 mA — 100 — 140 — — — — — — — — — 30 mA 40 70 30 mA 35 70 15 mA 20 70 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 7 IS61WV20488ALL, IS61/64WV20488BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter trc Read Cycle Time taa Address Access Time toha Output Hold Time tace CE Access Time tdoe OE Access Time (2) thzoe OE to High-Z Output tlzoe(2) OE to Low-Z Output thzce(2 CE to High-Z Output (2) tlzce CE to Low-Z Output tpu Power Up Time tpd Power Down Time -8 Min. Max. 8 — — 8 2 — — 8 — 5.5 — 3 0 — 0 3 3 — 0 — — 8 -10 Min. Max. 10 — — 10 2 — — 10 — 6.5 — 4 0 — 0 4 3 — 0 — — 10 Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter trc Read Cycle Time taa Address Access Time toha Output Hold Time tace CE Access Time tdoe OE Access Time (2) thzoe OE to High-Z Output (2) tlzoe OE to Low-Z Output thzce(2 CE to High-Z Output (2) tlzce CE to Low-Z Output tpu Power Up Time tpd Power Down Time -20 ns Min. Max. 20 — — 20 2.5 — — 20 — 8 0 8 0 — 0 8 3 — 0 — — 20 Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 9 IS61WV20488ALL, IS61/64WV20488BLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil) t RC ADDRESS t OHA DOUT t AA t OHA DATAVALID PREVIOUSDATAVALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATAVALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol twc tsce taw tha tsa tpwe1 tpwe2 tsd thd thzwe(2) tlzwe (2) -8 Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -10 Min. Max. 10 — 8 — 8 — Min. 8 6.5 6.5 Max. — — — 0 0 6.5 8.0 5 0 — — — — — — 0 0 8 10 6 0 — — — — — — ns ns ns ns ns ns — 2 3.5 — — 2 5 — ns ns Unit ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 11 IS61WV20488ALL, IS61/64WV20488BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc tsce taw tha tsa tpwe1 tpwe2 tsd thd thzwe(3) tlzwe(3) Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -20 ns Min. Max.Unit 20 — ns 12 — ns 12 — ns 0 0 12 17 9 0 — — — — — — — 3 9 — ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALIDADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATAUNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAINVALID CE_WR1.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 13 IS61WV20488ALL, IS61/64WV20488BLL AC WAVEFORMS WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS VALIDADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE DATAUNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAINVALID CE_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > Vih. 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALIDADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATAUNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAINVALID CE_WR3.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 15 IS61WV20488ALL, IS61/64WV20488BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Vdr Vdd for Data Retention See Data Retention Waveform 1.2 Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V Ind. — Auto. — typ.(1) tsdr Data Retention Setup Time See Data Retention Waveform 0 trdr Recovery Time See Data Retention Waveform trc Max. Unit 3.6 V 25 mA 60 3 — ns — ns Note: 1. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD 1.65V 1.4V VDR CE GND 16 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 IS61WV20488ALL, IS61/64WV20488BLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V peed (ns) S 10 (81) Order Part No. IS61WV20488BLL-10MI IS61WV20488BLL-10MLI IS61WV20488BLL-10TI IS61WV20488BLL-10TLI Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Note: 1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.3V. Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V peed (ns) S 20 Order Part No. IS61WV20488ALL-20MI IS61WV20488ALL-20TI Package 48 mini BGA (9mm x 11mm) TSOP (Type II) Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V peed (ns) S 10 Order Part No. IS64WV20488BLL-10MA3 IS64WV20488BLL-10MLA3 IS64WV20488BLL-10TA3 Package 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type II) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 17 18 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : 08/21/2008 IS61WV20488ALL, IS61/64WV20488BLL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 08/04/2010 Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : IS61WV20488ALL, IS61/64WV20488BLL 19