IS61WV6416EEBLL IS64WV6416EEBLL 64K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC ADVANCED INFORMATION OCTOBER 2012 DESCRIPTION The ISSI IS61/64WV6416EEBLL is a high-speed, FEATURES • High-speed access time: 8, 10 ns • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby • Single power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available • Error Detection and Error Correction 1,048,576-bit static RAMs organized as 65,536 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61/64WV6416EEBLL is packaged in the JEDEC standard 44-pin TSOP-II, 48-pin Mini BGA (6mm x 8mm), and 44-pin SOJ. FUNCTIONAL BLOCK DIAGRAM Memory Lower IO Array64Kx8 A0-A15 Decoder 8 IO0-7 IO8-15 /CE /OE /WE /UB /LB 8 8 I/O Data Circuit 8 ECC ECC 12 12 8 ECC Array64K x4 4 Memory ECC Array64K x4 Upper IO Array64Kx8 8 4 Column I/O Control Circuit Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com1 Rev. 00A 10/10/2012 IS61/64WV6416EEBLL TRUTH TABLE Mode Not Selected Output Disabled Read Write WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LBUB X X X X H H L H H L L L L H H L L L I/O PIN I/O0-I/O7 I/O8-I/O15Vdd Current High-Z High-Z Isb1, Isb2 High-Z High-Z Icc High-Z High-Z Dout High-Z Icc High-Z Dout Dout Dout Din High-Z Icc High-Z Din Din Din PIN CONFIGURATIONS 44-Pin TSOP-II A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC A0-A15 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VddPower GND Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 IS61/64WV6416EEBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 1 A LB 2 OE 3 A0 4 A1 5 A2 NC I/O8 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD NC I/O4 GND A3 A4 CE I/O0 E VDD F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC I/O12 NC 2 6 B UB 1 44-Pin SOJ (K) A15 1 44 A0 A14 2 43 A1 A13 3 42 A2 A12 4 41 OE A11 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 VDD 11 34 GND GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A10 18 27 A3 A9 19 26 A4 A8 20 25 A5 A7 21 24 A6 NC 22 23 NC 3 4 5 6 7 8 PIN DESCRIPTIONS 9 A0-A15 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VddPower GND Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 10 11 12 3 IS61/64WV6416EEBLL ABSOLUTE MAXIMUM RATINGS(1) SymbolParameter Vterm Terminal Voltage with Respect to GND Vdd Vdd Relates to GND Tstg Storage Temperature Pt Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. ERROR DETECTION AND ERROR CORRECTION • • • • Independent ECC with hamming code for each byte Detect and correct one bit error per byte Better reliability than parity code schemes which can only detect an error but not correct an error Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) OPERATING RANGE (Vdd)1 Range Ambient Temperature Industrial –40°C to +85°C Automotive (A1) –40°C to +85°C Automotive (A3) –40°C to +125°C IS61WV6416EEBLL Vdd (8, 10ns) 2.4V-3.6V — — IS64WV6416EEBLL Vdd — 2.4V-3.6V (8ns) 2.4V-3.6V (10ns) Note: 1. Contact [email protected] for 1.8V option 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 IS61/64WV6416EEBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 10% Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –4.0 mA Vdd = Min., Iol = 8.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled 1 Min.Max.Unit 2.4 — V — 0.4 V 2 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA 2 3 Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested. 4 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled 5 Min.Max.Unit 1.8 — V — 0.4 V 2.0 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA 6 7 Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested. 8 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8-10-20 Symbol Parameter Test ConditionsMin. Max. Min. Max. Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 40 — 30 — 25 Supply Current Iout = 0 mA, f = fmax Ind. — 45 — 35 — 30 Auto. — — — 50 — 45 typ.(2)21 21 Icc1 Operating Vdd = Max., Com. — 20 — 20 — 20 Supply Current Iout = 0 mA, f = 0 Ind. — 25 — 25 — 25 Auto. — — — 40 — 40 Isb1 TTL Standby Current Vdd = Max., Com. — 10 — 10 — 10 (TTL Inputs) Vin = Vih or Vil Ind. — 15 — 15 — 15 CE ≥ Vih, f = 0 Auto. — — — 30 — 30 Isb2 CMOS Standby Vdd = Max., Com. — 5 — 5 — 5 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 6 — 6 — 6 Vin ≥ Vdd – 0.2V, or Auto. — — — 15 — 15 Vin ≤ 0.2V, f = 0 typ.(2) 1.5 1.5 9 Unit mA mA 10 11 mA 12 mA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 5 IS61/64WV6416EEBLL AC TEST CONDITIONS ParameterUnit (2.4V-3.6V) Input Pulse Level 0.4V to Vdd-0.3V Input Rise and Fall Times 1V/ ns Input and Output Timing Vdd/2 and Reference Level (VRef) Output Load See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT 30 pF Including jig and scope Figure 1. OUTPUT 353 Ω 5 pF Including jig and scope Figure 2. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8-10-20 Symbol Parameter Min.Max. Min.Max. Min.Max. trc Read Cycle Time 8 — 10 — 20 — taa Address Access Time — 8 — 10 — 20 toha Output Hold Time 2.0 — 2.0 — 2.5 — tace CE Access Time — 8 — 10 — 20 tdoe OE Access Time — 4.5 — 4.5 — 8 (2) thzoe OE to High-Z Output — 3 — 4 0 8 tlzoe(2) OE to Low-Z Output 0 — 0 — 0 — (2 thzce CE to High-Z Output 0 3 0 4 0 8 tlzce(2) CE to Low-Z Output 3 — 3 — 3 — tba LB, UB Access Time — 5.5 — 6.5 — 8 thzb(2) LB, UB to High-Z Output 0 3 0 3 0 8 (2) tlzb LB, UB to Low-Z Output 0 — 0 — 0 — tpu Power Up Time 0 — 0 — 0 — tpd Power Down Time — 8 — 10 — 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 IS61/64WV6416EEBLL 1 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB or LB = Vil) 2 t RC ADDRESS t OHA DOUT t AA 3 t OHA DATA VALID PREVIOUS DATA VALID 4 READ1.eps 5 READ CYCLE NO. 2 (1,3) 6 tRC ADDRESS tAA tOHA 7 OE tHZOE tDOE tLZOE CE tACE tLZCE 8 tHZCE LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC 9 DATA VALID tPU 50% tPD 50% ICC 10 ISB UB_CEDR2.eps Notes: 1.WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = Vil. 3. Address is valid prior to or coincident with CE LOW transition. 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 7 IS61/64WV6416EEBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8-10-20 Symbol Parameter Min.Max. Min.Max. Min. Max. twc Write Cycle Time 8 — 10 — 20 — Unit ns tsce taw tha tsa CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time 6.5 — 6.5 — 8 — 8 — 12 — 12 — ns ns 0 — 0 — 0 — 0 — 0 — 0 — ns ns tpwb LB, UB Valid to End of Write 6.5 — 8 — 12 — ns tpwe1 WE Pulse Width 6.5 — 8 — 12 —ns tpwe2 WE Pulse Width (OE = LOW) 8 — 10 — 17 — ns tsd Data Setup to Write End 5 — 6 — 9 — ns thd Data Hold from Write End 0 — 0 — 0 — ns (2) thzwe WE LOW to High-Z Output — 3.5 — 5 — 9 ns tlzwe(2) WE HIGH to Low-Z Output 2 — 2 — 3 — ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 IS61/64WV6416EEBLL 1 AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) 2 t WC VALID ADDRESS ADDRESS t SA t SCE t HA 3 CE t AW t PWE1 t PWE2 WE 4 t PWB UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD 5 t HD DATAIN VALID DIN UB_CEWR1.eps 6 Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). 7 8 WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS 9 VALID ADDRESS t HA OE CE 10 LOW t AW t PWE1 WE t SA t PWB 11 UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN 12 t HD DATAIN VALID UB_CEWR2.eps Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 9 IS61/64WV6416EEBLL AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PWB UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR3.eps WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PWB t PWB WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 IS61/64WV6416EEBLL HIGH SPEED (IS61/64WV6416EEBLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = Vdr(min), CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25 C and not 100% tested. Options Com. Ind. Auto. Min. 2.0 — — 0 trc Typ. Max.Unit — 3.6 V 0.5 5 mA — 6 15 — — ns — — ns (1) o Data Retention Mode tRDR VDD 3 5 6 VDR CE GND 2 4 DATA RETENTION WAVEFORM (CE Controlled) tSDR 1 CE ≥ VDD - 0.2V 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com11 Rev. 00A 10/10/2012 IS61/64WV6416EEBLL ORDERING INFORMATION (HIGH SPEED) Industrial Range: -40°C to +85°C Speed (ns) 8 10 Order Part No. IS61WV6416EEBLL-8BI IS61WV6416EEBLL-8BLI IS61WV6416EEBLL-8TI IS61WV6416EEBLL-8TLI IS61WV6416EEBLL-10BI IS61WV6416EEBLL-10BLI IS61WV6416EEBLL-10TI IS61WV6416EEBLL-10TLI Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Industrial Range: -40°C to +85°C Speed (ns) 10 Order Part No. IS64WV6416EEBLL-10BA1 IS64WV6416EEBLL-10BLA1 IS64WV6416EEBLL-10CTA1 IS64WV6416EEBLL-10CTLA1 Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe Automotive Range: -40°C to +125°C Speed (ns) 10 12 Order Part No. IS64WV6416EEBLL-10BA3 IS64WV6416EEBLL-10BLA3 IS64WV6416EEBLL-10CTA3 IS64WV6416EEBLL-10CTLA3 Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS61/64WV6416EEBLL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Package Outline 08/12/2008 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61/64WV6416EEBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 10/10/2012 SEATING PLANE 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 5. Reference document : JEDEC SPEC MS-027. 3. Dimension b2 does not include dambar protrusion/intrusion. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : 12/21/2007 IS61/64WV6416EEBLL 1 2 3 4 5 6 7 8 9 10 11 12 15