IS61WV102416BBLL IS64WV102416BBLL 1Mx16 HIGH

IS61WV102416BBLL
IS64WV102416BBLL
1Mx16 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
 High-speed access time: 8, 10ns
 High- performance, low power CMOS process
 Multiple center power and ground pins for
greater noise immunity
 Easy memory expansion with CE# and OE#
 TTL compatible inputs and outputs
 Single power supply
– VDD 2.4V to 3.6V , Speed = 10ns
– VDD 3.3V + 5% , Speed = 8ns
 Packages available :
- 48 ball mini BGA (6mm x 8mm)
- 48 pin TSOP (Type I)
Industrial and Automotive temperature support

 Lead-free available
 Data Control for upper and lower bytes
DESCRIPTION
ADVANCED INFORMATION
JANUARY 2015
The ISSI IS61/64WV102416BBLL are high-speed, 16M bit
static RAMs organized as 1024K words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
When CE# is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE# and OE#. The active LOW
Write Enable
controls both writing and reading of the
memory. A data byte allows Upper Byte
and Lower
Byte (
access.
The device is packaged in the JEDEC standard 48-Pin
TSOP (TYPE I) and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
DECODER
A0 – A19
1024K x 16
MEMORY
ARRAY
VDD
GND
I/O0 – I/O7
Lower Byte
I/O8 – I/O15
Upper Byte
CE#
OE#
WE#
UB#
LB#
I/O
DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
12/16/2014
1
IS61WV102416BBLL
IS64WV102416BBLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
1
A
B
C
D
E
F
G
H
LB#
I/O8
I/O9
VSS
VDD
I/O14
2
OE#
UB#
I/O10
I/O11
I/O12
I/O13
3
A0
A3
A5
A17
NC
A14
4
A1
A4
A6
A7
A16
A15
48-Pin TSOP ,TYPE I ( 12mm x 20mm )
5
6
A2
CE#
I/O1
I/O3
I/O4
I/O5
NC
I/O0
I/O2
VDD
VSS
I/O6
I/O15
A19
A12
A13
WE#
I/O7
A18
A8
A9
A10
A11
NC
A4
1
48
A5
A3
A2
2
47
A6
3
46
A1
4
45
A7
A8
A0
5
44
OE#
NC
6
43
CE#
I/O0
7
42
UB#
LB#
8
41
I/O15
9
40
I/O14
10
11
39
I/O3
I/O13
I/O12
VDD
12
VSS
I/O4
13
14
36
VDD
35
I/O11
I/O5
I/O6
15
34
I/O10
16
33
I/O9
I/O7
17
32
I/O8
WE#
18
31
NC
I/O1
I/O2
38
37
VSS
NC
19
30
A9
A19
20
29
A10
A18
A17
21
28
A11
22
A12
A16
23
27
26
A15
24
25
A14
A13
PIN DESCRIPTIONS
A0-A19
I/O0-I/O15
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
NC
VDD
VSS
Lower-byte Control
(I/O0-I/O7)
Upper-byte Control
(I/O8-I/O15)
No Connection
Power
Ground
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Rev. 00A
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IS61WV102416BBLL
IS64WV102416BBLL
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
H
L
L
L
L
L
L
L
L
X
H
H
H
H
H
L
L
L
X
H
H
L
L
L
X
X
X
X
L
X
L
H
L
L
H
L
X
X
L
H
L
L
H
L
L
I/O0-I/O7
I/O8-I/O15
VDD Current
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
ISB1, ISB2
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS AND Operating Range
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vter m
VDD
tStg
Parameter
Terminal Voltage with Respect to VSS
V DD Related to VSS
Storage Temperature
Value
–0.5 to VDD + 0.5V
–0.3 to 4.0
–65 to +150
PT
Power Dissipation
1.0
Unit
V
V
C
W
Notes:
1.
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PIN CAPACITANCE (1)
Parameter
Input capacitance
DQ capacitance (IO0–IO15)
Symbol
CIN
CI/O
Test Condition
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
Max
6
8
Units
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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Rev. 00A
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IS61WV102416BBLL
IS64WV102416BBLL
OPERATING RANGE(1)
Range
Commercial
Industrial
Automotive
Commercial
Industrial
Ambient
Temperature
0C to +70C
-40C to +85C
-40C to +125C
0C to +70C
-40C to +85C
PART NUMBER
IS61WV102416BBLL
IS64WV102416BBLL
IS61WV102416BBLL
SPEED (MAX)
VDD
10 ns
10 ns
10 ns
8 ns
8 ns
2.4V – 3.6V
2.4V – 3.6V
2.4V – 3.6V
3.3V + 5%
3.3V + 5%
Notes:
When operated in the range of 2.4V ~3.6V, the device meets 10ns. When operated in the range of 3.3V + 5% , the device meets 8ns.
AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing and Reference Level (VREF)
Output Load Conditions
Unit
Unit
(2.2V~3.6V)
(3.3V + 5%)
0.4V to VDD -0.3V
0.4V to VDD -0.3V
1.5ns
1.5ns
VDD/2
VDD +0.05
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
Figure1
Figure2
319 ohm
3.3V
Z0 = 50 ohm
OUTPUT
50 ohm
30pF,
Including
jig
and scope
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
12/16/2014
1.5V
OUTPUT
5pF,
Including
jig
and scope
353 ohm
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IS61WV102416BBLL
IS64WV102416BBLL
DC ELECTRICAL CHARACTERISTICS
IS61(64)WV102416BBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
VDD = 2.4V ~ 3.6V
Symbol
VOH
VOL
VIH(1)
VIL(1)
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
V DD = Min., IOH = -1.0 mA
V DD = Min., IOL = 1.0 mA
VSS < VIN < VDD
VSS < VIN < VDD, Output Disabled
Min.
1.8
—
2.0
–0.3
–1
–1
Max.
—
0.4
VDD + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Min.
2.4
—
2.0
–0.3
–1
–1
Max.
—
0.4
VDD + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Notes:
1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested.
VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested.
VDD = 3.3V + 5%
Symbol
VOH
VOL
VIH(1)
VIL(1)
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
V DD = Min., IOH = -1.0 mA
V DD = Min., IOL = 1.0 mA
VSS < VIN < VDD
VSS < VIN < VDD, Output Disabled
Notes:
1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested.
VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested.
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Rev. 00A
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IS61WV102416BBLL
IS64WV102416BBLL
POWER SUPPLY CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE)
Symbol
ICC
ICC1
ISB1
ISB2
Parameter
Test Conditions
VDD Dynamic
Operating Supply
Current
VDD = MAX, IOU T = 0 mA, f = fMAX
Operating Supply
Current
VDD = MAX,
IOUT = 0 mA, f = 0
TTL Standby Current
(TTL Inputs)
VDD = MAX,
VIN = VIH or VIL
≥ VIH , f = 0
VDD = MAX,
≥ VDD - 0.2V
VIN ≥ VDD - 0.2V , or VIN ≤ 0.2V , f = 0
CMOS Standby
Current (CMOS
Inputs)
Grade
Com.
Ind.
Auto.
Typ. (2)
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Com.
Ind.
Auto.
-8
Max.
110
115
85
90
30
35
20
-10
Max.
90
95
140
60
85
90
110
30
35
70
20
25
25
-
60
Typ. (2)
Notes:
1.
2.
Unit
mA
mA
mA
mA
4
At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change.
Typical values are measured at VDD = 3.0V, TA = 25 °C and not 100% tested.
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Rev. 00A
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IS61WV102416BBLL
IS64WV102416BBLL
AC CHARACTERISTICS(6) (OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
Read Cycle Time
Address Access Time
Output Hold Time
tRC
tAA
tOHA
tACE
tDOE
tHZOE
tLZOE
tHZCE
tLZCE
tBA
tHZB
tLZB
Access Time
Access Time
to High-Z Output
to Low-Z Output
to High-Z Output
to Low-Z Output
Access Time
to High-Z Output
to Low-Z Output
-8(1)
Min Max
8
8
2.5
8
5.5
0
3
0
0
3
3
5.5
0
3
0
-
-10(1)
Min
10
2.5
0
0
0
10
0
0
Max
10
10
6.5
4
4
6.5
4
-
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
notes
2
2
2
2
2
2
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading
specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Timing Diagram
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Rev. 00A
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IS61WV102416BBLL
IS64WV102416BBLL
READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED) (
=
=VIL,
=VIH)
tRC
ADDRESS
tAA
tOHA
tOHA
I/O0-15
PREVIOUS DATA VALID
Notes:
1.
is HIGH for Read Cycle.
2. Address is valid prior to or coincident with
READ CYCLE NO. 2(1,2) (
,
Low-Z
DATA VALID
Low-Z
LOW transition.
, AND
&
CONTROLLED)
tRC
ADDRESS
tAA
tOHA
tDOE
OE#
tHZOE
CE#
tLZOE
tACE
tLZCE
DOUT
HIGH-Z
Notes:
1.
is HIGH for Read Cycle.
2. Address is valid prior to or coincident with
tHZCE
DATA VALID
LOW transition.
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Rev. 00A
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IS61WV102416BBLL
IS64WV102416BBLL
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
Write Cycle Time
tWC
tSCE
tAW
tPWB
tHA
tSA
tPWE1
tPWE2
tSD
tHD
tHZWE
tLZWE
to Write End
Address Setup Time to Write End
UB#,LB# to Write End
Address Hold from Write End
Address Setup Time
Pulse Width
Pulse Width (OE#=LOW)
Data Setup to Write End
Data Hold from Write End
LOW to High-Z Output
HIGH to Low-Z Output
-10(1)
-8(1)
Min Max
8
6.5
6.5
6.5
0
0
6.5
8
5
0
3.5
2
-
Min
10
8
8
8
0
0
8
10
6
0
2
Max
5
-
unit
notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
3
3
3
3
3
3
2, 3
2, 3
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading
specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
=LOW,
or
=LOW, and
=LOW. All signals must be in valid states to initiate
a Write, but anyone can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the write.
WRITE CYCLE NO. 1 (
CONTROLLED,
= HIGH OR LOW)
tWC
ADDRESS
VALID ADDRESS
tSCE
tHA
CE#
tAW
tPWE1
tPWE2
WE#
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA IN VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle.
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Rev. 00A
12/16/2014
goes high before
9
IS61WV102416BBLL
IS64WV102416BBLL
WRITE CYCLE NO. 2 (
CONTROLLED:
IS HIGH DURING WRITE CYCLE)
tWC
ADDRESS
VALID ADDRESS
tHA
OE#
CE#
LOW
tAW
tPWE1
WE#
tPBW
UB#,LB#
tHZWE
tSA
DOUT
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
WRITE CYCLE NO. 3 (
tHD
DATA IN VALID
CONTROLLED:
IS LOW DURING WRITE CYCLE)
tWC
ADDRESS
OE# = LOW
tHA
CE#=LOW
tAW
tPWE
WE#
tSA
tPWB
UB#, LB#
tHZWE
DOUT
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
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Rev. 00A
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tHD
DATA IN VALID
10
IS61WV102416BBLL
IS64WV102416BBLL
WRITE CYCLE NO. 4 (UB# & LB# Controlled, Back-to-Back Write)
tWC
ADDRESS
tWC
ADDRESS 1
ADDRESS 2
CE#=LOW
OE#=LOW
tSA
tHA
WE#
tHA
tSA
UB#,LB#
tPWB
tPWB
WORD 1
WORD 2
tHZWE
DOUT
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
DATA IN
VALID
tHD
DATA IN
VALID
Notes:
1. The internal Write time is defined by the overlap of CE# = LOW, UB# and/or LB# = LOW, and WE# = LOW. All signals must be in valid states to
initiate a Write, but any can be deasserted to terminate the write. The tSA, tHA, tSD, and tHD timing is referenced to the rising or falling edge of
the signal that terminates the Write.
2. Tested with OE# HIGH for a minimum of 4 ns before WE# = LOW to place the I/O in a HIGH-Z state.
3.
may be held LOW across many address cycles and the LB#, UB# pins can be used to control the Write function.
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IS61WV102416BBLL
IS64WV102416BBLL
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
VDR
VDD for Data
Retention
See Data Retention Waveform
Data Retention
Current
VDD= VDR(min),
VDD = 1.5V,
≥ VDD – 0.2V,
IDR
OPTION
Min.
Typ.(2)
2.0
Unit
3.6
V
Ind.
-
-
25
Auto.
-
-
60
tSDR
Data Retention
Setup Time
See Data Retention Waveform
0
-
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
DATA RETENTION WAVEFORM (
Max.
-
mA
ns
ns
CONTROLLED)
tSDR
DATA RETENTION MODE
tRDR
VDD
VDR
> VDD-0.2V
VSS
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IS61WV102416BBLL
IS64WV102416BBLL
ORDERING INFORMATION
IS61/64WV1M16BBLL (2.4V – 3.6V)
Industrial Range: -40°C to +85°C
Speed (ns)
10(8)
10(8)
10(8)
Notes:
1.
Order Part No.
Package
IS61WV102416BBLL-10BI
IS61WV102416BBLL-10BLI
IS61WV102416BBLL-10TLI
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I), Lead-free
Speed = 8ns for VDD = 3.3V + 5% . Speed = 10 ns for VDD = 2.4V – 3.6V
Automotive (A3) Range: –40°C to +125°C
Speed (ns)
10
10
10
Order Part No.
Package
IS64WV102416BBLL-10BA3
IS64WV102416BBLL-10BAL3
IS64WV102416BBLL-10CTLA3
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I), Copper Lead frame, Lead-free
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IS61WV102416BBLL
IS64WV102416BBLL
PACKAGE INFORMATION
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IS61WV102416BBLL
IS64WV102416BBLL
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