IRF3205Z/ZS/ZL
Features
l
l
l
l
l
HEXFET® Power MOSFET
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
D
VDSS = 55V
RDS(on) = 6.5mΩ
G
Description
This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of
applications.
ID = 75A
S
D2Pak
IRF3205ZS
TO-220AB
IRF3205Z
TO-262
IRF3205ZL
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
110
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
IDM
75
440
PD @TC = 25°C Power Dissipation
170
W
Linear Derating Factor
VGS
Gate-to-Source Voltage
EAS (Thermally limited) Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
EAS (Tested )
1.1
± 20
W/°C
V
180
mJ
78
c
d
c
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
-55 to + 175
°C
Thermal Resistance
i
Parameter
RθJC
Junction-to-Case
RθCS
Case-to-Sink, Flat Greased Surface
RθJA
Junction-to-Ambient
Junction-to-Ambient (PCB Mount)
A
mJ
Mounting Torque, 6-32 or M3 screw
i
250
See Fig.12a, 12b, 15, 16
g
Soldering Temperature, for 10 seconds
RθJA
h
A
i
j
300 (1.6mm from case )
y
y
10 lbf in (1.1N m)
Typ.
Max.
Units
–––
0.90
°C/W
0.50
–––
–––
62
–––
40
1 / 12
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IRF3205Z/ZS/ZL
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
55
–––
–––
ΔV(BR)DSS/ΔTJ
Breakdown Voltage Temp. Coefficient
–––
0.051
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
4.9
6.5
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
gfs
IDSS
Forward Transconductance
71
–––
–––
S
VDS = 25V, ID = 66A
Drain-to-Source Leakage Current
–––
–––
20
μA
VDS = 55V, VGS = 0V
–––
–––
250
IGSS
Gate-to-Source Forward Leakage
–––
–––
200
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-200
V
VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 66A
V
e
VDS = VGS, ID = 250μA
VDS = 55V, VGS = 0V, TJ = 125°C
VGS = -20V
Qg
Total Gate Charge
–––
76
110
Qgs
Gate-to-Source Charge
–––
21
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
30
–––
VGS = 10V
td(on)
Turn-On Delay Time
–––
18
–––
VDD = 28V
tr
Rise Time
–––
95
–––
td(off)
Turn-Off Delay Time
–––
45
–––
tf
Fall Time
–––
67
–––
VGS = 10V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
Ciss
Input Capacitance
–––
3450
–––
and center of die contact
VGS = 0V
Coss
Output Capacitance
–––
550
–––
Crss
Reverse Transfer Capacitance
–––
310
–––
Coss
Output Capacitance
–––
1940
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
430
–––
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
640
–––
VGS = 0V, VDS = 0V to 44V
ID = 66A
nC
VDS = 44V
e
ID = 66A
ns
nH
RG = 6.8 Ω
e
VDS = 25V
pF
ƒ = 1.0MHz
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
75
ISM
(Body Diode)
Pulsed Source Current
–––
–––
440
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
trr
Reverse Recovery Time
–––
28
42
ns
Qrr
Reverse Recovery Charge
–––
25
38
nC
ton
Forward Turn-On Time
2 / 12
c
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 66A, VGS = 0V
TJ = 25°C, IF = 66A, VDD = 25V
di/dt = 100A/μs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF3205Z/ZS/ZL
1000
100
1000
VGS
10
4.5V
1
0.1
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
100
4.5V
20μs PULSE WIDTH
Tj = 25°C
1
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
10
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
120
T J = 25°C
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current ( A)
VDS, Drain-to-Source Voltage (V)
T J = 175°C
100
10
VDS = 25V
20μs PULSE WIDTH
1
4.0
5.0
6.0
7.0
8.0
9.0
10.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
3 / 12
20μs PULSE WIDTH
Tj = 175°C
T J = 175°C
100
80
T J = 25°C
60
40
20
VDS = 10V
20μs PULSE WIDTH
0
11.0
0
20
40
60
80
100
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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IRF3205Z/ZS/ZL
6000
20
5000
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C, Capacitance (pF)
C oss = C ds + C gd
4000
Ciss
3000
2000
1000
Coss
Crss
VDS= 44V
VDS= 28V
VDS= 11V
16
12
8
4
0
0
1
ID= 66A
10
0
100
1000.0
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
60
80
100
120
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
TJ = 175°C
100.0
40
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
100
10.0
T J = 25°C
1.0
VGS = 0V
0.1
0.2
0.6
1.0
1.4
1.8
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4 / 12
20
100μsec
10
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
2.2
1
10msec
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF3205Z/ZS/ZL
120
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
LIMITED BY PACKAGE
ID , Drain Current (A)
100
80
60
40
20
0
25
50
75
100
125
150
175
T C , Case Temperature (°C)
ID = 66A
VGS = 10V
2.0
1.5
1.0
0.5
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
1
Thermal Response ( Z thJC )
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5 / 12
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IRF3205Z/ZS/ZL
DRIVER
L
VDS
D.U.T
RG
20V
VGS
+
V
- DD
IAS
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
350
15V
TOP
300
BOTTOM
ID
27A
47A
66A
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J, Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
L
DUT
0
1K
VCC
VGS(th) Gate threshold Voltage (V)
10 V
ID = 250μA
3.0
2.0
1.0
-75 -50 -25
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit
6 / 12
Fig 14. Threshold Voltage Vs. Temperature
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IRF3205Z/ZS/ZL
Avalanche Current (A)
1000
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Δ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
0.05
10
0.10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
200
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 66A
160
120
80
40
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
7 / 12
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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IRF3205Z/ZS/ZL
D.U.T
Driver Gate Drive
+
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8 / 12
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IRF3205Z/ZS/ZL
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
1
2
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
3
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
3X
1.40 (.055)
3X
1.15 (.045)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE AS SEMBLY LINE "C"
PART NUMBER
ASS EMBLY
LOT CODE
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
For GB Production
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
ASS EMBLED ON WW 19, 1997
IN T HE AS SEMBLY LINE "C"
PART NUMBER
LOT CODE
DAT E CODE
9
9 / 12
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IRF3205Z/ZS/ZL
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
THIS IS AN IRF 530S WITH
LOT CODE 8024
ASS EMBLED ON WW 02, 2000
IN THE ASS EMBLY LINE "L"
PART NUMBER
F 530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
AS SEMBLY
LOT CODE
For GB Production
THIS IS AN IRF 530S WITH
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN THE ASS EMBLY LINE "L"
PART NUMBER
F530S
LOT CODE
10 / 12
DATE CODE
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IRF3205Z/ZS/ZL
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
IGBT
1- GATE
2- COLLECTOR
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASS EMBLY LINE "C"
PART NUMBER
ASS EMBLY
LOT CODE
11 / 12
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
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IRF3205Z/ZS/ZL
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Notes:
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
max. junction temperature. (See fig. 11).
avalanche performance.
Limited by TJmax, starting TJ = 25°C, L = 0.08mH This value determined from sample failure population. 100%
RG = 25Ω, IAS = 66A, VGS =10V. Part not
tested to this value in production.
recommended for use above this value.
This is only applied to TO-220AB pakcage.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
This is applied to D2Pak, when mounted on 1" square PCB (FR Coss eff. is a fixed capacitance that gives the
4 or G-10 Material). For recommended footprint and soldering
same charging time as Coss while VDS is rising
techniques refer to application note #AN-994.
from 0 to 80% VDSS .
Repetitive rating; pulse width limited by
TO-220AB package is not recommended for Surface Mount Application.
12 / 12
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