CLC5632 Dual, High Output, Programmable Gain Buffer General Description The CLC5632 is a dual, low cost, high speed (130MHz) buffer which features user programmable gains of +2, +1, and −1V/V. The CLC5632 also has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (3.0mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear phase response up to one half of the −3dB frequency. The CLC5632 offers 0.1dB gain flatness to 30MHz and differential gain and phase errors of 0.08% and 0.02˚. These features are ideal for professional and consumer video applications. The CLC5632 offers superior dynamic performance with a 130MHz small-signal bandwidth, 410V/µs slew rate and 5.0ns rise/fall times (2Vstep). The combination of low quiescent power, high output current drive, and high speed performance make the CLC5632 well suited for many battery powered personal communication/computing systems. The ability to drive low impedance, highly capacitive loads, makes the CLC5632 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC5632 will drive a 100Ω load with only −82/−69dBc second/third harmonic distortion (AV = +2, VOUT = 2VPP, f = 1MHz). With a 25Ω load, and the same conditions, it produces only −71/−73dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high resolution A/D converters, the CLC5632 provides excellent −86/−96dBc second/third harmonic distortion (AV = +2, VOUT = 2VPP, f = 1MHz, RL = 1kΩ) and fast settling time. n n n n n n n n 0.08%, 0.02˚ differential gain, phase 3.0mA/ch supply current 130MHz bandwidth (Av =+2) −86/−96dBc HD2/HD3 (1MHz) 17ns settling to 0.05% 410V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V to ± 5V supplies Applications n n n n n n n Video line driver Coaxial cable driver Twisted pair driver Transformer/coil driver High capacitive load driver Portable/battery powered applications A/D driver Maximum Output Voltage vs. RL Features DS015003-1 n 130mA output current Connection Diagram DS015003-3 Pinout DIP & SOIC © 2000 National Semiconductor Corporation DS015003 www.national.com CLC5632 Dual, High Output, Programmable Gain Buffer December 2000 CLC5632 Typical Application DS015003-2 Differential Line Driver with Load Impedance Conversion Ordering Information Package Temperature RangeIndustrial −40˚C to +85˚C Packaging Marking Transport Media NSC Drawing 8-pin MDIP CLC5632IN CLC5632IN Rails N08E M08A 8-pin SOIC www.national.com CLC5632IM CLC5632IM Rails CLC5632IMX CLC5632IM 2.5k Units Tape and Reel 2 Lead Temperature (Soldering 10 sec) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Ratings Supply Voltage (VCC-VEE) Output Current (See note 4) Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Thermal Resistance Package MDIP SOIC +14V 140mA VEE to VCC +150˚C −65˚C to +150˚C +300˚C (θJC) 65˚C/W 50˚C/W (θJA) 130˚C/W 145˚C/W +5 Electrical Characteristics (AV = +2, RL = 100Ω, VS = +5V (Note 5), VCM = VEE + (VS/2), RL tied to VCM; Unless Specified). Symbol Parameter Ambient Temperature Conditions CLC5632IN/IM Typ Min/Max Ratings (Note 2) Units +25˚C +25˚C 0 to 70˚C −40 to 85˚C Frequency Domain Response -3dB Bandwidth VO =0.5VPP 100 70 65 65 MHz VO =2.0VPP 90 75 72 70 MHz −0.1dB Bandwidth VO =0.5VPP 23 20 20 16 MHz Gain Peaking < 200MHz, VO =0.5VPP < 30MHz, VO =0.5VPP < 30MHz, VO = 0.5VPP 0 0.5 0.9 1.0 dB Gain Rolloff Linear Phase Deviation 0.2 0.4 0.6 0.6 dB 0.12 0.3 0.4 0.4 deg Differential Gain NTSC, RL = 150Ω to −1V 0.05 – – – % Differential Phase NTSC, RL =150Ω to −1V 0.15 – – – deg Rise and Fall Time 2V Step 4.8 6.4 6.8 7.3 ns Settling Time to 0.05% 1V Step 20 24 40 60 ns Overshoot 2V Step 5 7 11 14 % Slew Rate 2V Step 290 170 150 140 V/µs 2VPP, 1MHz −72 −69 −66 −66 dBc Time Domain Response Distortion And Noise Response 2nd Harmonic Distortion 2VPP, 1MHz; RL = 1kΩ −77 −75 −72 −72 dBc 2VPP, 5MHz −63 −56 −52 −52 dBc 2VPP,1MHz −85 −82 −79 −79 dBc 2VPP, 1MHz; RL = 1kΩ −81 −78 −75 −75 dBc 2VPP, 5MHz −66 −60 −58 −58 dBc Voltage (eni) > 1MHz 3.4 4.4 4.9 4.9 nV/ Non-Inverting Current (ibn) > 1MHz 6.3 8.2 9.0 9.0 pA/ Inverting Current (ibi) > 1MHz 8.7 11.3 12.4 12.4 pA/ 10MHz, 1VPP −80 – – – 3rd Harmonic Distortion Equivalent Input Noise Crosstalk (Input Referred) dB Static, DC Performance Input Offset Voltage (Note 3) Average Drift Input Bias Current (Non-Inverting) (Note 3) Average Drift 3 13 30 35 35 mV 80 – – – µV/˚C 5 18 24 24 µA 30 – – – nA/˚C www.national.com CLC5632 Absolute Maximum Ratings (Note 1) CLC5632 +5 Electrical Characteristics (Continued) (AV = +2, RL = 100Ω, VS = +5V (Note 5), VCM = VEE + (VS/2), RL tied to VCM; Unless Specified). Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units Static, DC Performance ± 0.3 Gain Accuracy Internal Resistors (Rf, Rg) ± 2.0 ± 26% ± 2.0 ± 30% % 1000 ± 1.5 ± 20% Ω Power supply Rejection Ratio DC 48 45 43 43 dB Common Mode Rejection Ratio DC 46 44 42 42 dB Supply Current (Note 3) RL = ∞ 3.0 3.4 3.6 3.6 mA Input Resistance (Non-Inverting) 0.38 0.27 0.24 0.24 MΩ Input Capacitance (Non-Inverting) 2.2 3.3 3.3 3.3 pF Input Voltage Range, High 4.2 4.1 4.0 4.0 V Input Voltage Range, Low 0.8 0.9 1.0 1.0 V Miscellaneous Performance Output Voltage Range, High RL = 100Ω 4.0 3.9 3.8 3.8 V Output Voltage Range, Low RL = 100Ω 1.0 1.1 1.2 1.2 V Output Voltage Range, High RL = ∞ 4.1 4.0 4.0 3.9 V Output Voltage Range, Low RL = ∞ 0.9 1.0 1.0 1.1 V 100 80 65 40 mA 400 600 600 600 mΩ Output Current (Note 4) Output Resistance, Closed Loop DC ± 5 Electrical Characteristics (AV = +2, RL = 100Ω, VCC = ± 5V; Unless Specified). Symbol Parameter Ambient Temperature Conditions CLC5602IN/IM Typ Min/Max Ratings (Note 2) Units +25˚C +25˚C 0 to 70˚C −40 to 85˚C VO =1.0VPP 130 100 90 90 MHz VO =4.0VPP 70 55 52 50 MHz −0.1dB Bandwidth VO = 1.0VPP 30 25 20 20 MHz Gain Peaking < 200MHz, VO = 0 0.5 0.9 1.0 dB 0.1 0.3 0.5 0.5 dB Frequency Domain Response -3dB Bandwidth 1.0VPP Gain Rolloff < 300MHz, VO = 1.0VPP Linear Phase Deviation < 30MHz, VO = 1.0VPP 0.1 0.2 0.3 0.3 deg Differential Gain NTSC, RL = 150Ω 0.08 0.16 – – % Differential Phase NTSC, RL = 150Ω 0.02 0.04 – – deg 2V Step 5.0 6.5 7.0 7.7 ns ns Time Domain Response Rise and Fall Rime Settling Time to 0.05% 2V Step 17 28 40 60 Overshoot 2V Step 14 17 18 19 % Slew Rate 2V Step 410 310 240 225 V/µs dBc Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion www.national.com 2VPP,1MHz −82 −74 −72 −72 2VPP, 1MHz; RL =1kΩ −86 −82 −80 −68 dBc 2VPP, 5MHz −66 −61 −59 −59 dBc 2VPP,1MHz −69 −63 −61 −68 dBc 2VPP, 1MHz; RL = 1KΩ −96 −91 −88 −88 dBc 2VPP, 5MHz −71 −66 −64 −64 dBc 4 CLC5632 ± 5 Electrical Characteristics (Continued) (AV = +2, RL = 100Ω, VCC = ± 5V; Unless Specified). Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units Distortion And Noise Response Equivalent Input Noise Voltage (eni) > 1MHz 3.4 4.4 4.9 4.9 nV/ Non-Inverting Current (ibn) > 1MHz 6.3 8.2 9.0 9.0 pA/ Inverting Current (ibi) > 1MHz 8.7 11.3 12.4 12.4 pA/ 10MHz, 1VPP −80 – – – Crosstalk (Input Referred) dB Static, DC Performance Output Offset Voltage 7 30 35 35 mV Average Drift 80 – – – µV/˚C Input Bias Current (Non-Inverting) 5 18 25 25 µA Average Drift Gain Accuracy Internal Resistor (Rf, Rg) 40 – – – nA/˚C ± 0.3 ± 2.0 ± 26% ± 2.0 ± 30% % 1000 ± 1.5 ± 20% Ω Power Supply Rejection Ratio DC 48 45 43 43 dB Common Mode Rejection Ratio DC 47 45 43 43 dB Supply Current RL = ∞ 3.2 3.8 4.0 4.0 mA Input Resistance (Non-Inverting) 0.50 0.35 0.31 0.31 MΩ Input Capacitance (Non-Inverting) 1.9 2.85 2.85 2.85 pF ± 4.2 ± 3.8 ± 4.0 ± 4.1 ± 3.6 ± 3.8 ± 4.1 ± 3.6 ± 3.8 ± 4.0 ± 3.5 ± 3.7 V 130 100 80 50 mA 400 600 600 600 mΩ Miscellaneous Performance Common-Mode Input Range Output Voltage Range RL = 100Ω Output Voltage Range RL = ∞ Output Current (Note 4) Output Resistance, Closed Loop DC V V Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Note 4: The short circuit current can exceed the maximum safe output current Note 5: VS = VCC − VEE 5 www.national.com (AV = +2, RL = 100Ω, VS = +5V (Note 5), VCM = VEE + (VS/2), RL tied to VCM; Unless Specified). Frequency Response vs. RL Phase (deg) Vo = 0.5Vpp Av = +1 Gain Av = -1 Phase Magnitude (1dB/div) Vo = 0.5Vpp Phase (deg) Normalized Magnitude (1dB/div) Non-Inverting Frequency Response 0 -45 Av = +2 -90 RL = 1kΩ Gain Phase 0 -90 RL = 25Ω -180 RL = 100Ω -270 -135 -360 -180 -450 1M -225 1M 10M 10M 100M Frequency (Hz) 100M Frequency (Hz) DS015003-5 DS015003-4 Gain Flatness & Linear Phase Frequency Response vs. VO (AV = 2) 0.7 Magnitude (0.5dB/div) 0.6 0.5 0.2 Phase Vo = 0.1Vpp Magnitude (1dB/div) 0.3 Phase (deg) 0.4 Gain 0.1 0 Vo = 1Vpp Vo = 2Vpp Vo = 2.5Vpp -0.1 10 0 20 30 Frequency (MHz) 1M 10M 100M Frequency (Hz) DS015003-6 DS015003-7 Frequency Response vs. VO (AV = 1) Frequency Response vs. VO (AV = −1) Vo = 0.1Vpp Magnitude (1dB/div) Vo = 0.1Vpp Magnitude (1dB/div) CLC5632 +5V Typical Performance Characteristics Vo = 1Vpp Vo = 2Vpp Vo = 2.5Vpp 1M 10M 10M 100M Frequency (Hz) DS015003-8 www.national.com Vo = 2Vpp Vo = 2.5Vpp 1M 100M Frequency (Hz) Vo = 1Vpp DS015003-9 6 (AV = +2, RL = 100Ω, VS = +5V (Note 5), VCM = VEE + (VS/2), RL tied to VCM; Unless Specified).. (Continued) PSRR & CMRR Equivalent Input Noise Noise Voltage (nV/√Hz) CMRR 50 PSRR 40 30 20 10 0 10 3.5 Inverting Current 8.7pA/√Hz 3.4 7.5 Non-Inverting Current 7pA/√Hz Voltage 3.35nV/√Hz 5 3.3 2.5 3.2 1k 10k 100k 1M 10k 100M 10M Noise Current (pA/√Hz) PSRR & CMRR (dB) 12.5 3.6 60 100k Frequency (Hz) 1M 10M Frequency (Hz) DS015003-10 2nd & 3rd Harmonic Distortion DS015003-11 2nd & 3rd Harmonic Distortion, RL = 25Ω -30 -50 Vo = 2Vpp -40 Distortion (dBc) Distortion (dBc) -60 3rd RL = 1kΩ -70 2nd RL = 1kΩ -80 2nd RL = 100Ω -90 -50 2nd, 10MHz -60 3rd, 1MHz -70 3rd RL = 100Ω -100 3rd, 10MHz 2nd, 1MHz -80 1M 0 10M 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) Frequency (Hz) DS015003-12 2nd & 3rd Harmonic Distortion, RL = 100Ω DS015003-13 2nd & 3rd Harmonic Distortion, RL = 1kΩ -50 -50 3rd, 10MHz -60 3rd, 10MHz Distortion (dBc) Distortion (dBc) -60 2nd, 10MHz -70 2nd, 1MHz -80 2nd, 10MHz -70 2nd, 1MHz -80 -90 3rd, 1MHz -100 -90 3rd, 1MHz -110 -100 0 0 0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) Output Amplitude (Vpp) DS015003-15 DS015003-14 7 www.national.com CLC5632 +5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VS = +5V (Note 5), VCM = VEE + (VS/2), RL tied to VCM; Unless Specified).. (Continued) Closed Loop Output Resistance Large & Small Signal Pulse Response Output Voltage (0.05V/div) 100 VCC = ±5V Output Resistance (Ω) Large Signal Small Signal 10 1 0.1 0.01 Time (10ns/div) 10k DS015003-16 100k 1M 10M 100M Frequency (Hz) DS015003-17 4.0 4.0 3.5 3.0 3.0 2.0 VIO 2.5 IBN (µA) Offset Voltage VIO (mV) IBN & VIO vs. Temperature 1.0 IBN 2.0 0 -60 -20 20 60 100 140 Temperature (ϒC) DS015003-18 ± 5V Typical Performance Characteristics Frequency Response (AV = +2, RL = 100Ω, VCC = ± 5V; Unless Specified) Frequency Response vs. RL Phase (deg) Av = +1 Av = -1 Gain Phase Vo = 1.0Vpp Magnitude (1dB/div) Vo = 1.0Vpp 0 -45 -90 Av = +2 -135 RL = 1kΩ Gain RL = 100Ω Phase 0 -90 -180 RL = 25Ω -270 -180 -360 -225 1M 10M -450 1M 100M Frequency (Hz) 10M 100M Frequency (Hz) DS015003-19 www.national.com Phase (deg) Normalized Magnitude (1dB/div) CLC5632 +5V Typical Performance Characteristics DS015003-20 8 CLC5632 ± 5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC = ± 5V; Unless Specified) (Continued) Gain Flatness & Linear Phase Frequency Response vs. VO (AV = 2) 0.4 Magnitude (0.1dB/div) Vo = 0.1Vpp 0.2 0.1 Phase (deg) Gain Magnitude (1dB/div) 0.3 Phase 0 Vo = 1Vpp Vo = 5Vpp Vo = 2Vpp -0.1 0 5 10 15 20 1M 30 25 100M 10M Frequency (Hz) Frequency (MHz) DS015003-22 DS015003-21 Frequency Response vs. VO (AV = 1) Frequency Response vs. VO (AV = −1) Vo = 1Vpp Vo = 1Vpp Magnitude (1dB/div) Magnitude (1dB/div) Vo = 0.1Vpp Vo = 5Vpp Vo = 2Vpp 1M 10M 100M Vo = 0.1Vpp Vo = 5Vpp Vo = 2Vpp 1M 10M Frequency (Hz) 100M Frequency (Hz) DS015003-23 Large & Small Signal Pulse Response DS015003-24 Differential Gain & Phase -0.025 0.1 Gain Pos Sync -0.050 Gain (%) Small Signal 0.05 -0.075 0 Phase Pos Sync -0.100 -0.05 Phase Neg Sync Gain Neg Sync -0.125 -0.1 -0.150 Time (20ns/div) Phase (deg) Output Voltage (0.5V/div) Large Signal -0.15 1 2 3 4 Number of 150 Ω Loads DS015003-25 DS015003-26 9 www.national.com 2nd & 3rd Harmonic Distortion vs. Frequency (AV = +2, RL = 100Ω, VCC = ± 5V; Unless 2nd & 3rd Harmonic Distortion, RL = 25Ω -40 3rd, 10MHz Distortion (dBc) -50 2nd, 10MHz -60 2nd, 1MHz -70 3rd, 1MHz -80 -90 0 1 2 3 4 5 Output Amplitude (Vpp) DS015003-28 DS015003-27 2nd & 3rd Harmonic Distortion, RL = 100Ω 2nd & 3rd Harmonic Distortion, RL = 1kΩ -55 -50 3rd, 10MHz -60 -65 Distortion (dBc) Distortion (dBc) -60 -70 2nd, 10MHz -75 -80 2nd, 1MHz -85 -70 3rd, 10MHz 2nd, 10MHz -80 2nd, 1MHz -90 -100 3rd, 1MHz -90 -95 3rd, 1MHz -110 0 0.5 1 1.5 2 2.5 0 1 Output Amplitude (Vpp) 2 3 4 5 Output Amplitude (Vpp) DS015003-29 Short Term Settling Time DS015003-30 Long Term Settling Time 0.2 0.2 Vo (% Output Step) 0.15 0.15 Vo (% Output Step) CLC5632 ± 5V Typical Performance Characteristics Specified) (Continued) 0.1 0.05 0 -0.05 -0.1 0.1 0.05 0 -0.05 -0.1 -0.15 -0.15 -0.2 1µ -0.2 1 10 100 1000 100µ 1m 10m 100m Time (s) 10000 DS015003-32 Time (ns) DS015003-31 www.national.com 10µ 10 CLC5632 ± 5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC = ± 5V; Unless Specified) (Continued) Channel Matching 3.0 3.8 2.5 3.6 2.0 3.4 1.5 VOS 3.2 V0 = 1Vpp Magnitude (0.5dB/div) 4.0 IBN (µA) Offset Voltage VOS(mV) IBN & VOS vs. Temperature 1.0 IBN 3.0 0.5 2.8 Channel 2 Channel 1 0 -60 -20 20 60 100 1M 140 10M 100M Frequency (Hz) Temperature (ϒC) DS015003-34 DS015003-33 Input Referred Crosstalk Pulse Crosstalk -20 Active Channel Amplitude (0.2V/div) Magnitude (dB) -40 -60 -80 Inactive Output Channel Inactive Channel Amplitude (20mV/div) Active Output Channel Vo = 1Vpp -100 Time (10ns/div) -120 1M 10M DS015003-36 100M Frequency (Hz) DS015003-35 Application Division CLC5632 Operation The CLC5632 is a current feedback buffer fabricated in an advanced complementary bipolar process. The CLC5632 operates from a single 5V supply or dual ± 5V supplies. Operating from a single 5V supply, the CLC5632 has the following features: • Gains of ± 1, −1, and 2V/V are achievable without external resistors • Provides 100mA of output current while consuming only 15mW of power • • Offers low −79/−81dBc 2nd & 3rd harmonic distortion Current Feedback Amplifiers Some of the key features of current feedback technology are: • Independence of AC bandwidth and voltage gain • Inherently stable at unit gain • Adjustable frequency response with feedback resistor • High slew rate • Fast Settling Current feedback operation can be described using a simple equation. The voltage gain for non-inverting or inverting current feedback amplifier is approximated by Equation 1. Provides BW80MHz and 1MHz distortion < −75dBc at VO = 2VPP Vo = Vin The CLC5632 performance is further enhanced in ± 5V supply applications as indicated in the ± 5V Electrical Characteristics table and the ± 5V Typical Performance plots. If gains other than +1, −1, or +2V/V are required, then the CLC5602 can be used. The CLC5602 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors. Av Rf 1+ Z(jω ) (1) where: • • • 11 AV is the closed loop DC voltage gain Rf is the feedback resistor Z(jω) is the CLC5632’s open loop transimpedance gain www.national.com DC Coupled Single Supply Operation Figure 1, Figure 2, and Figure 3 on the following page, show the recommended configurations for input signals that remain above 0.8V DC. (Continued) • Z(jω)/Rf is the loop gain The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the −3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: • Decreases loop gain • Decreases bandwidth • Reduces gain peaking • Lowers pulse response overshoot • Affects frequency response phase linearity CLC5632 Design Information Closed Loop Gain Selection The CLC5632 is a current feedback op amp with Rf = Rg = 1kΩ on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and −1V/V by connecting pins 2 and 3 (or 5 and 6) as described in the chart below. DS015003-39 FIGURE 1. DC Coupled, AV = −1V/V Configuration VCC 6.8µF Gain AV Input Connections Non-Inverting (pins 3, 5) Inverting (pins 2, 6) −1V/V ground input signal +1V/V input signal NC (open) + Note: Rt and RL are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown. Vo 0.1µF 8 1 1kΩ RL 2 1kΩ - 7 + input signal Vcm Vin ground The gain accuracy of the CLC5632 is excellent and stable over temperature change. The internal gain setting resistors, Rf and Rg are diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of - 2000ppm/˚C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer. Single Supply Operation (VCC = +5V, VEE = GND) 1kΩ 1kΩ 6 - Rt 4 5 CLC5632 Vcm DS015003-40 FIGURE 2. DC Coupled, AV = +1V/V Configuration VCC 6.8µF The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (VCM) of 2.5V. VCM is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5632 is typically +0.8V to +4.2V. The typical output range with RL = 100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown. Vo 8 1 RL + 0.1µF 1kΩ Vcm 2 1kΩ - 7 + Vcm Vin 3 1kΩ 1kΩ 6 - www.national.com 3 Rt Vcm 4 + +2V/V + CLC5632 Application Division 5 CLC5632 DS015003-41 FIGURE 3. DC Coupled, AV = +2V/V Configuration 12 Dual Supply Operation The CLC5632 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figure 7, , and . (Continued) AC Coupled Single Supply Operation Figure 4, Figure 5, and Figure 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. VCC 6.8µF + VCC 6.8µF + Note: Channel 2 not shown. Vo 0.1µF 8 1 1kΩ Vin 1kΩ 2 Rt - R 7 1kΩ 1kΩ 3 Rb + 3 4 4 0.1µF 5 + CLC5632 1kΩ 6 - R - 7 + 1kΩ CC 1kΩ 2 5 CLC5632 Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ. Channel 2 not shown. + Vo = − Vin + 2.5 Low frequency cutoff = where Rg = 1kΩ. 6.8µF 1 , 2πR gCC 6 1kΩ - VCC Vin 0.1µF 8 1 + Vo VEE DS015003-45 DS015003-42 FIGURE 7. Dual Supply, AV = −1V/V Configuration FIGURE 4. AC Coupled, AV = −1V/V Configuration The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V) VCC 6.8µF + VCC Vo 6.8µF 1kΩ + Note: Channel 2 not shown. 0.1µF 8 1 1kΩ 2 - 7 + 1kΩ 2 3 - Rt 7 1kΩ 1kΩ 4 4 6 1kΩ 0.1µF 6 5 CLC5632 Note: Channel 2 not shown. - R 1kΩ + + 5 + Vin 3 - 1kΩ R CC Vin 0.1µF 8 1 + Vo VCC CLC5632 6.8µF Vo = Vin + 2.5 Low frequency cutoff = where Rin = VEE 1 , 2πRinCC R >> R source R 2 DS015003-46 FIGURE 8. Dual Supply, AV = +1V/V Configuration DS015003-43 FIGURE 5. AC Coupled, AV = +1V/V Configuration VCC 6.8µF + VCC 6.8µF + Note: Channel 2 not shown. Vo 8 1 0.1µF 1kΩ R C 2 1kΩ - Vin 7 3 1kΩ + 3 1kΩ 1kΩ Rt 6 4 - R - 7 + 4 + CC 1kΩ 2 1kΩ 1kΩ 6 - Vin 0.1µF 8 1 + Vo VCC CLC5632 5 0.1µF 5 CLC5632 Note: Channel 2 not shown. Vo = 2Vin + 2.5 Low frequency cutoff = where Rin = R 2 + 1 , 2πRinCC R >> Rsource 6.8µF VEE DS015003-44 DS015003-47 FIGURE 6. AC Coupled, AV = +2V/V Configuration FIGURE 9. Dual Supply, AV = +2V/V Configuration 13 www.national.com CLC5632 Application Division (Continued) R6 Load Termination R4 The CLC5632 can source and sink near equal amounts of current. For optimum performance, the load should be tied to VCM. Z0 8 1 Z0 Vo C6 R7 1kΩ R5 R1 Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5632 will improve stability and settling performance. The Frequency Response vs. CL plot, shown below in Figure 10, gives the recommended series resistance value for optimum flatness at various capacitive loads. Z0 2 3 R3 R2 - 7 + 4 V2 +- 1kΩ 1kΩ 1kΩ 6 - V1 +- + CLC5632 Application Division 5 CLC5632 Note: Channel 2 not shown. DS015003-49 FIGURE 11. Transmission Line Matching Power Dissipation Follow these steps to determine the power consumption of the CLC5632: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC−VEE) 2. Calculate the RMS power at the output stage: PO = (VCC −Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp+PO The maximum power that the DIP and SOIC, packages can dissipate at a given temperature is illustrated in Figure 12. The power derating curve for any CLC5632 package can be derived by utilizing the following equation: DS015003-48 where Tamb = Ambient temperature (˚C) θJA = Thermal resistance, from junction to ambient, for a given package (˚C/W) FIGURE 10. Frequency Response vs. CL Transmission Line Matching One method for matching the characteristic impedance (ZO) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 11 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-Inverting gain applications: • Connect pin 2 as indicated in the table in the Closed Loop Gain Selection section. • • Make R1, R2, R6, and R7 equal to ZO. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Inverting gain applications: • Connect R3 directly to ground. • Make the resistors R4, R6, and R7 equal to ZO. • Make R5 \ Rg = ZO. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. www.national.com DS015003-51 FIGURE 12. Power Derating Curve Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC5632 (CLC730038-DIP, CLC730036-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: 14 • Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. • Place the 6.8µF capacitors within 0.75 inches of the power pins. • Place the 0.1µF capacitors less than 0.1 inches from the power pins. CLC5632 Application Division (Continued) • Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. • • Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information A data sheet is available for the CLC730038/CLC730036 evaluation boards. The evaluation board data sheets provide: • Evaluation board schematics • Evaluation board layouts • General information about the boards The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Special Evaluation Board Considerations for the CLC5632 To optimize off-isolation of the CLC5632, cut the Rf trace on both the CLC730038 and the CLC730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and the output. Figure 13 shows where to cut both evaluation boards for improved off-isolation. DS015003-61 DS015003-52 FIGURE 13. Evaluation Board Changes SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: • • Support Berkeley SPICE 2G and its many derivatives Reproduce typical DC, AC, Transient, and Noise performance • Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. Application Circuits Single Supply Cable Driver Figure 14 below shows the CLC5632 driving 10m of 75Ω coaxial cable. The CLC5632 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at VO. The response after 10m of cable is illustrated in Figure 15 15 www.national.com Vo 10m of 75Ω Coaxial Cable (Continued) Rm/2 +5V 75Ω 6.8µF Vd/2 + 0.1µF 8 1 5kΩ Vin 0.1µF 0.1µF 8 1 1kΩ +5V 2 0.1µF 2 - 7 1kΩ 1kΩ 3 Rt + 3 1kΩ - 7 + Vin 1kΩ 1kΩ Zo 1kΩ 1kΩ RL UTP Rm/2 -Vd/2 6 - 75Ω Io 1:n Req 6 4 + CLC5632 5 Rt2 - 5kΩ 4 + 5 Note: Supplies and bypassing not shown. DS015003-55 CLC5632 NOTE: Channel 2 not shown FIGURE 16. Differential Line Driver with Load Impedance Conversion DS015003-53 FIGURE 14. Single Supply Cable Driver Set up the CLC5632 as a difference amplifier: • Set the Channel 1 amplifier to a gain of +1V/V • Set the Channel 2 amplifier to a gain of −1V/V Make the best use of the CLC5632’s output drive capability as follows: Vin = 10MHz, 0.5Vpp 100mV/div CLC5632 Application Division where Req is the transformed value of the load impedance, Vmax is the output Voltage Range, and Imax is the maximum Output Current. Match the line’s characteristic impedance: 20ns/div DS015003-54 FIGURE 15. Response After 10m of Cable RL = Z o Rm = Req Differential Line Driver with Load Impedance Conversion The circuit shown in the Typical Application schematic on the front page and in Figure 16, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5632’s output capabilities. The single-ended input signal is converted to a differential signal by the CLC5632. The line’s characteristic impedance is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line; other types of lines can also be driven. n= RL Req Select the transformer so that it loads the line with a value very near ZO over frequency range. The output impedance of the CLC5632 also affects the match. With an ideal transformer we obtain: where ZO(5632)(jω) is the output impedance of the CLC5632 and |ZO(5632)(jω)| << Rm. The load voltage and current will fall in the ranges: The CLC5632’s high output drive current and low distortion make it a good choice for this application. Differential Input/Differential Output Amplifier below illustrates a differential input/differential output configuration. The bypass capacitors are the only external components required. www.national.com 16 CLC5632 Application Division (Continued) -5V Vin2 0.1µF CLC5632 Vin1 6.8µF 1kΩ 1kΩ 1kΩ 6.8µF Vout2 1kΩ Vout1 0.1µF +5V Vout1 – Vout2 = (Vin1 – Vin2) x 2 DS015003-60 FIGURE 17. Differential Input/Differential Output Amplifier 17 www.national.com CLC5632 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NSC Package Number M08A 8-Pin MDIP NSC Package Number N08E www.national.com 18 CLC5632 Dual, High Output, Programmable Gain Buffer Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.