NSC CLC5665IM

N
CLC5665
Low Distortion Amplifier with Disable
General Description
Features
The CLC5665 is a low-cost, wideband amplifier that provides very
low 2nd and 3rd harmonic distortion at 1MHz (-89/-92dBc). The
great slew rate of 1800V/µs, bandwidth of 90MHz (Av = +1) and
fast disable make it an excellent choice for many high speed
multiplexing applications. Like all current feedback op amps, the
CLC5665 allows the frequency response to be optimized
(or adjusted) by the selection of the feedback resistor. For
demanding video applications, the 0.1dB bandwidth to 20MHz
and differential gain/phase of 0.05%/0.05° make the CLC5665
the preferred component for broadcast quality NTSC and PAL
video systems.
■
■
■
■
■
■
■
■
■
■
Applications
■
The large voltage swing (28Vpp), continuous output current
(85mA) and slew rate (1800V/µs) provide high-fidelity signal
conditioning for applications such as CCDs, transmission lines
and low impedance circuits.
■
■
■
■
■
■
■
xDSL driver
Twisted pair driver
Cable driver
Video distribution
CCD clock driver
Multimedia systems
DAC output buffers
Imaging systems
Non-Inverting Frequency Response
Av = 1
Rf = 698
Magnitude (1dB/div)
Gain
Av = 10
Rf = 100
Phase
Av = 2
Rf = 604
Av = 1
0
-45
Av = 50
-90
Av = 2
Av = 50
Rf = 500
1
Phase (deg)
xDSL, video distribution, multimedia and general purpose
applications will benefit from the CLC5665’s wide bandwidth and
disable feature. Power is reduced and the output becomes a high
impedance when disabled. The wide gain range of the CLC5665
makes this general purpose op amp an improved solution for
circuits such as active filters, single-to-differential-ended drivers,
DAC transimpedance amplifiers and MOSFET drivers.
0.1dB gain flatness to 20MHz (Av = +2)
90MHz bandwidth (Av = +1)
Large signal BW 25MHz
1800V/µs slew rate
0.05%/0.05° differential gain/phase
±5V, ±15V or single supplies
200ns disable to high-impedance output
Wide gain range
-89/-92dBc HD2/HD3 (RL = 500Ω)
Low cost
CLC5665
Low Distortion Amplifier with Disable
June 1999
-135
Av = 10
-180
10
100
Frequency (MHz)
DIS
+
Typical Application
Pinout
Differential Line Driver for xDSL
+
DIP & SOIC
CLC5665
-
Ro
Rf1
Vin (Vpp)
604Ω
Rg
1.2kΩ
Rf2
NC
1
Vinv
2
-
7 +Vcc
Vnon-inv
3
+
6 Vout
-Vcc
4
8 DIS
1:n
Vo = 2Vin
nVo
RL
604Ω
Ro
-
-
CLC5665
5 NC
Note: Supply and Bypassing not shown.
+
DIS
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
CLC5665 Electrical Characteristics
PARAMETERS
Ambient Temperature
CONDITIONS
CLC5665
FREQUENCY DOMAIN RESPONSE
small-signal bandwidth (Av = +1) Vout < 1.0Vpp
small-signal bandwidth
Vout < 1.0Vpp
Vout < 1.0Vpp
0.1dB bandwidth
Vout < 1.0Vpp
Vout < 1.0Vpp
large-signal bandwidth
Vout = 10Vpp
gain flatness
Vout < 1.0Vpp
peaking
DC to 10MHz
rolloff
DC to 20MHz
linear phase deviation
DC to 20MHz
differential gain
4.43MHz, RL =
4.43MHz, RL =
differential phase
4.43MHz, RL =
4.43MHz, RL =
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
(VCC = ±15V, Av = +2V/V; Rf = 604Ω, RL = 100Ω; unless specified)
150Ω
150Ω
150Ω
150Ω
Vcc
TYP
+25°C
±15
±15
±5
±15
±5
90
70
50
20
15
25
MHz
MHz
MHz
MHz
MHz
MHz
0.03
0.1
0.7
0.05
0.05
0.05
0.1
dB
dB
deg
%
%
deg
deg
5
10
35
5
1800
ns
ns
ns
%
V/µs
-89
-92
3.0
3.2
15
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
±15
±5
±15
±5
2V step
10V step
2V step
2V step
20V step
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
1Vpp,1MHz, RL = 500Ω
3rd harmonic distortion
1Vpp,1MHz, RL = 500Ω
input voltage noise
>1MHz
non-inverting input current noise >1MHz
inverting input current noise
>1MHz
DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input bias current
average drift
power-supply rejection ratio
common-mode rejection ratio
supply current
disabled
DC
DC
RL = ∞
RL = ∞
SWITCHING PERFORMANCE
turn on time
turn off time
off isolation
high input voltage
(Note 2)
10MHz
VIH
low input voltage
±15
±15, ±5
±15, ±5
1.0
25
3
10
3
10
60
60
11, 8.5
1.5
7.5
–
20
–
20
–
55
55
12
2.5
±15
±5
±15
±5
400
200
59
11.8
1.8
10.8
0.8
8.0
0.5
±12.5
±2.5
±14
±4.0
±85
non-inverting
±15, ±5
inverting
±15, ±5
VIL
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
non-inverting input capacitance
input voltage range
common mode
common mode
output voltage range
RL = ∞
RL = ∞
output current
MIN/MAX RATINGS
UNITS NOTES
+25°C
0 to 70°C -40 to 85°C
±15
±5
±15
±5
9.0
10.0
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
mA
20
20
20
20
50
50
14
2.5
50
50
15
2.5
500
800
56
12.5
2.5
10.5
0.6
550
800
56
12.7
2.7
10.0
0.1
550
800
56
ns
ns
dB
V
V
V
V
3.0
1.0
±12.3
±2.3
±13.7
±3.9
±60
2.5
1.0
±12.1
±2.2
±13.7
±3.8
±50
1.7
1.0
±11.8
±1.9
±13.6
±3.7
±45
MΩ
pF
V
V
V
V
mA
A
A
A
A
A
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
supply voltage
short circuit current
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
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Notes
A) J-level: spec is 100% tested at +25°C.
1) Output is short circuit protected to ground, however
maximum reliability is obtained if output current does not
exceed 125mA.
2) To >50dB attenuation @ 10MHz.
±16V
(see note 1)
±VCC
+150°C
-65°C to +150°C
+300°C
2
CLC5665 Typical Performance (V
CC
Inverting Frequency Response
Av = 1
Rf = 698
0
-45
Av = 50
-90
Av = 2
Av = 50
Rf = 500
1
-135
Av = 10
Av = -10
Rf = 500
Av = -2
Rf = 500
Phase
-45
Av = -50
-135
Av = -2
Av = -50
Rf = 2.5k
10
RL = 100
Phase
RL = 1k
Open-Loop Transimpedance Gain (Zs)
-90
RL = 100
1
100
10
100
Frequency (MHz)
Flatness Gain and Linear Phase
Equivalent Input Noise
100
Gain
0
90
60
Phase
80
80
70
100
60
120
50
140
40
160
Gain
Noise Voltage (nV/√Hz)
40
Phase
Inverting Current 14.8pA/√Hz
10
Non-Inverting Current 3.2pA/√Hz
Voltage 3.0nV/√Hz
1
0.001
0.01
1
0.1
10
0
100
4
8
Frequency (MHz)
12
16
1k
Gain Negative Sync
PSRR
40
0
30
-10
20
-20
20 log Ro
Phase
Positive Sync
0.06
0.04
0.10
0.06
Gain Positive Sync
1
10
0
0.03
1
100
2
IBI, IBN. VOS vs. Temperature
-0.05
6.0
4.5
5.0
4.0
4.0
3.5
3.0
3.0
IBN
2.5
2.0
IBI
1.0
2.0
VOS
0
1.5
-1.0
1.0
-0.15
-2.0
0.5
-0.2
-3.0
0
-0.1
Time (10ns/div)
-60
-20
20
60
100
50
Intercept (+dBm)
Short Term
0
60
5.0
IBI, IBN (µA)
VOS (mV)
0.1
40
30
50Ω
750Ω
750Ω
10
106
140
-10
22
20
18
16
14
Load
50Ω
Vin
10
50Ω
698Ω
698Ω
8
RL = 100Ω
Vout = 2Vpp
2nd
VCC = ±5V
-30
-40
2nd
VCC = ±15V
-50
0
5
10
15
3rd
VCC = ±15V
-60
-70
-80
3rd
VCC = ±5V
-90
20
25
30
35
Frequency (MHz)
40
45
50
RL = 500Ω
Vout = 2Vpp
-10
-20
-100
6
Harmonic Distortion vs. Frequency
0
Distortion Level (dBc)
24
Distortion Level (dBc)
0
107
Frequency (MHz)
Harmonic Distortion vs. Frequency
-1dBm Compression to Load
Pout
50Ω
20
Temperature (°C)
26
4
2-Tone, 3rd Order Intermodulation Intercept
7.0
0.15
3
Number of 150Ω Loads
Frequency (MHz)
2V output step
0.12
0.02
-40
0.01
0.18
Phase Negative Sync
-30
0
Short Term Settling Time
0.24
10
Phase (deg)
PSRR/CMRR (dB)
0.30
0.08
CMRR
50
10
0.2
100M
20
60
Time (20ns/div)
10M
1
30
20 log Ro
Small Signal Output (0.5V/div)
Small Signal
1M
Differential Gain and Phase (3.58MHz)
PSRR, CMRR and Closed Loop Ro
Large Signal
100k
Frequency (MHz)
70
0.05
10k
Frequency (MHz)
Signal Pulse Response
Large Signal Output (2V/div)
0.1k
20
Gain (%)
30
0.0001
12
Noise Current (pA/√Hz)
100
Phase (0.2°/div)
20
Phase (deg)
110
Magnitude (0.1dB/div)
120
Settling Error (%)
-135
-180
130
Compression Point (dBm)
0
-45
RL = 50
Frequency (MHz)
Frequency (MHz)
Gain (20 log)
RL = 50
-180
Av = -1
1
100
-90
Av = -10
-180
10
0
RL = 1k
Phase (deg)
Phase
Gain
Phase (deg)
Av = 2
Rf = 604
Av = 1
Phase (deg)
Av = 10
Rf = 100
Gain
Magnitude (1dB/div)
Gain
Frequency Response vs. Load
Av = -1
Rf = 500
Magnitude (1dB/div)
Non-Inverting Frequency Response
Magnitude (1dB/div)
= ±15V, Av = +2V/V; Rf = 604Ω, RL = 100Ω; unless specified)
-20
2nd
VCC = ±5V
-30
-40
2nd
VCC = ±15V
-50
-60
3rd
VCC = ±15V
-70
-80
3rd
VCC = ±5V
-90
-100
1
10
100
Frequency (MHz)
3
1
10
100
Frequency (MHz)
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VCC
Enable
Disable
CLC5665 Design Considerations
The CLC5665 is a general purpose current-feedback
amplifier for use in a variety of small- and large-signal
applications. Use the feedback resistor to fine tune the
gain flatness and -3dB bandwidth for any gain setting.
National provides information for the performance at a
gain of +2 for small and large signal bandwidths. The
plots show feedback resistor values for selected gains.
+Vcc
2kΩ
To CLC5665
Bias network
8kΩ
-R f
Rg
Figure 2: Pin 8 Equivalent Disable Circuit
Choose the resistor values for non-inverting or inverting
gain by the following steps.
+
Rin
Rs
CLC5665
Open-collector or CMOS interfaces are recommended to
drive pin 8. The turn-on and off time depends on the
speed of the digital interface.
Vo
The equivalent output impedance when disabled is
shown in Figure 3. With Rg connected to ground, the sum
of Rf and Rg dominates and reduces the disabled output
impedance. To raise the output impedance in the disabled state, connect the CLC5665 as a unity-gain
voltage follower by removing Rg. Current-feedback
op-amps need the recommended Rf in a unity-gain
follower circuit. For high density circuit layouts consider
using the dual CLC431 (with disable) or the dual CLC432
(without disable).
Rf
Rg
Figure 1: Component Identification
1)
2)
3)
4)
-Vcc
Pin 8 DISABLE
Vin
±5V
>2.7V
<0.8V
The amplifier is enabled with pin 8 left open due to the
2kΩ pull-up resistor, shown in Figure 2.
Gain
Use the following equations to set the CLC5665’s noninverting or inverting gain:
R
Non − Inverting Gain = 1 + f
Rg
Inverting Gain =
±15V
>12.7V
<10.0V
Select the recommended feedback resistor Rf.
Choose the value of Rg to set gain.
Select Rs to set the circuit output impedance.
Select Rin for input impedance and input bias.
Equivalent Impedance
in Disable
Vin
+
High Gains
Current feedback closed-loop bandwidth is independent
of gain-bandwidth-product for small gain changes. For
larger gain changes the optimum feedback register Rf is
derived by the following:
300kΩ
Vout
8pF
-
Rf = 724Ω – 60Ω (Av)
•
Rg
As gain is increased, the feedback resistor allows bandwidth to be held constant over a wide gain range. For a
more complete explanation refer to application note OA-25:
Stability Analysis of Current-Feedback Amplifiers.
Rf
1M
100k
Resistors have varying parasitics that affect circuit
performance in high-speed design. For best results, use
leaded metal-film resistors or surface mount resistors. A
SPICE model for the CLC5665 is available to simulate
overall circuit performance.
Zout (Ω)
10k
1k
100
Enable/Disable Function
The CLC5665 amplifier features an enable/disable
function that changes the output and inverting input from
low to high impedance. The pin 8 enable/disable logic
levels are as follows:
10
1
1
10
100
Frequency (MHz)
Figure 3: Equivalent Disabled Output Impedance
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4
2nd and 3rd Harmonic Distortion
To meet low distortion requirements, recognize the effect
of the feedback resistor. Increasing the feedback
resistor will decrease the loop gain and increase
distortion. Decreasing the load impedance increases 3rd
harmonic distortion more than 2nd.
+
Vin AC
C
Vout
Rin
CLC5665
Vin DC
Rf
R2
Rg
Differential Gain and Differential Phase
The CLC5665 has low DG and DP errors for video
applications. Add an external pulldown resistor to the
CLC5665’s output to improve DG and DP as seen in
Figure 4. A 604Ω Rp will improve DG and DP to 0.01%
and 0.02°.
Figure 5: Level Shifting Circuit
Multiplexing
Multiple signal switching is easily handled with the disable function of the CLC5665. Board trace capacitance
at the output pin will affect the frequency response and
switching transients. To lessen the effects of output
capacitance place a resistor (Ro) within the feedback
loop to isolate the outputs as shown in Figure 6. To match
the mux output impedance to a transmission line, add a
resistor (Rs) in series with the output.
Add Rp to
improve
DG and DP
Vin
+
Vout
Rin
CLC5665
Rs
Rp
Rg
Rf
Rg
Rf
-
-Vcc
Ro
CLC5665
Vin1
+
Figure 4: Improved DG and DP Video Amplifier
Vin2
Rin
Printed Circuit Layout
To get the best amplifier performance careful placement
of the amplifier, components and printed circuit traces
must be observed. Place the 0.1µF ceramic decoupling
capacitors less than 0.1” (3mm) from the power supply
pins. Place the 6.8µF tantalum capacitors less than
0.75” (20mm) from the power supply pins. Shorten traces
between the inverting pin and components to less
than 0.25” (6mm). Clear ground plane 0.1” (3mm) away
from pads and traces that connect to the inverting, noninverting and output pins. Do not place ground or power
plane beneath the op-amp package. National provides
literature and evaluation boards CLC730013 DIP or
CLC730027 SOIC illustrating the recommended op-amp
layout.
Vout
Rs
DIS1
DIS2
+
RL
Ro
CLC5665
Rin
-
Rf
Rg
Figure 6: Output Connection for
Multiplexing Circuits
Differential Line Driver With Load
Impedance Conversion
The circuit shown in Figure 7, operates as a differential
line driver. The transformer converts the load impedance
to a value that best matches the CLC5665’s output
capabilities. The single-ended input signal is converted
to a differential signal by the CLC5665. The line’s
characteristic impedance is matched at both the input
and the output. The schematic shows Unshielded Twisted
Pair for the transmission line; other types of lines can also
be driven.
Applications Circuits
Level Shifting
The circuit shown in Figure 5 implements level shifting by
AC coupling the input signal and summing a DC voltage.
The resistor Rin and the capacitor C set the high-pass
break frequency. The amplifier closed-loop bandwidth is
fixed by the selection of Rf. The DC and AC gains for
circuit of Figure 5 are different. The AC gain is set by the
ratio of Rf and Rg. And the DC gain is set by the parallel
combination of Rg and R2.
Rf2
Rg2
Vd/2
Vin
+
Rt1
CLC5665
-
-
CLC5665
Rf1
  R 
 Rf 
f
Vout = Vinac 1 + 
  − VinDC  R 
R
R
 2
  g 2 
Rg1
+
Rt2
-Vd/2
Rm/2
Req
1:n
Io
Zo
RL
UTP
+
Vo
-
Rm/2
Figure 7: Differential Line Driver with
Load Impedance Conversion
5
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Set up the CLC5665 as a difference amplifier. Vd is
determined by:
VinA
+
Rf1
VoB
+
RL = Z o
Rm = Req
-
Rt2
Rt2
VoutA(B) ≈ VinA(B) ⋅ A +
Select the transformer so that it loads the line with a
value very near Zo over frequency range. The output
impedance of the CLC5665 also affects the match. With
an ideal transformer we obtain:
CLC5665
VoA
+
VinB(A) 
Z o(5665) (jω ) 
R
⋅ 1 − f2 +

2
Rm1
 R g2

where A is the attenuation of the cable, Zo(5665)(jω) is
the output impedance of the CLC5665, and | Zo(5665)(jω) |
<< Rm1.
n2 ⋅ Z o(5665) ( jω )
,dB
Zo
We selected the component values as follows:
Rf1 = 1.2kΩ, the recommended value for
CLC5665 at unity gain
■ Rm1 = Zo = 50Ω, the characteristic impedance
of the transmission line
■ Rf2 = Rg2 = 750Ω ≥ Rm1, the recommended
value for the CLC5665 at Av = 2
■
where Zo(5665)(jω) is the output impedance of the
CLC5665 and |Zo(5665)(jω)| << Rm.
The load voltage and current will fall in the ranges:
Imax
n
Rf2
The receiver output voltages are:
RL
n=
Req
Io ≤
Rf1
Rg2
Rm1 is used to match the transmission line. Rf2 and Rg2
set the DC gain of the CLC5665, which is used in a
difference mode. Rt2 provides good CMRR and DC
offset. The transmitting CLC5665’s are shown in a unity
gain configuration because they consume the least
power of any gain, for a given load. For proper operation
we need Rf2 = Rg2.
Match the line’s characteristic impedance:
≤ n ⋅ Vmax
Rt1
Figure 8: Full Duplex Cable Driver
where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the
maximum Output Current.
■
R t2 = (R f2 || R g2 ) –
Rm1
= 25Ω
2
These values give excellent isolation from the other input:
VoA(B)
The CLC5665’s high output drive current and low
distortion make it a good choice for this application.
VinB(A)
≈ −38dB, f = 5.0MHz
The CLC5665 provides large output current drive, while
consuming little supply current, at the nominal bias point.
It also produces low distortion with large signal swings
and heavy loads. These features make the CLC5665 an
excellent choice for driving transmission lines.
Full Duplex Cable Driver
The circuit shown in Figure 8 below, operates as a full
duplex cable driver which allows simultaneous transmission and reception of signals on one transmission line.
The circuit on either side of the transmission line uses are
CLC5665 as a cable driver, and the second CLC5665 as
a receiver. VoA is an attenuated version of VinA, while VoB
is an attenuated version of VinB.
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CLC5665
2 ⋅ Vmax
Imax
Vo
Rg2
-
Make the best use of the CLC5665’s output drive
capability as follows:
Return Loss = −20 ⋅ log10
CLC5665
-
Rf2
VinB
+
Rm1
-

Vd
R 
R
= 2 ⋅ 1 + f1  = 2 ⋅ f2
Vin
R g2
 R g1 
Rm + Req =
Z0
Rm1
CLC5665
Rt1
6
CCD Clock Driver
Reliability Information
Transistor Count
Vin
+
RT
Rs
CLC5665
-
Vo
Package Thermal Resistance
CL
Package
Voffset
R
Plastic (IN)
Surface Mount (IM)
Rf
Rg
θJC
θJA
65°C/W
50°C/W
130°C/W
145°C/W
Ordering Information
14
Output Voltage (2V/div)
38
Model
10
CLC5665IN
CLC5665IM
CLC5665IMX
6
2
Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Description
8-pin PDIP
8-pin SOIC
8-pin SOIC tape and reel
-2
-6
-10
-14
0
50
100
150
200
Frequency (ns)
Figure 9: CCD Clock Driver
7
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CLC5665
Low Distortion Amplifier with Disable
Customer Design Applications Support
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National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
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the president of National Semiconductor Corporation. As used herein:
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sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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