LOGIC LF3311

LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
FEATURES
8 Vertical Filter Taps
Two Operating Modes: Dimensionally Separate and Orthogonal
Supports Interleaved Data Streams
Horizontal Filter Supports Decimation up to
16:1 for Increasing Number of Filter Taps
3.3 Volt Power Supply
5 Volt Tolerant I/O
144 Lead PQFP
111 MHz Data Rate
12-bit Data and Coefficients
On-board Memory for 256 Horizontal and 256 Vertical Coefficient Sets
LF Interface™ Allows All 512 Coefficient Sets to be
Updated Within Vertical Blanking
Selectable 12-bit Data Output with User-Defined
Rounding and Limiting
Seven 3K x 12-bit, Programmable Two-Mode Line
Buffers
16 Horizontal Filter Taps
DESCRIPTION
The LF3311 is an improved version of the LF3310 Horizontal/Vertical Digital Image Filter capable of
operating at speeds of up to 111MHz. This improved speed will increase flexibility and performance. The
added performance will enable you to use this device in more applications. For example, four interleaved
data streams of 27MHz can now be processed within one device. The part is functionally identical to the
LF3310 with the exception that the filter data path is specified to operate faster than the LF Control Interface.
When operating the filter at speeds in excess of 90MHz, loading of coefficients via the LF Interface must
be throttled to a maximum of 90MHz by asserting the PAUSE pin as required to allow sufficient setup time
for the configuration data provided to the Figure 1 below demonstrates the switching waveforms of case 2,
while the switching characteristics are shown in Table 1.
Figure 1. Switching Waveforms: LF InterfaceTM
CLK
tPWH
tS0
LDB
tPS
PAUSEA
CFA 11-0
CFB 11-0
tLH
tCYC
LDA
PAUSEB
tPWL
tPH
tCFH
tCFS
ADDRESS
CF0
CF1
The LF3311 remains a two-dimensional digital image filter capable of filtering data at real-time video rates.
The device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for
two-dimensional filtering. The input, coefficient, and output data are all 12-bits and in two’s complement
format. The horizontal filter is designed to take advantage of symmetric coefficient sets. When symmetric
coefficient sets are used, the horizontal filter can be configured as a 16-tap FIR filter. When asymmetric
coefficient sets are used, it can be configured as an 8-tap FIR filter. The vertical filter is an 8-tap FIR
filter with all required line buffers contained on-chip. The line buffers can store video lines with lengths
from 4 to 3076 pixels. Horizontal filter Interleave/Decimation Registers (I/D Registers) and the vertical filter
line buffers allow interleaved data to be fed directly into the device and filtered without separating the data
into individual data streams. The horizontal filter can handle a maximum of sixteen data sets interleaved
together. The vertical filter can handle interleaved video lines which contain 3076 or less data values. The
I/D Registers and horizontal accumulator facilitate using decimation to increase the number of filter taps
in the horizontal filter. It will support a decimation factor of up to 16:1. The device has on-chip storage
for 256 horizontal coefficient sets and 256 vertical coefficient sets. Each filter’s coefficients are loaded
independently of each other allowing one filter’s coefficients to be updated without affecting the other filter’s
coefficients. In addition, a horizontal or vertical coefficient set can be updated independently from the other
coefficient sets in the same filter.
LOGIC Devices Incorporated
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Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Table 1. Switching Characteristics
Commercial Operating Range (0ºC to + 70ºC)
9 (ns) speed grade
Symbol
Parameter
MIN
MAX
tCYC
Cycle Time
9
tPWL
Clock Pulse Width Low
4
tPWH
Clock Pulse Width High
4
tS0
Input Setup Time
4
tS1
Input Setup Time (xCEN, xRSL)
4
tH0
Input Hold Time
1
tH1
Input Hold Time (xCEN, xRSL)
tD
Output Delay
8
tDIS
Three-State Output Disable Delay
10
tENA
Three-State Output Enable Delay
tCFS
Coefficient Input Setup Time
5
tCFH
Coefficient input Hold Time
1.5
tLS
Load Setup Time
4
tLH
Load Hold Time
1.5
tPS
PAUSE Setup Time
tPH
PAUSE Hold time
1.5
10
4
1.5
Figure 2. LF3311 Block Diagram
DIN11-0
12
16-TAP HORIZONTAL FILTER
256 COEFFICIENT SET STORAGE
8-TAP VERTICAL FILTER
256 COEFFICIENT SET STORAGE
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
12
3K LINE BUFFER
LOGIC Devices Incorporated
DOUT11-0
2
Video Imaging Products
9/19/05 LDS.3311-C
3
VLD
VCA7-0
VCEN
8
12
LF
INTERFACE
3K Line Buffer
3K Line Buffer
3K Line Buffer
24
24
12
12
V Coef Bank 0
V Coef Bank 2
24
12
V Coef Bank 1
24
12
V Coef Bank 3
24
24
12
12
24
12
12
V Coef Bank 4
12
12
12
V Coef Bank 5
24
12
12
V Coef Bank 6
12
12
12
V Coef Bank 7
H Coef Bank 3
H Coef Bank 2
26
26
12
12
12
25
13
VACC
25
"0"
27
31
1-16
13
A
ALU
DOUT11-0
12
LIMIT
RND
O
25
25
C
13
13
DATA
DELAY
13
RND
3K Line Buffer
3K Line Buffer
C
8
H Coef Bank 1
1-16
12
B
B
A
ALU
31
"0"
25
13
13
B
A
ALU
25
13
13
B
A
ALU
27
25
13
13
B
ALU
OE
HACC
25
13
13
A
B
12
12
12
12
Figure 3. LF3311 Functional Block Diagram
3K Line Buffer
3K Line Buffer
12
O
12
HCA7-0
HCEN
H Coef Bank 0
ALU
1-16
13
A
H Coef Bank 7
H Coef Bank 6
H Coef Bank 4
H Coef Bank 5
DEVICES INCORPORATED
VCF11-0
VSHEN
HSHEN
TXFR
WE
CONFIGURATION
REGISTERS
C
LF
INTERFACE
B
DATA
REVERSAL
CRA4-0
HLD
HCF11-0
ALU
1-16
1-16
13
1-16
8
A
E O I
5
B
1-16
1-16
CNFG7-0
ALU
1-16
1-16
13
A
1-16
1-16
12
DATA
DELAY
1-16
CLK
12
1-16
1-16
LOGIC Devices Incorporated
O
DIN11-0
LF3311
Horizontal / Vertical Digital Image Filter
Improved Performance
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Horizontal Filter
The horizontal filter is designed to filter a digital image in the horizontal dimension. This FIR filter can
be configured to have as many as 16-taps when symmetric coefficient sets are used and 8-taps when
asymmetric coefficient sets are used.
ALU
The ALUs double the number of filter taps available, when symmetric coefficient sets are used, by preadding data values which are then multiplied by a common coefficient (see Figure 4). The ALUs can
perform two operations: A+B and B–A. Bit 0 of Configuration Register 0 determines the ALU operation.
A+B is used with even-symmetric coefficient sets. B–A is used with odd-symmetric coefficient sets. Also,
either the A or B operand may be set to 0. Bits 1 and 2 of Configuration Register 0 control the ALU inputs.
A+0 or B+0 are used with asymmetric coefficient sets.
Figure 4. Symmetric Coefficient Set Examples
8 7 6 5
8 7 6 5 4 3 2 1
7 6 5 4 3 2 1
Even-Tap, Even-Symmetric
Coefficient Set
Odd-Tap, Even-Symmetric
Coefficient Set
4 3 2 1
Even-Tap, Odd-Symmetric
Coefficient Set
I/D Registers
The Interleave/Decimation Registers (I/D Registers) feed the ALU inputs. They allow the device to filter up
to sixteen data sets interleaved into the same data stream without having to separate the data sets. The I/D
Registers should be set to a length equal to the number of data sets interleaved together. For example, if
two data sets are interleaved together, the I/D Registers should be set to a length of two. Bits 1 through 4 of
Configuration Register 1 determine the I/D Register length.
The I/D Registers also facilitate using decimation to increase the number of filter taps. Decimation by N
is accomplished by reading the horizontal filter’s output once every N clock cycles. The device supports
decimation up to 16:1. With no decimation, the maximum number of filter taps is sixteen. When decimating
by N, the number of filter taps becomes 16N because there are N–1 clock cycles when the horizontal filter’s
output is not being read. The extra clock cycles are used to calculate more filter taps.
When decimating, the I/D Registers should be set to a length equal to the decimation factor. For example,
when performing a 4:1 decimation, the I/D Registers should be set to a length of four. When not decimating
or when only one data set (non-interleaved data) is fed into the device, the I/D Registers should be set
to a length of one.
HSHEN enables or disables the loading of data into the forward and reverse I/D Registers when the device
is in Dimensionally Separate Mode (see the HSHEN section for a full discussion). When in Orthogonal
Mode, HSHEN also enables or disables the loading of data into the input register (DIN11-0) and the line
buffers.
It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable the loading of data
into the input register (DIN11-0), I/D Registers, and line buffers. Both must be active to enable data loading
in Orthogonal Mode.
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9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
I/D Register Data
Path Control
The multiplexer in the middle of the I/D Register data path controls how data is fed to the reverse data path.
The forward data path contains the I/D Registers in which data flows from left to right in the block diagram in
Figure 1. The reverse data path contains the I/D Registers in which data flows from right to left. When the
filter is configured for an even number of taps, data from the last I/D Register in the forward data path is fed
into the first I/D Register in the reverse data path (see Figure 5).
Figure 5. I/D Register Data Paths
ALU
1-16
1-16
1-16
1-16
1-16
1-16
Delay Stage N
A
A
B
DATA
REVERSAL
ALU
B
1-16
ALU
A
B
1-16
A
DATA
REVERSAL
ALU
B
1-16
1-16
DATA
REVERSAL
1-16
1-16
A
Delay Stage N 1
ALU
B
A
ALU
B
COEF 7
COEF 7
2
COEF 7
2
COEF 6
COEF 6
COEF 6
EVEN-TAP MODE
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
When the filter is configured for an odd number of taps, the data which will appear at the output of the last
I/D Register in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse
data path. Bit 5 in Configuration Register 1 configures the filter for an even or odd number of taps.
When interleaved data is fed through the device and an even tap filter is desired, the filter should be
configured for an even number of taps (Bit 5 of CR1 set to “0”) and the I/D Register length should match
the number of data sets interleaved together. When interleaved data is to be fed through the device and
an odd tap filter is desired, the filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration
Register 1 configures the filter for Odd-Tap Interleave Mode. When the filter is configured for Odd-Tap
Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the first I/D
Register in the reverse data path.
When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is
structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in
the forward data path. In order to achieve the correct result, the user must divide the coefficient by two.
Data Reversal
LOGIC Devices Incorporated
Data reversal circuitry is placed after the multiplexer which routes data from the forward data path to the
reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to be
properly aligned at the inputs of the ALUs. When data reversal is enabled, the circuitry uses a pair of LIFOs
to reverse the order of the data sent to the reverse data path. When TXFR goes LOW, the LIFO sending
data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO
receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The
device must see a HIGH to LOW transition of TXFR in order to switch LIFOs. If decimating by N, TXFR
should go low once every N clock cycles. When data reversal is disabled, the circuitry functions like an
I/D Register. When feeding interleaved data through the filter, data reversal should be disabled. Bit 6 of
Configuration Register 1 enables or disables data reversal.
5
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Horizontal
Rounding
The horizontal filter output may be rounded by adding the contents of one of the sixteen horizontal round
registers to the horizontal filter output Wide Output Mode in the Operating Modes section). All programming
of the device is done through the Configuration Registers via the 16-bit Configuration/Control Interface.
(see Figure 7). Each round register is 32-bits wide and user-programmable. This allows the filter’s output to
be rounded to any precision required. Since any 32-bit value may be programmed into the round registers,
the device can support complex rounding algorithms as well as standard Half-LSB rounding. HRSL3-0
determines which of the sixteen horizontal round registers are used in the rounding operation. A value of
0 on HRSL3-0 selects horizontal round register 0. A value of 1 selects horizontal round register 1 and
so on. HRSL3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be
changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round
register should be loaded with 0 and selected as the register used for rounding. Round register loading is
discussed in the LF Interface™ section.
Figure 6. Data Reversal
TXFRA/TXFRB
LIFO A
LIFO B
1-16
Horizontal Select
The word width of the horizontal filter output is 32-bits. However, only 12-bits may be sent to the filter output.
The horizontal filter select circuitry determines which 12-bits are passed (see Table 20). The horizontal
select registers control the horizontal select circuitry. There are sixteen horizontal select registers. Each
select register is 5-bits wide and user-programmable. HRSL3-0 determines which of the sixteen horizontal
select registers are used in the horizontal select circuitry. A value of 0 on HRSL3-0 selects horizontal select
register 0. A value of 1 selects horizontal select register 1 and so on. HRSL3-0 may be changed every
clock cycle if desired. This allows the 12-bit window to be changed every clock cycle. This is useful when
filtering interleaved data. Select register loading is discussed in the LF Interface™ section.
Horizontal Limiting
An output limiting function is provided for the output of the horizontal filter. The horizontal limit registers
determine the valid range of output values when limiting is enabled (Bit 1 in Configuration Register 5). There
are sixteen 24-bit horizontal limit registers. HRSL3-0 determines which horizontal limit register is used
during the limit operation. A value of 0 on HRSL3-0 selects horizontal limit register 0. A value of 1 selects
horizontal limit register 1 and so on. Each limit register contains both an upper and lower limit value. If
the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the
filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value
is passed as the filter output. HRSL3-0 may be changed every clock cycle if desired. This allows the
limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading
limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is
discussed in the LF Interface™ section.
LOGIC Devices Incorporated
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Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Figure 7. Horizontal and Verticle Round/Limit/Select Circuitry
DATA IN
4
32
R0
RSL3-0
32
R15
RND
S0
32
5
S15
SELECT
L0
16
32
L15
LIMIT
RSL CIRCUITRY
16
DATA OUT
Table 2. Configuration register 0 - Address 200H
BITS
FUNCTION
DESCRIPTION
0
ALU Mode
1
Pass A
2
Pass B
0:A+B
1:B–A
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
Must be set to “0”
11-3
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Reserved
7
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Vertical Filter
The vertical filter is designed to filter a digital image in the vertical dimension. It is a FIR filter which can
be configured to have as many as 8-taps.
Line Buffers
There are seven on-chip line buffers. The maximum delay length of each line buffer is 3076 cycles and
the minimum is 4 cycles. Configuration Register 2 (CR2) determines the delay length of the line buffers.
The line buffer length is equal to the value of CR2 plus 4. A value of 0 for CR2 sets the line buffer
length to 4. A value of 3072 for CR2 sets the line buffer length to 3076. Any values for CR2 greater
than 3072 are not valid.
The line buffers have two modes of operation: delay mode and recirculate mode. Bit 0 of Configuration
Register 3 determines which mode the line buffers are in. In delay mode, the data input to the line buffer is
delayed by an amount determined by CR2. In recirculate mode, the output of the line buffer is routed back to
the input of the line buffer allowing the line buffer contents to be read multiple times.
Bit 1 of Configuration Register 3 allows the line buffers to be loaded in parallel. When Bit 1 is “1”, the input
register (DIN11-0) loads all seven line buffers in parallel. This allows all the line buffers to be preloaded with
data in the amount of time it normally takes to load a single line buffer.
VSHEN enables or disables the loading of data into the line buffers when the device is in Dimensionally
Separate Mode (see the VSHEN section for a full discussion). When in Orthogonal Mode, VSHEN also
enables or disables the loading of data into the input register (DIN11-0) and the forward and reverse I/D
It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable the loading of data
into the input register (DIN11-0), I/D Registers, and line buffers. Both must be active to enable data loading
in Orthogonal Mode.
Interleaved Data
The vertical filter is capable of handling interleaved data. The number of data sets it can handle is
determined by the number of data values contained in a video line. If the interleaved video line has 3076
data values or less, the vertical filter can handle it no matter how many data sets are interleaved together.
Vertical Rounding
The vertical filter output may be rounded by adding the contents of one of the sixteen vertical round registers
to the vertical filter output (see Figure 7). Each round register is 32-bits wide and user-programmable.
This allows the filter’s output to be rounded to any precision required. Since any 32-bit value may be
programmed into the round registers, the device can support complex rounding algorithms as well as
standard Half-LSB rounding. VRSL3-0 determines which of the sixteen vertical round registers are used
in the rounding operation. A value of 0 on VRSL3-0 selects vertical round register 0. A value of 1 selects
vertical round register 1 and so on. VRSL3-0 may be changed every clock cycle if desired. This allows
the rounding algorithm to be changed every clock cycle. This is useful when filtering interleaved data. If
rounding is not desired, a round register should be loaded with 0 and selected as the register used for
rounding. Round register loading is discussed in the LF Interface™ section.
Vertical Select
The word width of the vertical filter output is 32-bits. However, only 12-bits may be sent to the filter output.
The vertical filter select circuitry determines which 12-bits are passed (see Table 20). The vertical select
registers control the vertical select circuitry. There are sixteen vertical select registers. Each select register
is 5-bits wide and user-programmable. VRSL3-0 determines which of the sixteen vertical select registers
are used in the vertical select circuitry. A value of 0 on VRSL3-0 selects vertical select register 0. A value
of 1 selects vertical select register 1 and so on. VRSL3-0 may be changed every clock cycle if desired.
This allows the 12-bit window to be changed every clock cycle. This is useful when filtering interleaved data.
Select register loading is discussed in the LF Interface™ section.
LOGIC Devices Incorporated
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Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Vertical Limiting
An output limiting function is provided for the output of the vertical filter. The vertical limit registers determine
the valid range of output values when limiting is enabled (Bit 0 in Configuration Register 5). There are
sixteen 24-bit vertical limit registers. VRSL3-0 determines which vertical limit register is used during the limit
operation. A value of 0 on VRSL3-0 selects vertical limit register 0. A value of 1 selects vertical limit register
1 and so on. Each limit register contains both an upper and lower limit value. If the value fed to the limiting
circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the
limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. VRSL3-0
may be changed every clock cycle if desired. This allows the limit range to be changed every clock cycle.
This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must
be greater than the lower limit. Limit register loading is discussed in the LF Interface™ section.
Table 3. Configuration Register 1 - Address 201H
BITS
0
FUNCTION
Odd-Tap Interleave Mode
4-1
I/D Register Length
5
Horizontal Tap Number
6
Horizontal Data Reversal
11-7
Reserved
DESCRIPTION
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
0000 : 1 Register
0001 : 2 Registers
0010 : 3 Registers
0011 : 4 Registers
0100 : 5 Registers
0101 : 6 Registers
0110 : 7 Registers
0111 : 8 Registers
1000 : 9 Registers
1001 : 10 Registers
1010 : 11 Registers
1011 : 12 Registers
1100 : 13 Registers
1101 : 14 Registers
1110 : 15 Registers
1111 : 16 Registers
0 : Even Number of Taps
1 : Odd Number of Taps
0 : Data Reversal Enabled
1 : Data Reversal Disabled
Must be set to “0”
Table 4. Configuration Register 2 - Address 202H
BITS
11-0
FUNCTION
Line Buffer Length
DESCRIPTION
See Line Buffer Description Section
Table 5. Configuration Register 3 - Address 203H
BITS
0
FUNCTION
Line Buffer Mode
1
Line Buffer Load
11-2
LOGIC Devices Incorporated
Reserved
9
DESCRIPTION
0 : Delay Mode
1 : Recirculate Mode
0 : Normal Load
1 : Parallel Load
Must be set to “0”
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Table 6. Configuration Register 4 - Adress 204H
BITS
0
FUNCTION
HV Filter Mode
1
HV Direction
3-2
Orthogonal Kernel Size
4
Limit Register Load Control
11-5
Reserved
DESCRIPTION
0 : Orthogonal Mode
1 : Dimensionally Separate
0 : Horizontal to Vertical
1 : Vertical to Horizontal
00 : 3-3 Kernel
01 : 5-5 Kernel
10 : 7-7 Kernel
11 : Not Used
0 : Limit Registers Always Enabled
1 : Limit Registers Under Shift Enable Control
Must be set to “0”
Table 7. Configuration Register 5 - Adress 205H
BITS
0
FUNCTION
Vertical Limit Enable
1
Horizontal Limit Enable
11-2
Reserved
DESCRIPTION
0 : Vertical Limiting Disabled
1 : Vertical Limiting Enabled
0 : Horizontal Limiting Disabled
1 : Horizontal Limiting Enabled
Must be set to “0”
Table 8. HCF/VCF11-9 Decode
11
0
0
0
0
1
1
1
1
9
0
1
0
1
0
1
0
1
DESCRIPTION
Coefficient Banks
Configuration Registers
Horizontal Select Registers
Vertical Select Registers
Horizontal Round Registers
Vertical Round Registers
Horizontal Limit Registers
Vertical Limit Registers
Table 9 H Round Registers
Table 10 H Select Registers
Table 11 H Limit Registers
REGISTER ADDRESS (HEX)
0
800
1
801
REGISTER ADDRESS (HEX)
0
400
1
401
REGISTER ADDRESS (HEX)
0
C00
1
C01
14
15
80E
80F
14
15
40E
40F
14
15
C0E
C0F
Table 12 V Round Registers
Table 13 V Select Registers
Table 14 V Limit Registers
REGISTER ADDRESS (HEX)
0
A00
1
A01
REGISTER ADDRESS (HEX)
0
600
1
601
REGISTER ADDRESS (HEX)
0
E00
1
E01
14
15
LOGIC Devices Incorporated
10
0
0
1
1
0
0
1
1
A0E
A0F
14
15
10
60E
60F
14
15
E0E
E0F
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Coefficient
Banks
The coefficient banks store the coefficients which feed into the multipliers in the horizontal and vertical
filters. There is a separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks
are loaded using an LF Interface™. There is a separate LF Interface™ for the horizontal and vertical banks.
Coefficient bank loading is discussed in the LF Interface™ section.
Configuration
and Control
Registers
The Configuration Registers determine how the HV Filter operates. Tables 2 through 7 show the formats
of the six configuration registers. There are three types of control registers: round, select, and limit. There
are sixteen round registers for the horizontal filter and sixteen for the vertical filter. Each register is 32-bits
wide. HRSL3-0 and VRSL3-0 determine which horizontal and vertical round registers respectively are
used for rounding.
There are sixteen select registers for the horizontal filter and sixteen for the vertical filter. Each register is
5-bits wide. HRSL3-0 and VRSL3-0 determine which horizontal and vertical select registers respectively
are used in the select circuitry.
There are sixteen limit registers for the horizontal filter and sixteen for the vertical filter. Each register is
24-bits wide and stores both an upper and lower limit value. The lower limit is stored in bits 11-0 and the
upper limit is stored in bits 23-12. HRSL3-0 and VRSL3-0 determine which horizontal and vertical limit
registers respectively are used for limiting when limiting is enabled. Configuration and Control Register
loading is discussed in the LF Interface™ section.
Figure 8. Coefficient Bank Loading Sequence
COEFFICIENT SET 3
COEFFICIENT SET 2
COEFFICIENT SET 1
CLK
W3
W2
W1
HLD/VLD
HCF/VCF11-0
COEF7
ADDR1 COEF0
COEF7
ADDR2 COEF0
COEF7
ADDR3 COEF0
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
Figure 9. Configurational/Control Register Loading Sequence
CONFIG REG
ROUND REGISTER
SELECT REG
LIMIT REGISTER
CLK
W2
W1
W3
W4
HLD/VLD
HCF/VCF11-0
ADDR1
DATA1 ADDR2
DATA1 ADDR3
DATA1
DATA2
DATA3
DATA4 ADDR4
DATA1
DATA2
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
LOGIC Devices Incorporated
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Video Imaging Products
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LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
LF Interface ™
The Horizontal and Vertical LF Interface™ are used to load data into the horizontal and vertical coefficient
banks respectively. They are also used to load data into the Configuration and Control Registers.
The following section describes how the Horizontal LF Interface™ works. The Horizontal and Vertical LF
Interface™ are identical in function. If HLD and HCF11-0 are replaced with VLD and VCF11-0, the following
section will describe how the Vertical LF Interface™ works.
HLD is used to enable and disable the Horizontal LF Interface™. When HLD goes LOW, the Horizontal LF
Interface™ is enabled for data input. The first value fed into the interface on HCF11-0 is an address which
determines what the interface is going to load. The three most significant bits (HCF11-9) determine if the
LF Interface™ will load coefficient banks or Configuration/Control Registers (see Table 8). The nine least
significant bits (HCF8-0) are the address for whatever is to be loaded (see Tables 9-14). For example, to
load address 15 of the horizontal coefficient banks, the first data value into the LF Interface™ should be
00FH. To load horizontal limit register 10, the first data value should be C0AH. The first address value
should be loaded into the interface on the same clock cycle that latches the HIGH to LOW transition of
HLD (see Figures 8 and 9).
The next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register
defined by the address value. When loading coefficient banks, the interface will expect eight values to
be loaded into the device after the address value. The eight values are coefficients 0 through 7. When
loading select or Configuration Registers, the interface will expect one value after the address value. When
loading round registers, the interface will expect four values after the address value. When loading limit
registers, the interface will expect two values after the address value. Figures 8 and 9 show the data
loading sequences for the coefficient banks and Configuration/Control Registers.
Figure 10. Coefficient Bank Loading Sequence with HPAUSE and VPAUSE
ROUND REGISTER
CLK
W1
HPAUSE/VPAUSE
HLD/VLD
HCF/VCF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Round Register loaded with new data on this rising clock edge.
Figure 11. Config and Select Register Loading Sequence with HPAUSE and VPAUSE
LIMIT REGISTER
CLK
W1
HPAUSE/VPAUSE
HLD/VLD
HCF/VCF11-0
ADDR1
DATA1
DATA2
W1: Limit Register loaded with new data on this rising clock edge.
LOGIC Devices Incorporated
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Video Imaging Products
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LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
LF Interface ™
Continued
Both HPAUSE and VPAUSE allow the user to effectively slow the rate of data loading through the LF
Interface™. When HPAUSE is HIGH, the LF Interface™ affecting the data used for the Horizontal Filter is
held until HPAUSE is returned to a LOW. When VPAUSE is HIGH, the LF Interface™ affecting the data
used for the Vertical Filter is held until VPAUSE is returned to a LOW. Figures 10 through 13 display the
effects of both HPAUSE and VPAUSE while loading coefficient and control data. Table 15 shows an example
of loading data into the coefficient banks. The following data values are written into address 10 of coefficient
banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 16 shows an example of
loading data into a Configuration Register. Data value 003H is written into Configuration Table 15 shows
an example of loading data into the coefficient banks. The following data values are written into address
10 of coefficient banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 16 shows
an example of loading data into a Configuration Register. Data value 003H is written into Configuration
Register 4. Table 17 shows an example of loading data into a round register. Data value 7683F4A2H is
written into horizontal round register 12. Table 18 shows an example of loading data into a select register.
Data value 00FH is loaded into horizontal select register 2. Table 19 shows an example of loading data into
vertical limit register 7. Data value 390H is loaded as the lower limit and 743H is loaded as the upper limit. It
takes 9S clock cycles to load S coefficient sets into the device. Therefore, it takes 2304 clock cycles to
load all 256 coefficient sets. Assuming an 83 MHz clock rate, all 256 coefficient sets can be updated in
28.8 µs, which is well within vertical blanking time. It takes 5S or 3S clock cycles to load S round or limit
registers respectively. Therefore, it takes 256 clock cycles to update all round and limit registers (both
horizontal and vertical). Assuming an 83 MHz clock rate, all horizontal and vertical Round/Limit registers
can be updated in 3.08 µs.
Figure 12. Round Register Loading Sequence with HPAUSE and VPAUSE
ROUND REGISTER
CLK
W1
PAUSE
LD
CF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Round Register loaded with new data on this rising clock edge.
Figure 13. Round Register Loading Sequence with HPAUSE and VPAUSE
LIMIT REGISTER
CLK
W1
PAUSE
LD
CF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Limit Register loaded with new data on this rising clock edge.
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LF3311
Horizontal / Vertical Digital Image Filter
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Improved Performance
Functional Description
Table 15. Coefficient Bank Loading Format
1st Word - Address
2nd Word - Bank 0
3rd Word - Bank 1
4th Word - Bank 2
5th Word - Bank 3
6th Word - Bank 4
7th Word - Bank 5
8th Word - Bank 6
9th Word - Bank 7
H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
1
1
0
1
0
0
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
Table 16. Configuration Register Loading Format
1st Word - Address
2nd Word - Data
CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Table 17. Round Register Loading Format
1st Word - Address
2nd Word - Data
3rd Word - Data
4th Word - Data
5th Word - Data
CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0
1
0
0
0
0
0
0
0
1
1
0
0
R
R
R
R
0
1
0
1
0
0
1
0
R
R
R
R
1
1
1
1
0
1
0
0
R
R
R
R
1
0
0
0
0
0
1
1
R
R
R
R
0 **
1
1
1
0
1
1
0
Table 18. Select Register Loading Format
1st Word - Address
2nd Word - Data
CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
Table 19. Limit Register Loading Format
1st Word - Address
2nd Word - Data
3rd Word - Data
*
**
LF Interface ™
Continued
LOGIC Devices Incorporated
H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0
1
1
1
0
0
0
0
0
0
1
1
1
0*
0
1
1
1
0
0
1
0
0
0
0
0**
1
1
1
0
1
0
0
0
0
1
1
This bit represents the MSB of the Lower Limit.
This bit represents the MSB of the Upper Limit.
The coefficient banks and Configuration/Control Registers are not loaded with data until all data values for
the specified address are loaded into the LF InterfaceTM. In other words, the coefficient banks are not
written to until all eight coefficients have been loaded into the LF InterfaceTM. A round register is not
written to until all four data values are loaded. After the last data value is loaded, the interface will expect
a new address value on the next clock cycle. After the next address value is loaded, data loading will
begin again as previously discussed. As long as data is loaded into the interface, HLD must remain
LOW. After all desired coefficient banks and Configuration/Control Registers are loaded with data, the
LF InterfaceTM must be disabled. This is done by setting HLD HIGH on the clock cycle after the clock
cycle which latches the last data value. It is important that the LF InterfaceTM remain disabled when
not loading data into it.
14
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LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
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Functional Description
LF Interface ™
Continued
The horizontal coefficient banks may only be loaded with the Horizontal LF InterfaceTM and the vertical
coefficient banks may only be loaded with the Vertical LF InterfaceTM. The Configuration and Control
Registers may be loaded with either the Horizontal or Vertical LF InterfacesTM. Since both LF InterfacesTM
operate independently of each other, both LF InterfacesTM can load data into their respective coefficient
banks at the same time. Or, one LF InterfaceTM can load the Configuration/Control Registers while the
other loads it’s respective coefficient banks. If both LF InterfacesTM are used to load a configuration or
control register at the same time, the Vertical LF InterfaceTM will be given priority over the Horizontal LF
InterfaceTM. For example, if the Horizontal LF InterfaceTM attempts to load data into a Configuration
Register at the same time that the Vertical LF InterfaceTM attempts to load a horizontal round register, the
Vertical LF InterfaceTM will be allowed to load the round register while the Horizontal LF InterfaceTM will
not be allowed to load the Configuration Register. However, the Horizontal LF InterfaceTM will continue
to function as if the write occurred.
Operating Modes
Dimensionally
Seperate Mode
In Dimensionally Separate Mode, the horizontal and vertical filters are cascaded together to form a twodimensional image filter (see Figures 14 and 15). Bit 1 in Configuration Register 4 determines the cascade
order. If this bit is set to “0”, data on DIN11-0 is fed into the horizontal filter first. The horizontal filter then
feeds data into the vertical filter. If this bit is set to “1”, data on DIN11-0 is fed into the vertical filter first. The
vertical filter then feeds data into the horizontal filter.
Figure 14. Dimensionally Seperate Mode: H to V
DIN11-0
12
HORIZONTAL FILTER
12
LINE BUFFER
VERTICAL FILTER
LINE BUFFER
LINE BUFFER
LINE BUFFER
12
DOUT11-0
LINE BUFFER
LINE BUFFER
LINE BUFFER
Figure 15. Dimensionally Seperate Mode: V to H
DIN11-0
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
VERTICAL FILTER
LINE BUFFER
12
HORIZONTAL FILTER
LINE BUFFER
12
LINE BUFFER
LINE BUFFER
LOGIC Devices Incorporated
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DOUT11-0
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Horizontal / Vertical Digital Image Filter
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Operating Modes
Orthogonal Mode
In Orthogonal Mode, the horizontal and vertical filters are used concurrently to implement an orthogonal
kernel on the input data (see Figure 16). The HV Filter can handle kernel sizes of 3-3, 5-5, and 7-7
(see Figure 17). Data delay elements at the input of the horizontal filter and the output of the vertical
filter are used to properly align data so that the orthogonal kernel is implemented correctly. The data
delays are automatically set to the correct lengths based on the programmed length of the line buffers
and the kernel size.
Kernel sizes of 3-3, 5-5, and 7-7 require that the horizontal filter’s output be delayed by LB – 2, 2(LB)
– 3, and 3(LB) – 4 clock cycles respectively before being added to the vertical filter’s output (LB is the
programmed line buffer length). The data delay at the input of the horizontal filter handles the LB, 2(LB),
and 3(LB) delays. The data delay at the output of the vertical filter handles the – 2, – 3, and – 4 delays.
For example, if the line buffers are programmed for a length of 720 and a 5–5 kernel is selected, the
horizontal filter input data delay will be 1440 clock cycles and the vertical filter output data delay will be
3 clock cycles.
It is important to note that the first 3, 5, or 7 multipliers of the horizontal and vertical filters must be used
in Orthogonal Mode. If other multipliers are used, data from the horizontal and vertical filters will not line
up correctly because the data delays are calculated assuming that the first 3, 5, or 7 multipliers are used.
Also, the ALUs in the horizontal filter should be configured to accept data from the forward I/D Register path
into ALU Input A and force ALU Input B to 0.
Figure 14. Orthogonal Mode
12
DIN11-0
DATA
DELAY
HORIZONTAL FILTER
LINE BUFFER
VERTICAL FILTER
LINE BUFFER
LINE BUFFER
LINE BUFFER
DATA
DELAY
LINE BUFFER
12
LINE BUFFER
LINE BUFFER
DOUT11-0
Figure 15. 3-3, 5-5, and 7-7 Orthagonal Kernels
V1
V1
V2
V1
V2
V3
H1 HV2 H3
H1 H2 HV3 H4 H5
H1 H2 H3 HV4 H5 H6 H7
V3
V4
V5
V5
V6
V7
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LF3311
Horizontal / Vertical Digital Image Filter
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Signal Definitions
Power
Vcc and GND
+3.3 V power supply. All pins must be connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all enabled registers.
Inputs
DIN11-0 — Data Input
DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12-bit input port
to Filter B. Data is latched on the rising edge of clock.
HCF11-0 — Horizontal Coefficient Input
HCF11-0 is used to load data into the horizontal coefficient banks and the Configuration/Control Registers.
Data present on HCF11-0 is latched into the Horizontal LF InterfaceTM on the rising edge of CLK when HLD
is LOW (see the LF InterfaceTM section for a full discussion).
HCA7-0 — Horizontal Coefficient Address
HCA7-0 determines which row of data in the horizontal coefficient banks is fed to the multipliers in the
horizontal filter. HCA7-0 is latched into the Horizontal Coefficient Address Register on the rising edge of
CLK when HCEN is LOW.
VCF11-0 — Vertical Coefficient Input
VCF11-0 is used to load data into the vertical coefficient banks and the Configuration/Control Registers.
Data present on VCF11-0 is latched into the Vertical LF InterfaceTM on the rising edge of CLK when VLD is
LOW (see the LF InterfaceTM section for a full discussion).
VCA7-0 — Vertical Coefficient Address
VCA7-0 determines which row of data in the vertical coefficient banks is fed to the multipliers in the vertical
filter. VCA7-0 is latched into the Vertical Coefficient Address Register on the rising edge of CLK when
VCEN is LOW.
Figure 16. Input Formats
Input Data
11 10 9
211 210 29
(Sign)
Coefficient Data
2 1 0
22 21 20
11 10 9
20 2 1 2 2
(Sign)
2 1 0
2 9 2 10 2 11
Figure 17. Accumulator Output Formats
Accumulator Output
31 30 29
220 219 218
(Sign)
LOGIC Devices Incorporated
2 1 0
2 9 2 10 2 11
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Signal Definitions
Table 20. Output Formats
SLCT4-0
00000
00001
00010
·
·
·
01110
01111
10000
S15
F15
F16
F17
·
·
·
F29
F30
F31
S14
F14
F15
F16
·
·
·
F28
F29
F30
S13
F13
F14
F15
·
·
·
F27
F28
F29
···
···
···
···
···
···
···
S8
F8
F9
F10
·
·
·
F22
F23
F24
S7
F7
F8
F9
·
·
·
F21
F22
F23
···
···
···
···
···
···
···
S2
F2
F3
F4
·
·
·
F16
F17
F18
S1
F1
F2
F3
·
·
·
F15
F16
F17
S0
F0
F1
F2
·
·
·
F14
F15
F16
Outputs
DOUT11-0 — Data Output
DOUT11-0 is the 12-bit registered data output port.
Controls
HLD — Horizontal Coefficient Load
When HLD is LOW, data on HCF11-0 is latched into the Horizontal LF InterfaceTM on the rising edge of
CLK. When HLD is HIGH, data can not be latched into the Horizontal LF InterfaceTM. When enabling the
LF InterfaceTM for data input, a HIGH to LOW transition of HLD is required in order for the input circuitry to
function properly. Therefore, HLD must be set HIGH immediately after power up to ensure proper operation
of the input circuitry (see the LF InterfaceTM section for a full discussion).
HCEN — Horizontal Coefficient Address Enable
When HCEN is LOW, data on HCA7-0 is latched into the Horizontal Coefficient Address Register on the
rising edge of CLK. When HCEN is HIGH, data on HCA7-0 is not latched and the register’s contents
will not be changed.
VLD — Vertical Coefficient Load
When VLD is LOW, data on VCF11-0 is latched into the Vertical LF InterfaceTM on the rising edge of
CLK. When VLD is HIGH, data can not be latched into the Vertical LF InterfaceTM. When enabling the LF
InterfaceTM for data input, a HIGH to LOW transition of VLD is required in order for the input circuitry to
function properly. Therefore, VLD must be set HIGH immediately after power up to ensure proper operation
of the input circuitry (see the LF InterfaceTM section for a full discussion).
VCEN — Vertical Coefficient Address Enable
When VCEN is LOW, data on VCA7-0 is latched into the Vertical Coefficient Address Register on the
rising edge of CLK. When VCEN is HIGH, data on VCA7-0 is not latched and the register’s contents
will not be changed.
TXFR — Horizontal Filter LIFO Transfer Control
TXFR is used to change which LIFO in the data reversal circuitry sends data to the reverse data path and
which LIFO receives data from the forward data path. When TXFR goes LOW, the LIFO sending data to the
reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data
from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a
HIGH to LOW transition of TXFR in order to switch LIFOs.
LOGIC Devices Incorporated
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LF3311
Horizontal / Vertical Digital Image Filter
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Signal Definitions
Controls Continued
HACC — Horizontal Accumulator Control
When HACC is HIGH, the horizontal accumulator is enabled for accumulation and the accumulator output
register is disabled for loading. When HACC is LOW, no accumulation is performed and the accumulator
output register is enabled for loading. HACC is latched on the rising edge of CLK.
VACC — Vertical Accumulator Control
When VACC is HIGH, the vertical accumulator is enabled for accumulation and the accumulator output
register is disabled for loading. When VACC is LOW, no accumulation is performed and the accumulator
output register is enabled for loading. VACC is latched on the rising edge of CLK.
HSHEN — Horizontal Shift Enable
HSHEN enables or disables the loading of data into the forward and reverse I/D Registers in the horizontal
filter when the device is in Dimensionally Separate Mode. If the device is configured such that the horizontal
filter feeds the vertical filter, HSHEN also enables or disables the loading of data into the input register
(DIN11-0). If the device is configured such that the vertical filter feeds the horizontal filter and the vertical
limit register is under shift control, HSHEN also enables or disables the loading of data into the vertical limit
register in the vertical Round/Select/Limit circuitry. In Orthogonal Mode, HSHEN also enables or disables
the loading of data into the input register (DIN11-0) and the line buffers in the vertical filter. It is important
to note that in Orthogonal Mode, either HSHEN or VSHEN can disable data loading. Both must be active
to enable data loading in Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical limit
registers can not be disabled.
When HSHEN is LOW, data is loaded into and shifted through the registers HSHEN controls and the forward
and reverse I/D Registers on the rising edge of CLK. When HSHEN is HIGH, data is not loaded into or
shifted through the registers HSHEN controls and the I/D Registers, and their contents will not be changed.
HSHEN is latched on the rising edge of CLK.
VSHEN — Vertical Shift Enable
VSHEN enables or disables the loading of data into the line buffers in the vertical filter when the device is
in Dimensionally Separate Mode. If the device is configured such that the vertical filter feeds the horizontal
filter, VSHEN also enables or disables the loading of data into the input register (DIN11-0). If the device is
configured such that the horizontal filter feeds the vertical filter and the horizontal limit register is under shift
control, VSHEN also enables or disables the loading of data into the horizontal limit register in the horizontal
Round/Select/Limit circuitry. In Orthogonal Mode, VSHEN also enables or disables the loading of data into
the input register (DIN11-0) and the forward and reverse I/D Registers in the horizontal filter. It is important
to note that in Orthogonal Mode, either HSHEN or VSHEN can disable data loading. Both must be active
to enable data loading in Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical limit
registers can not be disabled.
When VSHEN is LOW, data is loaded into and shifted through the registers VSHEN controls and the line
buffers on the rising edge of CLK. When VSHEN is HIGH, data is not loaded into or shifted through the
registers VSHEN controls and the line buffers, and their contents will not be changed. VSHEN is latched
on the rising edge of CLK.
LOGIC Devices Incorporated
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LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
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Signal Definitions
Controls Cont’d
HRSL3-0 — Horizontal Round/Select/Limit Control
HRSL3-0 determines which of the sixteen user-programmable Round/Select/Limit registers (RSL registers)
are used in the horizontal Round/Select/Limit circuitry (RSL circuitry). A value of 0 on HRSL3-0 selects RSL
register 0. A value of 1 selects round/select/limit register 1 and so on. HRSL3-0 is latched on the rising
edge of CLK (see the horizontal round, select, andv limit sections for a complete discussion).
VRSL3-0 — Vertical Round/Select/Limit Control
VRSL3-0 determines which of the sixteen user-programmable RSL registers are used in the vertical RSL
circuitry. A value of 0 on VRSL3-0 selects RSL register 0. A value of 1 selects RSL register 1 and so
on. VRSL3-0 is latched on the rising edge of CLK (see the vertical round, select, and limit sections for
a complete discussion).
OE — Output Enable
When OE is LOW, DOUT11-0 is enabled for output. When OE is HIGH, DOUT11-0 is placed in a
high-impedance state.
HPAUSE — LF InterfaceTM Pause
When HPAUSE is HIGH, the Horizontal LF InterfaceTM loading sequence is halted until HPAUSE is returned
to a LOW state. This effectively allows the user to load coefficients and Control Registers at a slower rate
than the master clock (see the LF InterfaceTM section for a full discussion).
VPAUSE — LF InterfaceTM Pause
When VPAUSE is HIGH, the Vertical LF InterfaceTM loading sequence is halted until VPAUSE is returned to
a LOW state. This effectively allows the user to load coefficients and Control Registers at a slower rate than
the master clock (see the LF InterfaceTM section for a full discussion).
LOGIC Devices Incorporated
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LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Specifications
Maximum Ratings - Above which useful life may be impaired (Notes 1,2,3,8)
Storage temperature .......................................................................................... –65°C to +150°C
Operating ambient temperature ......................................................................... –55°C to +125°C
VCCO supply voltage with respect to ground ........................................................ –0.5 V to +4.5 V
Input signal with respect to ground ........................................................................ –0.5 V to 5.5 V
Signal applied to high impedance output ............................................................... –0.5 V to 5.5 V
Output current into low outputs ........................................................................................... 25 mA
Latchup current .............................................................................................................. > 400 mA
ESD Classification (MIL-STD-883E METHOD 3015.7) ..................................................... Class 3
Operating Conditions - To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range (Ambient)
0°C to +70°C
-55°C to +125°C
Supply Voltage
3.00’V < VCCO < 3.60 V
3.00 V < VCCO < 3.60 V
Electrical Characteristics - Over Operating Conditions (Note 4)
Symbol
Parameter
VOH
VOL
VIH
VIL
I IX
I OZ
I CC1
I CC2
C IN
C OUT
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
Input Capacitance
Output Capacitance
CLK
2
Switching1Waveforms:
tH
tS
DIN11-0
Test Condition
Data3 I/O
DINN+1
CA7-0
CAN
CAN+1
VB11-0
VBN
VBN+1
tCYC
4
Max Unit
2.4
5
0.4
5.5
0.8
+10
+10
250
2
10
10
2.0
0.0
(Note 3)
Ground < VIN < VCC (Note 12)
Ground < VOUT < VCC (Note 12)
(Notes 5, 6)
(Note 7)
TA = 25°C, f = 1 MHz
TA = 25°C, f = 1 MHz
tPW
DINN
Min Typ
VCC = Min., IOH = -4 mA
VCC = Min., IOL = 8.0 mA
6
V
V
V
V
µA
µA
mA
mA
pF
pF
7
tPW
CONTROLS
(Except OE)
OE
tDIS
DOUT15-0
tENA
HIGH IMPEDANCE
tDD
DOUTN-1
DOUTN
tDC
COUT11-0
LOGIC Devices Incorporated
HIGH IMPEDANCE
21
COUTN-1
COUTN
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Notes
1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values
beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating
conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from
damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional
precautions should be observed during storage, handling, and use of these circuits in order to avoid
exposure to excessive electrical stress values.
3. This device provides hard clamping of transient undershoot. Input levels below ground will be clamped
beginning at –0.6 V. The device can withstand indefinite operation with inputs or outputs in the range of
–0.5V to +5.5V. Device operation will not be adversely affected, however, input current levels will be well
in excess of 100 mA.
4. Actual test conditions may vary from those designated but operation is guaranteed as specified.
5. Supply current for a given application can be accurately approximated by:
where
NCV2 F
4
N
C
V
F
= total number of device outputs
= capacitive load per output
= supply voltage
= clock frequency
6. Tested with outputs changing every cycle and no load, at a 40 MHz clock rate.
7. Tested with all inputs within 0.1 V of VCC or Ground, no load.
8. These parameters are guaranteed but not 100% tested.
9. AC specifications are tested with input transition times less than 3ns, output reference levels of 1.5V
(except tDIS test), and input levels of nominally 0 to 3.0V. Output loading may be a resistive divider which
provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively,
a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of
1.5V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current pulses and fast turn-on/turn-off
times. As a result, care must be exercised in the testing of this device. The following measures are
recommended:
a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to the Device
Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester
common, and device ground and tester common.
b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers.
c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to
maintain required DUT input levels relative to the DUT ground pin.
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the
point of view of the external system driving the chip. Setup time, for example, is specified as a minimum
since the external system must supply at least that much time to meet the worst-case requirements of all
parts. Responses from the internal circuitry are specified from the point of view of the device. Output
delay, for example, is specified as a maximum since worst-case operation of any device always provides
data within that time.
LOGIC Devices Incorporated
22
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Notes
11. For the tENA test, the transition is measured to the 1.5V crossing point with datasheet loads. For
the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output
voltage with ±10mA loads. The balancing voltage, VTH, is set at 3.0 V for Z-to-0 and 0-to-Z tests, and
set at 0 V for Z-to-1 and 1-to-Z tests.
12. These parameters are only tested at the high temperature extreme, which is the worst case
for leakage current.
Figure A. Output Loading Circuit
Figure B. Threshold Levels
tENA
OE
S1
DUT
IOL
Z
0
tDIS
1.5 V
1.5 V
1.5 V
VTH
CL
IOH
Z
1
1.5 V
3.0V Vth
VOL*
VOH*
0.2 V
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
LOGIC Devices Incorporated
23
Video Imaging Products
9/19/05 LDS.3311-C
LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Top
View
144-pin
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VCC
VCC
GND
GND
TXFR
VSHEN
VCEN
VCA7
VCA6
VCA5
VCA4
GND
VCC
VCA3
VCA2
VCA1
VCA0
GND
VCC
VB11
VB10
VB9
VB8
VB7
VB6
GND
VCC
VB5
VB4
VB3
VB2
VB1
VB0
GND
GND
VCC
VCC
GND
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
VCC
GND
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
VCC
GND
VLD
VCF0
VCF1
VCF2
VCF3
VCF4
VCF5
VCC
GND
VCF6
VCF7
VCF8
VCF9
VCF10
VCF11
CLK
GND
VCC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
VCC
GND
GND
HCEN
HCA0
HCA1
HCA2
HCA3
GND
VCC
HCA4
HCA5
HCA6
HCA7
GND
VCC
HCF0
HCF1
HCF2
HCF3
HCF4
HCF5
GND
VCC
HCF6
HCF7
HCF8
HCF9
HCF10
HCF11
HLD
GND
GND
VCC
VCC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VCC
GND
GND
HSHEN
HACC
HRSL0
HRSL1
HRSL2
HRSL3
GEN
GND
VCC
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
VCC
GND
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
GND
VCC
VRSL3
VRSL2
VRSL1
VRSL0
VACC
GND
GND
VCC
Package and Ordering Information
Plastic Quad Flatpack (Q5)
0°C to 70°C--Commercial Screening
Speed
9 ns
9 ns
LF3311QC9
LF3311QC9G (GREEN)
LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and
to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current
and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed
the purchase price of LOGIC Devices products. LOGIC Devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety
applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user.
LOGIC Devices Incorporated
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Video Imaging Products
9/19/05 LDS.3311-C