LF3330 LF3330 DEVICES INCORPORATED Vertical Digital Image Filter Vertical Digital Image Filter DEVICES INCORPORATED FEATURES DESCRIPTION 83 MHz Data Rate 12-bit Data and Coefficients On-board Memory for 256 Coefficient Sets LF InterfaceTM Allows All 256 Coefficient Sets to be Updated Within Vertical Blanking Selectable 16-bit Data Output with User-Defined Rounding and Limiting Seven 3K x 12-bit, Programmable Two-Mode Line Buffers Separate Input Port for Odd and Even Field Filtering 8 Filter Taps Cascadable for More Filter Taps Supports Interleaved Data Streams 3.3 Volt Power Supply 5 Volt Tolerant I/O 100 Lead PQFP The LF3330 filters digital images in the vertical dimension at real-time video rates. The input and coefficient data are both 12 bits and in two’s complement format. The output is also in two’s complement format and may be rounded to 16 bits. The filter is an 8-tap FIR filter with all required line buffers contained onchip. The line buffers can store video lines with lengths from 4 to 3076 pixels. data streams. The number of interleaved data sets that the device can handle is limited only by the length of the on-chip line buffers. If the interleaved video line has 3076 data values or less, the filter can handle it. The LF3330 contains enough on-board memory to store 256 coefficient sets. The LF InterfaceTM allows all 256 coefficient sets to be updated within vertical blanking. Selectable 16-bit data output with Multiple LF3330s can be cascaded user-defined rounding and limiting together to create larger vertical filters. minimizes the constraints put on coefficient sets for various filter impleDue to the length of the line buffers, mentations. interleaved data can be fed directly into the device and filtered without SIGNAL DEFINITIONS separating the data into individual LF3330 BLOCK DIAGRAM DIN11-0 12 3K LINE BUFFER 3K LINE BUFFER VB11-0 12 3K LINE BUFFER 3K LINE BUFFER 8-TAP VERTICAL FILTER 256 COEFFICIENT SET STORAGE 3K LINE BUFFER 32 ROUND SELECT LIMIT CIRCUITRY 16 DOUT15-0 OED 3K LINE BUFFER 3K LINE BUFFER 12 COUT11-0 OEC Video Imaging Products 1 9/19/2005–LDS.3330-N 2 CLK PAUSE LD CF11-0 COUT11-0 12 12 12 12 CONFIGURATION AND CONTROL REGISTERS LF INTERFACE 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 24 12 Coef Bank 2 Coef Bank 3 24 12 Coef Bank 1 24 12 Coef Bank 0 24 12 24 24 12 12 24 12 12 12 12 12 Coef Bank 4 24 12 12 Coef Bank 5 12 12 12 Coef Bank 6 26 26 ACC 32 "0" 4 RSL3-0 16 OED 16 DOUT15-0 DEVICES INCORPORATED OEC VB11-0 DIN11-0 SHEN Coef Bank 7 ROUND 8 LIMIT CA7-0 SELECT CEN LF3330 Vertical Digital Image Filter FIGURE 1. LF3330 FUNCTIONAL BLOCK DIAGRAM Video Imaging Products 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Power Vertical Digital Image Filter FIGURE 2. INPUT FORMATS VCC and GND Input Data +3.3 V power supply. All pins must be connected. 11 10 9 211 210 29 2 1 0 22 21 20 (Sign) Clock Coefficient Data 11 10 9 20 2 1 2 2 (Sign) 2 1 0 2 9 2 10 2 11 CLK — Master Clock The rising edge of CLK strobes all enabled registers. TABLE 1. OUTPUT FORMATS SLCT4-0 S15 S14 S13 Inputs 00000 F15 F14 F13 DIN11-0 — Data Input 00001 F16 F15 F14 DIN11-0 is the 12-bit registered data input port. Data is latched on the rising edge of CLK. 00010 F17 F16 F15 01110 F29 F28 F27 01111 F30 F29 F28 10000 F31 F30 F29 VB11-0 — Field Filtering Data Input VB11-0 is the 12-bit registered data input port used only when implementing Odd and Even Field Filtering (see Functional Description section for a full discussion). Data is latched on the rising edge of CLK. CF11-0 — Coefficient Input CF11-0 is used to load data into the coefficient banks and configuration/ control registers. Data present on CF11-0 is latched into the LF InterfaceTM on the rising edge of CLK when LD is LOW (see the LF InterfaceTM section for a full discussion). CA7-0 — Coefficient Address CA7-0 determines which row of data in the coefficient banks is fed to the multipliers. CA7-0 is latched into the Coefficient Address Register on the rising edge of CLK when CEN is LOW. Outputs DOUT15-0 — Data Output DOUT15-0 is the 16-bit registered data output port. · · · · · · · · · · · · ··· ··· ··· ··· ··· ··· ··· COUT11-0 — Cascade Data Output COUT11-0 is a 12-bit cascade output port. COUT11-0 on one device should be connected to DIN11-0 of another LF3330. S8 S7 F8 F7 F9 F8 F10 F9 · · · · · · F22 F21 F23 F22 F24 F23 ··· ··· ··· ··· S2 S1 S0 F2 F1 F0 F3 F2 F1 F4 F3 F2 ··· ··· ··· F16 F15 F14 · · · · · · · · · F17 F16 F15 F18 F17 F16 FIGURE 3. ACCUMULATOR FORMAT Accumulator Output 31 30 29 220 219 218 (Sign) 2 1 0 2 9 2 10 2 11 Controls LD — Coefficient Load When LD is LOW, data on CF11-0 is latched into the LF InterfaceTM on the rising edge of CLK. When LD is HIGH, data can not be latched into the LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of LD is required in order for the input circuitry to function properly. Therefore, LD must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). PAUSE — LF InterfaceTM Pause When PAUSE is HIGH, the LF InterfaceTM loading sequence is halted until PAUSE is returned to a LOW state. This effectively allows the user to load coefficients and control registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). CEN — Coefficient Address Enable When CEN is LOW, data on CA7-0 is latched into the Coefficient Address Register on the rising edge of CLK. When CEN is HIGH, data on CA7-0 is not latched and the register’s contents will not be changed. Video Imaging Products 3 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter TABLE 2. CONFIGURATION REGISTER 0 – ADDRESS 200H FIGURE 4. RSL CIRCUITRY BITS FUNCTION DESCRIPTION RSL3-0 DATA IN 11-0 Line Buffer Length See Line Buffer Description Section 4 32 TABLE 3. CONFIGURATION REGISTER 1 – ADDRESS 201H DESCRIPTION 0 : Delay Mode 1 Line Buffer Load 1 : Recirculate Mode 0 : Normal Load 2 Odd and Even Field 0 : VB Port Disabled Filtering Port Enable 1 : VB Port Enabled Odd and Even Field 0 : VB Line Buffer Disabled Filtering Line Buffer Enable 1 : VB Line Buffer Enabled Reserved Must be set to “0” R0 FUNCTION Line Buffer Mode 1 : Parallel Load 11-4 32 5 SELECT S15 3 RND R15 32 S0 BITS 0 TABLE 4. CONFIGURATION REGISTER 2 – ADDRESS 202H FUNCTION Limit Enable 16 DESCRIPTION 0 : Limiting Disabled L0 BITS 0 32 1 : Limiting Enabled Reserved Must be set to “0” L15 11-1 LIMIT TABLE 5. CONFIGURATION REGISTER 3 – ADDRESS 203H BITS 0 FUNCTION Cascade Mode DESCRIPTION 0 : First Device RSL CIRCUITRY 1 : Cascaded Device 11-1 Reserved ACC — Accumulator Control When ACC is HIGH, the accumulator is enabled for accumulation and the accumulator output register is disabled for loading. When ACC is LOW, no accumulation is performed and the accumulator output register is enabled for loading. ACC is latched on the rising edge of CLK. SHEN — Shift Enable SHEN enables or disables the loading of data into the input/cascade registers and the line buffers. When SHEN is LOW, data is loaded into the input/ cascade registers and shifted through 16 DATA OUT Must be set to “0” the line buffers on the rising edge of CLK. When SHEN is HIGH, data can not be loaded into the input/cascade registers or shifted through the line buffers and their contents will not be changed. RSL3-0 — Round/Select/Limit Control RSL3-0 determines which of the sixteen user-programmable round/ select/limit registers are used in the round/select/limit circuitry. A value of 0 on RSL3-0 selects round/select/ limit register 0. A value of 1 selects round/select/limit register 1 and so on. RSL3-0 is latched on the rising edge of CLK (see the round, select, and limit sections for a complete discussion). OED — DOUT Output Enable When OED is LOW, DOUT15-0 is enabled for output. When OED is HIGH, DOUT15-0 is placed in a highimpedance state. OEC — COUT Output Enable When OEC is LOW, COUT15-0 is enabled for output. When OEC is HIGH, COUT15-0 is placed in a highimpedance state. FUNCTIONAL DESCRIPTION Video Imaging Products 4 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter Line Buffers The maximum delay length of each line buffer is 3076 cycles and the minimum is 4 cycles. Configuration Register 0 (CR0) determines the delay length of the line buffers. The line buffer length is equal to the value of CR0 plus 4. A value of 0 for CR0 sets the line buffer length to 4. A value of 3072 for CR0 sets the line buffer length to 3076. Any values for CR0 greater than 3072 are not valid. The line buffers have two modes of operation: delay mode and recirculate mode. Bit 0 of Configuration Register 1 determines which mode the line buffers are in. In delay mode, the data input to the line buffer is delayed by an amount determined by CR0. In recirculate mode, the output of the line buffer is routed back to the input of the line buffer allowing the line buffer contents to be read multiple times. Bit 1 of Configuration Register 1 allows the line buffers to be loaded in parallel. When Bit 1 is “1”, the input register (DIN11-0) loads all seven line buffers in parallel. This allows all FIGURE 5. DIN 12 the line buffers to be preloaded with data in the amount of time it normally takes to load a single line buffer. A cascade port is provided to allow cascading of multiple devices for more filter taps (see Figure 5). COUT11-0 Odd and Even Field Filtering of one device should be connected to The LF3330 is capable of odd and even DIN11-0 of another device. As many LF3330s as desired may be cascaded field filtering. Bit 2 of Configuration together. However, the outputs of the Register 1 enables the VB Data Input LF3330s must be added together with port required for odd and even field external adders. filtering. Bit 3 of the same configuration register enables the line buffer in The first line buffer on a cascaded the VB Data path. Line buffer length device must have its length shortened is set to the length written to Configu- by two delays. This is to account for ration Register 0. If line buffer parallel the added delays of the input register load is enabled and odd and even field on the device and the cascade output filtering is enabled, the data for the VB register from the previous LF3330. If line buffer comes from the VB Data Bit 0 of Configuration Register 3 is Input port. set to “1”, the length of the first line Interleaved Data The LF3330 is capable of handling interleaved data. The number of data sets it can handle is determined by the number of data values contained in a video line. If the interleaved video line has 3076 data values or less, the LF3330 can handle it no matter how many data sets are interleaved together. MULTIPLE LF3330S CASCADED TOGETHER LF3330 LINE BUFFERS LF3330 COUT DIN Cascading LINE BUFFERS buffer will be reduced by two. This will make its effective length the same as the other line buffers on the device. If Bit 0 of Configuration Register 3 is set to “0”, the length of the first line buffer will be the same as the other line buffers. When cascading devices, the first LF3330 should have Bit 0 of Configuration Register 3 set to “0”. Any LF3330s cascaded after the first LF3330 should have Bit 0 of Configu- LF3330 COUT DIN LINE BUFFERS LF3330 COUT DIN LINE BUFFERS VERTICAL FILTER VERTICAL FILTER VERTICAL FILTER VERTICAL FILTER RSL CIRCUIT RSL CIRCUIT RSL CIRCUIT RSL CIRCUIT LF3347 25 25 RSL CIRCUIT 16 DATA OUT 29 TAP RESULT Video Imaging Products 5 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter ration Register 3 set to “1”. When not cascading, Bit 0 of Configuration Register 3 should be set to “0”. It is important to note that the first multiplier on all cascaded devices should not be used. This is because the first multiplier does not have a line buffer in front of it. The coefficient value sent to the first multiplier on a cascaded device should be “0”. Rounding The filter output may be rounded by adding the contents of one of the sixteen round registers to the filter output (see Figure 4). Each round register is 32 bits wide and user-programmable. This allows the filter’s output to be rounded to any precision required. Since any 32-bit value may be programmed into the round regis- ters, the device can support complex rounding algorithms as well as standard half-LSB rounding. RSL3-0 determines which of the sixteen round registers are used in the rounding operation. A value of 0 on RSL3-0 selects round register 0. A value of 1 selects round register 1 and so on. RSL3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. Round register loading is discussed in the LF InterfaceTM section. sent to DOUT15-0. The select circuitry determines which 16 bits are passed (see Table 1). There are sixteen select registers which control the select circuitry. Each select register is 5 bits wide and user-programmable. RSL3-0 determines which of the sixteen select registers are used in the select circuitry. Select register 0 is chosen by loading a 0 on RSL3-0. Select register 1 is chosen by loading a 1 on RSL3-0 and so on. RSL3-0 may be changed every clock cycle if desired. This allows the 16-bit window to be changed every clock cycle. This is useful when filtering interleaved data. Select register loading is discussed in the LF InterfaceTM section. Output Select Limiting The word width of the filter output is 32 bits. However, only 16 bits may be An output limiting function is provided for the output of the filter. FIGURE 6. COEFFICIENT BANK LOADING SEQUENCE COEFFICIENT SET 1 COEFFICIENT SET 2 COEFFICIENT SET 3 CLK W1 W2 W3 LD ADDR1 CF11-0 COEF0 COEF7 ADDR2 COEF0 COEF7 ADDR3 COEF0 COEF7 W1: Coefficient Set 1 written to coefficient banks during this clock cycle. W2: Coefficient Set 2 written to coefficient banks during this clock cycle. W3: Coefficient Set 3 written to coefficient banks during this clock cycle. FIGURE 7. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE CONFIG REG ROUND REGISTER SELECT REG LIMIT REGISTER CLK W1 W2 W3 W4 LD CF11-0 ADDR1 DATA1 ADDR2 DATA1 ADDR3 DATA1 DATA2 DATA3 DATA4 ADDR4 DATA1 DATA2 DATA3 DATA4 W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge. W3: Round Register loaded with new data on this rising clock edge. W4: Limit Register loaded with new data on this rising clock edge. Video Imaging Products 6 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter The limit registers determine the valid range of output values when limiting is enabled (Bit 0 in Configuration Register 2). There are sixteen 32-bit limit registers. RSL3-0 determines which limit register is used during the limit operation. A value of 0 on RSL3-0 selects limit register 0. A value of 1 selects limit register 1 and so on. Each limit register contains both an upper and lower limit value. If the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. RSL3-0 may be changed every clock cycle if desired. This allows the limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is discussed in the LF InterfaceTM section. select, and limit. There are sixteen round registers. Each round register is 32 bits wide. RSL3-0 determines which round register is used for rounding. Coefficient Banks There are sixteen select registers. Each select register is 5 bits wide. RSL3-0 determines which select register is used for the select circuitry. The coefficient banks store the coefficients which feed into the multipliers in the filter. There is a separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks are loaded using the LF InterfaceTM. Coefficient bank loading is discussed in the LF InterfaceTM section. Configuration and Control Registers The configuration registers determine how the LF3330 operates. Tables 2 through 5 show the formats of the four configuration registers. There are three types of control registers: round, There are sixteen limit registers. Each limit register is 32 bits wide and stores both an upper and lower limit value. The lower limit is stored in bits 15-0 and the upper limit is stored in bits 31-16. RSL3-0 determines which limit register is used for limiting when limiting is enabled. Configuration and control register loading is discussed in the LF InterfaceTM section. LF InterfaceTM The LF InterfaceTM is used to load FIGURE 8. COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION COEFFICIENT SET 1 CLK W1 PAUSE LD ADDR1 CF11-0 COEF0 COEF1 COEF7 W1: Configuration Register loaded with new data on this rising clock edge. FIGURE 9. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION SELECT REGISTER CONFIGURATION REGISTER CLK W1 W2 PAUSE LD CF11-0 ADDR1 DATA1 ADDR2 DATA1 W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge. Video Imaging Products 7 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter data into the coefficient banks and configuration/control registers. LD is used to enable and disable the LF InterfaceTM. When LD goes LOW, the LF InterfaceTM is enabled for data input. The first value fed into the interface on CF11-0 is an address which determines what the interface is going to load. The three most significant bits (CF11-9) determine if the LF InterfaceTM will load coefficient banks or configuration/control registers (see Table 6). The nine least significant bits (CF8-0) are the address for whatever is to be loaded (see Tables 7 through 9). For example, to load address 15 of the coefficient banks, the first data FIGURE 10. ROUND REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION ROUND REGISTER CLK W1 PAUSE LD ADDR1 CF11-0 DATA1 DATA2 DATA3 DATA4 W1: Round Register loaded with new data on this rising clock edge. FIGURE 11. LIMIT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION LIMIT REGISTER CLK W1 PAUSE LD CF11-0 ADDR1 DATA1 DATA2 DATA3 DATA4 W1: Limit Register loaded with new data on this rising clock edge. TABLE 10. COEFFICIENT BANK LOADING FORMAT 1st Word - Address 2nd Word - Bank 0 3rd Word - Bank 1 4th Word - Bank 2 5th Word - Bank 3 6th Word - Bank 4 7th Word - Bank 5 8th Word - Bank 6 9th Word - Bank 7 CF11 0 0 0 1 1 0 1 1 0 CF10 0 0 1 1 0 1 0 1 0 CF9 0 1 0 0 0 1 0 1 0 CF8 0 0 1 0 1 1 0 1 1 CF7 0 0 0 0 1 0 0 0 0 CF6 0 0 1 1 1 0 0 0 1 CF5 0 0 0 1 1 0 1 1 0 CF4 0 1 0 1 0 0 1 0 0 CF3 1 0 0 0 0 0 0 0 0 CF2 0 0 0 1 0 0 0 0 0 CF1 1 0 1 1 1 0 1 0 1 CF0 0 0 1 0 1 1 0 0 1 Video Imaging Products 8 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter value into the LF InterfaceTM should be 00FH. To load limit register 10, the first data value should be E0AH. The first address value should be loaded into the interface on the same clock cycle that latches the HIGH to LOW transition of LD (see Figures 6 and 7). The next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defined by the address value. When loading coefficient banks, the interface will expect eight values to be loaded into the device after the address value. The eight values are coefficients 0 through 7. When loading configuration or select registers, the interface will expect one value after the address value. When loading round or limit registers, the interface will expect four values after the address value. Figures 6 and 7 show the data loading sequences for the coefficient banks and configuration/control registers. PAUSE allows the user to effectively slow the rate of data loading through the LF InterfaceTM. When PAUSE is HIGH, the LF InterfaceTM is held until TABLE 6. CF11-9 DECODE 11 0 0 0 1 10 0 0 1 0 9 0 1 1 1 TABLE 7. ROUND REGISTERS DESCRIPTION Coefficient Banks Configuration Registers Select Registers Round Registers REGISTER 0 1 ADDRESS (HEX) A00 A01 14 A0E 15 A0F 1 1 1 Limit Registers PAUSE is returned to a LOW. Figures 8 through 11 display the effects of PAUSE while leading coefficient and control data. Table 10 shows an example of loading data into the coefficient banks. The following data values are written into address 10 of coefficient banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 11 shows an example of loading data into a configuration register. Data value 003H is written into Configuration Register 2. Table 12 shows an example of loading data into a round register. Data value 7683F4A2H is written into round register 12. Table 13 shows an example of loading data into a select register. Data value 00FH is loaded into select register 2. Table 14 shows an example of loading data TABLE 8. SELECT REGISTERS REGISTER 0 1 ADDRESS (HEX) 600 601 14 60E 15 60F TABLE 9. LIMIT REGISTERS REGISTER 0 1 ADDRESS (HEX) E00 E01 14 E0E 15 E0F TABLE 11. CONFIGURATION REGISTER LOADING FORMAT 1st Word - Address 2nd Word - Data CF11 0 0 CF10 0 0 CF9 1 0 CF8 0 0 CF7 0 0 CF6 0 0 CF5 0 0 CF4 0 0 CF3 0 0 CF2 0 0 CF1 1 1 CF0 0 1 CF7 0 1 1 1 0** CF6 0 0 1 0 1 CF5 0 1 1 0 1 CF4 0 0 1 0 1 CF3 1 0 0 0 0 CF2 1 0 1 0 1 CF1 0 1 0 1 1 CF0 0 0* 0 1 0 TABLE 12. ROUND REGISTER LOADING FORMAT 1st Word - Address 2nd Word - Data 3rd Word - Data 4th Word - Data 5th Word - Data CF11 1 R R R R CF10 0 R R R R CF9 1 R R R R CF8 0 R R R R R = Reserved. Must be set to “0”. * This bit represents the LSB of the Round Register. ** This bit represents the MSB of the Round Register. Video Imaging Products 9 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter into limit register 7. Data value 3B60H is loaded as the lower limit and 72A4H is loaded as the upper limit. It takes 9S clock cycles to load S coefficient sets into the device. Therefore, it takes 2304 clock cycles to load all 256 coefficient sets. Assuming an 83 MHz clock rate, all 256 coefficient sets can be updated in less than 27.7 µs, which is well within vertical blanking time. It takes 5S clock cycles to load S round or limit registers. Therefore, it takes 160 clock cycles to update all round and limit registers. Assuming an 83 MHz clock rate, all round/limit registers can be updated in 1.92 µs. The coefficient banks and configuration/control registers are not loaded with data until all data values for the specified address are loaded into the LF InterfaceTM. In other words, the coefficient banks are not written to until all eight coefficients have been loaded into the LF InterfaceTM. A round register is not written to until all four data values are loaded. is done by setting LD HIGH on the clock cycle after the clock cycle which latches the last data value. It is important that the LF InterfaceTM remain disabled when not loading data into it. After the last data value is loaded, the interface will expect a new address value on the next clock cycle. After the next address value is loaded, data loading will begin again as previously discussed. As long as data is loaded into the interface, LD must remain LOW. After all desired coefficient banks and configuration/control registers are loaded with data, the LF InterfaceTM must be disabled. This TABLE 13. SELECT REGISTER LOADING FORMAT 1st Word - Address 2nd Word - Data CF11 0 0 CF10 1 0 CF9 1 0 CF8 0 0 CF7 0 0 CF6 0 0 CF5 0 0 CF4 0 0 CF3 0 1 CF2 0 1 CF1 1 1 CF0 0 1 CF7 0 0 0* 1 0** CF6 0 1 0 0 1 CF5 0 1 1 1 1 CF4 0 0 1 0 1 CF3 0 0 1 0 0 CF2 1 0 0 1 0 CF1 1 0 1 0 1 CF0 1 0 1 0 0 TABLE 14. LIMIT REGISTER LOADING FORMAT 1st Word - Address 2nd Word - Data 3rd Word - Data 4th Word - Data 5th Word - Data CF11 1 R R R R CF10 1 R R R R CF9 1 R R R R CF8 0 R R R R R = Reserved. Must be set to “0”. * This bit represents the MSB of the Lower Limit. ** This bit represents the MSB of the Upper Limit. Video Imaging Products 10 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ............................................................................................................ –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +4.5 V Input signal with respect to ground .......................................................................................... –0.5 V to 5.5 V Signal applied to high impedance output ................................................................................. –0.5 V to 5.5 V Output current into low outputs ............................................................................................................ 25 mA Latchup current ............................................................................................................................... > 400 mA ESD Classification (MIL-STD-883E METHOD 3015.7) ....................................................................... Class 3 OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 3.00 V ≤ VCC ≤ 3.60 V –55°C to +125°C 3.00 V ≤ VCC ≤ 3.60 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –4 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 8.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.4 V 2.0 5.5 V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±10 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 240 mA ICC2 VCC Current, Quiescent (Note 7) 1 mA CIN Input Capacitance TA = 25°C, f = 1 MHz 10 pF COUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF Video Imaging Products 11 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) 25* Min 18* Max Min LF3330– 15 Max Min 12 Symbol Parameter tCYC Clock Cycle Time 25 18 15 Max Min 12 Max tPW Clock Pulse Width 10 8 7 5 tS Input Setup Time 8 6 5 4 tH Input Hold Time 0.5 0.5 0.5 0.5 tDD Data Output Delay 13 9 10 8 tDC Cascade Data Output Delay 13 9 10 9 tDIS Three-State Output Disable Delay (Note 11) 15 11 12 10 tENA Three-State Output Enable Delay (Note 11) 15 11 12 10 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) LF3330– 18* 25* Min Symbol Parameter tCYC Clock Cycle Time 25 18 15 tPW Clock Pulse Width 10 8 7 tS Input Setup Time 8 6 5 tH Input Hold Time 0.5 0.5 0.5 tDD Data Output Delay 13 9 10 tDC Cascade Data Output Delay 13 9 10 tDIS Three-State Output Disable Delay (Note 11) 15 11 12 tENA Three-State Output Enable Delay (Note 11) 15 11 12 SWITCHING WAVEFORMS: Max Min 15* Max Min Max DATA I/O 1 2 3 4 5 6 7 CLK tH tS DIN11-0 tPW DINN DINN+1 CA7-0 CAN CAN+1 VB11-0 VBN VBN+1 tCYC tPW CONTROLS (Except OE) OE tDIS DOUT15-0 tENA tDD HIGH IMPEDANCE DOUTN-1 DOUTN tDC COUT11-0 HIGH IMPEDANCE COUTN-1 *DISCONTINUED SPEED GRADE COUTN Video Imaging Products 12 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter COMMERCIAL OPERATING RANGE (0°C to +70°C) 25* Min 18* Max Min LF3330– 15 Max Min 12 Symbol Parameter tCFS Coefficient Input Setup Time 8 6 5 Max Min 5 tCFH Coefficient Input Hold Time 0 0 0 0 tLS Load Setup Time 8 7 6 4 tLH Load Hold Time 0 0 0 0 tPS PAUSE Setup Time 8 6 5 4 tPH PAUSE Hold Time 0.5 0.5 0.5 0.5 Max MILITARY OPERATING RANGE (–55°C to +125°C) LF3330– 18* 25* Min Symbol Parameter tCFS Coefficient Input Setup Time 8 6 5 tCFH Coefficient Input Hold Time 0 0 0 tLS Load Setup Time 8 7 6 tLH Load Hold Time 0 0 0 tPS PAUSE Setup Time 8 6 5 tPH PAUSE Hold Time 0.5 0.5 0.5 SWITCHING WAVEFORMS: Max Min Max 15* Min Max LF INTERFACETM 1 2 3 4 5 6 CLK tLS tPW tLH tPW tCYC LD tPS tPH PAUSE tCFS CF11–0 tCFH ADDRESS CF0 CF1 *DISCONTINUED SPEED GRADE CF2 Video Imaging Products 13 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. but not 100% tested. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. case operation of any device always provides data within that time. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, VTH, is set at 3.0 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z-to-1 and 1-to-Z tests. 2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. 12. These parameters are only tested at Nevertheless, conventional precauthe high temperature extreme, which is tions should be observed during storthe worst case for leakage current. age, handling, and use of these circuits This device has high-speed outputs in order to avoid exposure to excessive capable of large instantaneous current electrical stress values. pulses and fast turn-on/turn-off times. 3. This device provides hard clamping As a result, care must be exercised in of transient undershoot. Input levels the testing of this device. The following below ground will be clamped begin- measures are recommended: ning at –0.6 V. The device can withstand indefinite operation with inputs a. A 0.1 µF ceramic capacitor should S1 or outputs in the range of –0.5 V to be installed between VCC and Ground DUT IOL leads as close to the Device Under Test +5.5 V. Device operation will not be (DUT) as possible. Similar capacitors VTH CL adversely affected, however, input should be installed between device IOH current levels will be well in excess VCC and the tester common, and device of 100 mA. ground and tester common. 4. Actual test conditions may vary FIGURE B. THRESHOLD LEVELS from those designated but operation is b. Ground and VCC supply planes tENA tDIS must be brought directly to the DUT guaranteed as specified. OE 1.5 V 1.5 V socket or contactor fingers. 5. Supply current for a given applica3.0V Vth Z 0 1.5 V tion can be accurately approximated c. Input voltages on a test fixture VOL* 0.2 V 0 Z should be adjusted to compensate for by: 2 1 Z inductive ground and VCC noise to NCV F 0.2 V VOH* 1.5 V 0V Vth Z 1 maintain required DUT input levels 4 VOL* Measured VOL with IOH = –10mA and IOL = 10mA relative to the DUT ground pin. VOH* Measured VOH with IOH = –10mA and IOL = 10mA where 10. Each parameter is shown as a N = total number of device outputs minimum or maximum value. Input C = capacitive load per output requirements are specified from the V = supply voltage point of view of the external system F = clock frequency driving the chip. Setup time, for example, is specified as a minimum 6. Tested with outputs changing every since the external system must supply cycle and no load, at a 40 MHz clock at least that much time to meet the rate. worst-case requirements of all parts. 7. Tested with all inputs within 0.1 V of Responses from the internal circuitry are specified from the point of view of VCC or Ground, no load. the device. Output delay, for example, 8. These parameters are guaranteed is specified as a maximum since worst- Video Imaging Products 14 9/19/2005–LDS.3330-N LF3330 DEVICES INCORPORATED Vertical Digital Image Filter ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top View 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 OED VCC CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10 CF11 LD PAUSE VCC GND COUT0 COUT1 COUT2 COUT3 COUT4 COUT5 COUT6 COUT7 COUT8 COUT9 COUT10 COUT11 GND VCC VB0 VB1 VB2 VB3 VB4 VB5 VCC CLK GND VB6 VB7 VB8 VB9 VB10 VB11 OEC VCC GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND ACC RSL0 RSL1 RSL2 RSL3 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CEN VCC GND SHEN DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GND VCC DOUT15 DOUT14 DOUT13 DOUT12 DOUT11 DOUT10 DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 VCC GND 100-pin Speed Plastic Quad Flatpack (Q2) 0°C to +70°C — COMMERCIAL SCREENING 15 ns 12 ns 12 ns LF3330QC15 LF3330QC12 LF3330QC12G (GREEN) LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the purchase price of LOGIC Devices products. LOGIC Devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. Video Imaging Products 15 9/19/2005–LDS.3330-N