DA6181B.002 5 May, 2011 MAS6181B AM Receiver IC • • • • • • • • Dual Band Receiver IC High Sensitivity Very Low Power Consumption Wide Supply Voltage Range Power Down Control Control for AGC On High Selectivity by Crystal Filter Fast Startup Feature DESCRIPTION The MAS6181 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiving. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. FEATURES APPLICATIONS • • • • • • • • • • • The MAS6181 supports receiving two different frequency signals by two selective crystal filters and an integrated switch to switch between two antenna frequencies. It has differential input for improved common mode disturbance rejection. Dual Band Receiver IC Highly Sensitive AM Receiver Wide Supply Voltage Range from 1.1 V to 3.6 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On Wide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter Differential Input • Multi Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HBG (Switzerland) and BPC (China) BLOCK DIAGRAM VDD RFIP QO2 QO1 AON QI VDD AGC Amplifier Demodulator & Comparator OUT RFIM RFI2 Power Supply/Biasing VDD VSS PDN1 PDN2 AGC DEC 1 (15) DA6181B.002 5 May, 2011 PAD LAYOUT MAS6181B1 1st bond! VDD RFI2 QO1 RFIM QI RFIP AGC Do not bond! 1530 µm RFI2B RFIMB QO2 VSS PDN1 PDN2 AON OUT DEC 1120 µm DIE size = 1120 x 1530 µm; rectangular PAD 80 µm x 80 µm Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Name X-coordinate Y-coordinate Power Supply Voltage Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 Quartz Filter Input for Crystals AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 Positive Receiver Input Negative Receiver Input Test pad RFIMB Test pad RFI2B Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground VDD QO2 QO1 QI AGC PDN2 OUT DEC AON PDN1 RFIP RFIM RFIMB RFI2B RFI2 VSS 126 µm 126 µm 126 µm 126 µm 126 µm 126 µm 126 µm 994 µm 994 µm 994 µm 994 µm 994 µm 298 µm 400 µm 994 µm 994 µm 1332 µm 1132 µm 962 µm 788 µm 614 µm 440 µm 263 µm 266 µm 450 µm 618 µm 807 µm 985 µm 1025 µm 1025 µm 1163 µm 1321 µm Note 1 2 3 1 4 4 5 5 Notes: 1) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power on 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - The output is a current source/sink with |IOUT| > 5 µA - At power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation) - Unused AON pad can be left unconnected due to internal pull-up with current < 1 µA. Pull up current is switched off at power down. 4) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD 5) RFIMB and RFI2B pads are left unconnected. They are only for wafer level testing purposes 2 (15) DA6181B.002 5 May, 2011 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Supply Voltage Input Voltage Operating Temperature Storage Temperature VDD-VSS VIN TOP TST Conditions Min Max Unit -0.3 VSS-0.3 -40 -55 3.6 VDD+0.3 +85 +150 V V o C o C Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will not be destroyed. ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 1.5V, Temperature = 27°C unless otherwise noted Parameter Operating Voltage Current Consumption Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Receiver Input Resistance Receiver Input Capacitance RFI2 Switch On Resistance RFI2 Switch Off Capacitance Input Levels |lIN|<0.5 µA Output Current VOL<0.2 VDD;VOH >0.8 VDD DCF77 Output Pulses Symbol VDD IDD IDDoff fIN VIN min VIN max RRFI CRFI RON2 COFF2 VIL VIH |IOUT| Startup Time T 100ms T 200ms T 100ms T 200ms T 300ms T 500ms T 200ms T 500ms T 800ms T 200ms T 500ms T 800ms T 200ms T 500ms T 800ms TStart Output Delay Time TDelay MSF Output Pulses WWVB Output Pulses JJY60 Output Pulses JJY40 Output Pulses Conditions VDD=1.5 V, Vin=0 µVrms VDD=1.5 V, Vin=20 mVrms VDD=3.6 V, Vin=0 µVrms VDD=3.6 V, Vin=20 mVrms Min Typ Max Unit 1.10 1.5 66 40 68 42 3.6 V 31 24 40 0.4 µA 85 65 0.1 100 1 20 f=40kHz...77.5 kHz 600 1.1 5 20 VDD=1.4 V 15 0.35 VDD-0.35 5 1 µVrms ≤ VIN ≤ 20 mVrms, see note below! 1 µVrms ≤ VIN ≤ 20 mVrms, see note below! 1 µVrms ≤ VIN ≤ 20 mVrms, see note below! 1 µVrms ≤ VIN ≤ 20 mVrms, see note below! 1 µVrms ≤ VIN ≤ 20 mVrms, see note below! Fast Start-up, Vin=0.4 µVrms Fast Start-up, Vin=20 mVrms µA kHz µVrms mVrms kΩ pF Ω pF V µA 95 195 120 220 320 520 200 500 800 210 505 800 200 495 790 1.3 3.5 50 ms ms ms ms ms s 100 ms Note: Stand-by current consumption may increase if V IH and V IL differ from VDD and GND respectively. Note: See Note 6: Time Signal Software’s Pulse Width Recognition Limits and Table 5 on page 9! 3 (15) DA6181B.002 5 May, 2011 FREQUENCY SELECTION The power down control and frequency selection using internal antenna’s tuning capacitor switch (RFI2) are achieved by two digital control pins Table 1. Frequency selection and power down control PDN1 PDN2 RFI2 Switch High High Low Low High Low High Low Open Open Closed Closed PDN1 and PDN2. The control logic is presented in table 1. Description Power down Antenna frequency 1 Antenna frequency 2, RFI2 capacitor connected in parallel with antenna Antenna frequency 2, RFI2 capacitor connected in parallel with antenna If frequency 1 is selected the RFI2 switch is open (non conductive). Antenna frequency is determined by antenna inductor LANT (see Typical Application on page 5), antenna capacitor CANT1 and parasitic capacitances related to antenna coil, inputs RFIP, RFIM and RFI2 (see Antenna Tuning Considerations below). Frequency 1 is the highest frequency of the two selected frequencies. If frequency 2 is selected then RFI2 switch is closed to connect CANT2 to pin RFIM in parallel with ferrite antenna and tune it to frequency 2. Frequency 2 is the lowest frequencies. frequency of the two selected It is recommended to switch the device to power down for at least 50ms before switching to another frequency. This guarantees fast startup in switching to another frequency. During minimum 50ms power down time the AGC capacitor voltage is completely pulled to VDD to initialize proper startup conditions for the AGC. Without the described proper fast startup control the startup time can be several minutes. With fast startup it is shortened typically to a few seconds. ANTENNA TUNING CONSIDERATIONS The ferrite bar antenna having inductance LANT and parasitic coil capacitance CCOIL is tuned to two reception frequencies f1 and f2 by parallel capacitors CANT1 and CANT2. The receiver input stage and internal antenna capacitor switches have capacitances CRFI and COFF2 which affect the resonance frequencies. COFF2 is switch capacitance when switch is open. When the antenna switch is closed the off capacitance is shorted by on resistance of the switch and it is effectively eliminated. Following relationships can be written for the two tuning frequencies. Frequency f1 (highest frequency): CTOT1~CCOIL+CANT1+CRFI+COFF2, assuming CANT2>>COFF2 1 f1 = 2π L ANT ⋅ CTOT 1 Frequency f2 (lowest frequency): CTOT2=CCOIL+CANT1+CANT2+CRFI 1 f2 = 2π L ANT ⋅ CTOT 2 4 (15) DA6181B.002 5 May, 2011 TYPICAL APPLICATION Note 1 VDD Note 5 CANT1 LANT CANT2 RFIP X2 Note 4 X1 Optional Control for AGC on/hold QO2 QO1 AON QI Demodulator & Comparator VDD AGC Amplifier OUT Receiver Output RFIM Ferrite Antenna RFI2 Power Supply/Biasing VDD VSS PDN1 PDN2 VBATTERY AGC DEC CDEC 47 nF CAGC 10 µF Power Down / VDD VDD Note 3 Fast Startup / Note 2 Frequency Selection Figure 1. Application circuit of dual band receiver MAS6181 X2 40003 Hz Note 1 Note 4 X1 60003 Hz VDD Note 5 LANT 3.64 mH CANT1 1.9 nF Ferrite Antenna CANT1 2.4 nF RFIP QO2 QO1 Optional Control for AGC on/hold AON QI VDD AGC Amplifier Demodulator & Comparator OUT Receiver Output RFIM RFI2 Power Supply/Biasing VDD VBATTERY VSS PDN1 PDN2 AGC DEC CAGC 10 µF CDEC 47 nF Power Down / VDD VDD Note 3 Fast Startup / Note 2 Frequency Selection Figure 2. Example circuit of dual band receiver MAS6181 for JJY 60 kHz and 40 kHz frequencies 5 (15) DA6181B.002 5 May, 2011 TYPICAL APPLICATION (Continued) X2 X3 Cext~0.75pF X1 VDD L1 C3 C1 C2 RFIP QO2 QO1 AON QI VDD AGC Amplifier Demodulator & Comparator OUT Receiver Output RFIM Ferrite Antenna 3rd Antenna Frequency Selection RFI2 Power Supply/Biasing VDD VSS PDN1 PDN2 AGC DEC CDEC 47 nF CAGC 10 µF VDD Power Down / VDD Fast Startup / Frequency Selection VDD Figure 3. Application circuit of MAS6181 in tri band receiver configuration 6 (15) DA6181B.002 5 May, 2011 TYPICAL APPLICATION (Continued) Note 1: Crystals The crystals as well as ferrite antenna frequencies are chosen according to the time signal system (Table 2). The reason why the crystal frequency is about 3 Hz higher than the signal frequency is that the crystal is operated without the loading capacitor. Without loading capacitor the actual resonance frequency is about 3 Hz lower than with load thus 77.503 kHz crystal resonates at 77.500 kHz when no loading capacitor is used. Table 2. Time Signal System Frequencies Time Signal System Location Antenna Frequency Recommended Crystal Frequency DCF77 HBG MSF WWVB JJY BPC 77.5 kHz 75 kHz 60 kHz 60 kHz 40 kHz and 60 kHz 68.5 kHz 77.503 Hz 75.003 kHz 60.003 kHz 60.003 kHz 40.003 kHz and 60.003 kHz 68.505 kHz Germany Switzerland United Kingdom USA Japan China The parasitic shunt capacitance C0 of the two crystals should be as similar to each other as possible since they are used to cancel each other. Large shunt capacitance mismatch between the two crystals can lead to nonideal filter characteristics and wide noise band-width. Effectively this means lower sensitivity performance. It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of floating crystal shunt capacitance. For example crystal with 1pF floating package shunt capacitance can have 0.85pF grounded package shunt capacitance. PCB traces of crystal and external compensation capacitance should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance mismatching. When using MAS6181B1 it does not matter which of the two frequency crystals is connected to QO1 pin and which to QO2 pin. Table 3 below presents some crystal suppliers having suitable crystals for time signal receiver application. Table 3. Crystal Suppliers and Crystal Types in Alphabetical Order for Time Signal Receiver Application Supplier Crystal Type Dimensions Web Link Citizen Epson Toyocom KDS Daishinku Microcrystal Seiko Instruments CFV-206 C-2-Type C-4-Type DT-261 MS3V-T1R VTC-120 ø 2.0 x 6.0 ø 1.5 x 5.0 ø 2.0 x 6.0 ø 2.0 x 6.0 1.45 x 1.45 x 6.7 ø 1.2 x 4.7 http://www.citizen.co.jp/tokuhan/quartz/ http://www.epsontoyocom.co.jp/english/ http://www.kds.info/index_en.htm http://www.microcrystal.com/ http://www.sii-crystal.com Note 2: AGC Capacitor The 10µF AGC and 47nF DEC capacitors must have low leakage currents due to very small signal currents through the capacitors. The insulation resistance of these capacitors should be at minimum several 100 MΩ. Also probes with at least several 100 MΩ impedance should be used for voltage probing of the AGC and DEC pins to not disturb their operation. Tantalum capacitors have lower leakage than the electrolyte capacitors. In case of using electrolyte type AGC capacitor the capacitor voltage rating should be at least 25 V for sufficiently low leakage. The DEC capacitor can be low leakage chip capacitor since its capacitance value is small. It is recommended to connect both AGC and DEC capacitors to VDD (see application figures 1 and 2) although VSS connection is also possible. The VDD connection provides better supply noise immunity because the signals and AGC gain are referenced to VDD. Additionally leakage currents are minimized in this connection because in power down the AGC pin voltage is pulled to VDD (to minimum AGC gain) providing zero voltage over the AGC capacitor. 7 (15) DA6181B.002 5 May, 2011 TYPICAL APPLICATION (Continued) Note 3: Power Down / Fast Startup Control Both power down and fast startup is controlled using the PDN pin. The device is in power down (turned off) if PDN1 = PDN2 = VDD and in power up with other three PDN1 and PDN2 control bit combinations (see table 1 on page 4). Fast startup is triggered automatically when moving from power down to power up. The VDD must have been high before moving from power down to power up to guarantee proper operation of fast startup circuitry. Additionally the device should have been kept in power down state at least 50ms before power up. This guarantees that the AGC capacitor voltage has been completely pulled to VDD during power down. The startup time without proper fast startup control can be several minutes. With fast startup it is shortened typically to a few seconds. Note 4: Optional Control for AGC On/Hold AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected. Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive of analog clock or watch can produce disturbing amount of noise which can shift the input amplifier gain to non optimal level. This can be avoided by controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC (AON=VDD) when motors are not driven. The AGC should be in hold only during disturbances and kept on other time released since due to leakage the AGC can still change slowly when in hold. Note 5: Ferrite Antenna The ferrite antenna converts the transmitted radio wave into a voltage signal. It has an important role in determining receiver performance. Recommended antenna impedance at resonance is around 100 kΩ. Low antenna impedance corresponds to low noise but often also to small signal amplitude. On the other hand high antenna impedance corresponds to high noise but also large signal. The optimum performance where signal-to-noise ratio is at maximum is achieved in between. The antenna should have also some selectivity for rejecting near signal band disturbances. This is determined by the antenna quality factor which should be approximately 100. Much higher quality factor antennas suffer from extensive tuning accuracy requirements and possible tuning drifts by the temperature. Antenna impedance Rant can be calculated using equation 1 where fres, L, Qant and C are resonance frequency fres, coil inductance, antenna quality factor and antenna tuning capacitor respectively. Antenna quality factor Qant is defined by ratio of resonance frequency fres and antenna bandwidth B (equation 2). Rant = 2π ⋅ f res ⋅ L ⋅ Qant = Qant = Qant 1 = 2π ⋅ f res ⋅ C 2π ⋅ B ⋅ C f res B Equation 1. Equation 2. Table 4 below presents some antenna suppliers for time signal application. Table 4. Antenna Suppliers and Antenna Types in for Time Signal Application Supplier Antenna Type Dimensions Web Link Micro Analog Systems Oy HR Electronic GmbH Hitachi Metals Premo Sumida A10X60-77.5K222PY A10X100-77.5K222PY A3.5X4X15-7.87MH A2X3X21-0.92MH A3.75X3.75X23.6-0.92MH 60716 (60 kHz) 60708 (77.5 kHz) AN-T702Sxx AN-T702Mxx AN-T702Lxx RCA-SMD-77A (77.5 kHz) RCA-SMD-60A (60 kHz) ACL80A (40 kHz) ø 10 x 60 mm ø 10 x 100 mm 3.5 x 4 x 15 mm 2 x 3 x 21 mm 3.75x3.75x23 mm ø 10 x 60 mm http://www.masoy.com/en/products/radio-controlledclock-rcc/antennas/ http://www.hrelectronic.com/ 19 x 5.5 x 6.3 mm 28 x 5 x 5 mm 50 x 5 x 5 mm 75 x 15 x 6.3 mm http://www.hitachimetals.co.jp/e/prod/prod06/p06_12.html http://www.grupopremo.com/ ø 10 x 80 mm www.sumida.co.jp/jeita/XJA021.pdf 8 (15) DA6181B.002 5 May, 2011 TYPICAL APPLICATION (Continued) Note 6: Time Signal Software’s Pulse Width Recognition Limits The typical output pulse width specifications are presented in the electrical characteristics section on page 3. Due to process variations the typical output pulse width can differ from these. Additionally the output pulse widths can vary even more depending on the receiving antenna signal strength versus noise and disturbance conditions. That is why it is important that the time signal decoding software has appropriate tolerance limits for managing the output pulse width variations successfully. The table 5 presents recommended software pulse width tolerance limits for recognizing pulses of different time signals. Table 5. Recommended Software Pulse Width Recognition Limits for Different Time Signals Parameter DCF77 Output Pulses MSF Output Pulses WWVB Output Pulses JJY60 Output Pulses JJY40 Output Pulses Symbol Min Max Unit T 100ms T 200ms T 100ms T 200ms T 300ms T 500ms T 200ms T 500ms T 800ms T 200ms T 500ms T 800ms T 200ms T 500ms T 800ms 40 140 50 170 280 400 100 400 700 100 400 700 100 400 700 130 250 160 270 380 600 300 600 900 300 600 900 300 600 900 ms ms ms ms ms 9 (15) DA6181B.002 5 May, 2011 MAS6181 SAMPLES IN PDIP-20 PACKAGE 1 20 VSS 19 RFI2 18 RFIM VDD 2 QO2 3 6 QI 7 AGC 8 MAS6181ZZ YYWW XXXXX.X QO1 4 5 PDN2 9 17 RFIP 16 15 14 PDN1 13 AON 12 DEC 11 OUT 10 Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number ZZ = Sample Version PIN DESCRIPTION Pin Name VDD QO2 QO1 QI AGC PDN2 OUT DEC AON PDN1 RFIP RFIM RFI2 VSS Pin Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC P AO AO NC NC AI AO DI DO NC AO DI DI NC NC AI AI AI G Function Note Positive Power Supply Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 1 1 Quartz Filter Input for Crystal AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output 2 3 Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 4 2 Positive Receiver Input Negative Receiver Input Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground 5 5 A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected Notes: 1) Pins 5 and 6 between QO1 and QI must be connected to VSS to eliminate DIL package lead frame parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power on 3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - The output is a current source/sink with |IOUT| > 5 µA - At power down the output is pulled to VSS (pull down switch) 4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation) - Unused AON pad can be left unconnected due to internal pull-up with current < 1 µA. Pull up current is switched off at power down. 5) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD 10 (15) DA6181B.002 5 May, 2011 PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE VSS RFI2 RFIM RFIP VDD QO2 QO1 6181Bz YYWW QI AGC PDN2 OUT PDN1 AON DEC Top Marking Definitions: z = Version Number YYWW = Year Week PIN DESCRIPTION Pin Name Pin Type VDD QO2 QO1 1 2 3 4 5 P AO AO NC AI 6 7 8 9 10 11 12 13 14 15 16 AO DI DO AO DI DI NC AI AI AI G QI AGC PDN2 OUT DEC AON PDN1 RFIP RFIM RFI2 VSS Function Note Positive Power Supply Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 1 Quartz Filter Input for Crystal and External Compensation Capacitor AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 Positive Receiver Input Negative Receiver Input Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground 2 3 4 2 5 5 A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected Notes: 1) Pin 4 between QO1 and QI must be connected to VSS to eliminate TSSOP package lead frame parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power on 3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - The output is a current source/sink with |IOUT| > 5 µA - At power down the output is pulled to VSS (pull down switch) 4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation) - Unused AON pad can be left unconnected due to internal pull-up with current < 1 µA. Pull up current is switched off at power down. 5) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD 11 (15) DA6181B.002 5 May, 2011 PACKAGE (TSSOP-16) OUTLINES C E D Seating Plane B F G H A O Pin 1 B Detail A B L I I1 K P Section B-B J1 M J Dimension N Min A B C D E F G H I I1 J J1 K L M (The length of a terminal for soldering to a substrate) N O P Detail A Max 6.40 BSC 4.30 4.50 5.00 BSC 0.05 0.15 1.10 0.30 0.19 0.65 BSC 0.18 0.09 0.09 0.19 0.19 0° 0.24 0.50 0.28 0.20 0.16 0.30 0.25 8° 0.26 0.75 1.00 REF 12° 12° Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm Dimensions do not include mold flash, protrusions, or gate burrs. All dimensions are in accordance with JEDEC standard MO-153. 12 (15) DA6181B.002 5 May, 2011 SOLDERING INFORMATION ◆ For Pb-Free, RoHS Compliant TSSOP-16 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Matte Tin Seating Plane Co-planarity Lead Finish EMBOSSED TAPE SPECIFICATIONS Tape Feed Direction P0 D0 P2 A E1 F1 W D1 A A0 P Tape Feed Direction T Section A - A B0 S1 K0 Pin 1 Designator Dimension Min Max Unit A0 B0 D0 D1 E1 F1 K0 P P0 P2 S1 T W 6.50 5.20 6.70 5.40 mm mm mm mm mm mm mm mm mm mm mm mm mm 1.50 +0.10 / -0.00 1.50 1.65 7.20 1.20 11.90 1.85 7.30 1.40 12.10 4.0 1.95 0.6 0.25 11.70 2.05 0.35 12.30 13 (15) DA6181B.002 5 May, 2011 REEL SPECIFICATIONS W2 A D C Tape Slot for Tape Start N B W1 2000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Weight Leader Components Min 1.5 12.80 20.2 50 12.4 Max Unit 330 14.4 mm mm mm mm mm mm 18.4 mm 13.50 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape mm mm 1500 g 14 (15) DA6181B.002 5 May, 2011 ORDERING INFORMATION Product Code Product Description MAS6181B1TC00 Dual Band AM-Receiver IC with Differential Input Dual Band AM-Receiver IC with Differential Input EWS-tested wafer, diameter 8”, thickness 395 µm ± 5%. TSSOP-16, Pb-free, RoHS compliant, Tape & Reel MAS6181B1UC06 Contact Micro Analog Systems Oy for other wafer thickness options. ◆ The formation of product code An example for MAS6181B1TC00: MAS6181 B 1 Product Design Capacitance option: name version CC = 0.75 pF TC Package type: TC = 400 µm thick EWS tested wafer 00 Delivery format: 00 = undiced wafer 05 = dies on tray 06 = tape & reel 08 = in tube LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kutomotie 16 FI-00380 Helsinki, FINLAND Tel. Int. +358 10 835 1100 Telefax +358 10 835 1119 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 15 (15)