SY75576L 267MHz 1:4 3.3V HCSL/LVDS Fanout Buffer PrecisionEdge™ General Description Features The SY75576L is a high-speed, fully differential 1:4 clock fanout buffer optimized to provide four identical output copies with 137fs phase jitter and maximum 50ps outputto-output skew. Designed to be used with PCI-Express applications, SY75576L accepts and outputs HCSL or LVDS logic levels. • Four differential pairs of LVDS or HCSL outputs • Two pairs of differential inputs accept LVDS or HCSL logic levels • 267MHz max HCSL frequency • 100MHz max LVDS frequency • Ultra low phase jitter: − 137fsrms, 200MHz (12kHz–20MHz) − 153fsrms, 156.25MHz (12kHz–20MHz) − 212fsrms, 100MHz (12kHz–20MHz) • <2ps Total_Jitterpk-pk, 200MHz (BER = 10−12) • 50ps output-to-output skew • 3.3V ±5% power supply operation • −40°C to +85°C operating temperature • Available in 20-pin TSSOP lead-free package The SY75576L operates from a 3.3V ±5% power supply and is guaranteed over the full industrial temperature range (−40°C to +85°C). It is available in a 20-pin TSSOP lead-free package. The SY75576L is part of Micrel’s high-speed, ultra-low jitter, PrecisionEdge™ product line. Datasheets and support documentation are available on Micrel’s web site at: www.micrel.com. Functional Block Diagram Applications • • • • • Clock distribution PCI-Express Servers Switches Routers Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com July 2, 2013 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY75576LKY TSSOP-20 Industrial 75576L with Pb-Free bar-line indicator Matte-Sn TSSOP-20 Industrial 75576L with Pb-Free bar-line indicator Matte-Sn (2) SY75576LKY TR Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. Pin Configuration 20-Pin TSSOP July 2, 2013 2 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Pin Description Pin Number Pin Name Pin Function 1 SEL 2 VDDIN 3 IN1 HCSL/LVDS input 1 4 /IN1 HCSL/LVDS inverted input 1 5 /PD PD = 0 powers down the chip and tri-states outputs. The pin is attached to an internal pull-up resistor. 6 IN2 HCSL/LVDS input 2 7 /IN2 HCSL/LVDS inverted input 2 8 OE Tri-state outputs. High = enable outputs. Low = disable outputs. Internal pull-up resistor, outputs are enabled by default. 9 GND Ground 10 IREF External resistor Rref between pin IREF and GND controls reference current 11 /CLKD Inverted output D 12 CLKD Non-inverted output D 13 /CLKC Inverted output C 14 CLKC Non-inverted output C 15 VDD 3.3V power supply 16 GND Ground 17 /CLKB Inverted output B 18 CLKB Non-inverted output B 19 /CLKA Inverted output A 20 CLKA Non-inverted output A SEL = 0 propagates IN2, /IN2 to outputs. SEL = 1 propagates IN1, /IN1 to outputs. Internal pullup resistor, IN1, /IN1 is selected by default. 3.3V power supply Clock Input Function Table SEL Input Pair 0 IN2 / IN2 1 IN1 / IN1 July 2, 2013 3 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Absolute Maximum Ratings(3) Operating Ratings(4) Supply Voltage (VDD, VDDIN) ........................................... 5.5V Input Voltage (VIN) .............................. –0.5V to VDDIN + 0.5V Lead Temperature (soldering, 20s) ............................ 260°C Maximum Junction Temperature................................ 125°C Storage Temperature (Ts) ......................... –65°C to +150°C ESD Protection (input) ....................................... 2000V min. Supply Voltage (VDD, VDDIN) ...................... 3.135V to 3.465V Ambient Op Temperature (TA) .................... −40°C to +85°C (5) Package Thermal Resistance TSSOP Still-air (θJA) ................................................. 93°C/W Junction-to-Case (θJC) ................................. 20°C/W DC Electrical Characteristics(6) VDD = VDDIN = 3.135V to 3.465V, TA = −40°C to +85°C, unless otherwise stated. Rref = 475Ω Symbol Parameter VDD, VDDIN Power Supply Voltage Range CIN Min. Typ. Max. Units 3.135 3.3 3.465 V Input Capacitance 7 pF Cout Output Capacitance 6 pF LPin Pin Inductance 5 nH Rout Output Resistance Rpull up Pull up Resistance SEL, /PD, OE VIH Input High Voltage SEL, /PD, OE 2 VDDIN + 0.3 V VIL Input Low Voltage SEL, /PD, OE −0.3 0.8 V VIH Input High Voltage HCSL, IN, /IN 660 750 850 V VIL Input Low Voltage HCSL, IN, /IN −150 0 VIN Differential Input Voltage Range LVDS, IN, /IN 250 350 550 mV Vinput offset Input Common Mode Voltage LVDS, IN, /IN, 1.125 1.25 1.375 V VOH Output High Voltage HSCL 660 750 850 mV Output Low Voltage HSCL −150 0 27 mV Crossing Point Voltage Absolute 250 350 550 mV Variation of Crossing Point Voltage Variation over all edges 140 mV 90 mA No load, /PD = Low 0.4 mA OE = Logic Low 20 mA 5 µA VOL Vcross (7, 8) Vcross_variation IDD IIL (10) (7, 8, 9) Power Supply Current For VDD + VDDIN Input Leakage Current Condition 3 110 50Ω, 2pF 0 < VIN < VDDIN kΩ kΩ 75 −5 V Notes: 3. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings. 5. Package thermal resistance assumes that the exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA values are determined for a 4-layer board in still-air unless otherwise stated. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 7. Test setup is RL = 50Ω with 2pF, Rr = 475Ω ±1%. 8. Measurement taken from Q and /Q. 9. Measured at the crossing point where instantaneous voltages of CLK and /CLK are equal. 10. Inputs with pull-up/pull-down resistances are not included. July 2, 2013 4 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L AC Electrical Characteristics(6) VDD = VDDIN = 3.135V to 3.465V, TA = −40°C to +85°C, unless otherwise stated. Symbol Parameter fMAX Maximum Frequency tPD Propagation Delay Note 11 tSkew Output-to-Output skew Notes 12, 13 tR, tF Output Rise/Fall Times 0.175V to 0.525V / 0.525V to 0.175V At full output swing. 50Ω, 2pF tR/F_var Rise/Fall Time Variation At full output swing. 50Ω, 2pF TRJ_Jitter Phase Jitter Condition Min. Typ. Max. Units HCSL Termination 267 MHz LVDS Termination 100 MHz 2 175 338 ns 50 ps 700 ps 125 ps At 200MHz 137 fsrms At 156.25MHz 153 fsrms At 100MHz 212 fsrms -12 TTJ_Jitter Total Jitter BER = 10 , TDJ = 0, at 200MHz 2 ps TOE_enable Output Enable Time All Outputs 2 µs TOE_disable Output Disable Time All Outputs 10 ns TDCY Duty Cycle 45 50 55 % Notes: 11. Measured from the differential input crossing point to the differential output crossing point. 12. Output-to-Output skew is the difference in time between outputs, receiving data from the same input, for the same temperature, voltage, and transition. 13. This parameter is defined in accordance with JEDEC Standard 65. Jitter Analysis Where Tj is total jitter, Rj is random jitter, and Dj is deterministic jitter. If routing clock signals, the deterministic jitter is usually negligible and the Tj is dominated by the random jitter. Calculating Tj from Rj using Equation 1 gives the values in Table 1. Jitter is defined as the deviation of a signal from its ideal position. Phase noise is the presence of signal energy at frequencies other than the carrier. Random jitter has a Gaussian distribution and is specified as an rms unit, which is one standard deviation of the distribution. Since Gaussian distribution is unbounded in an infinite sample, no communication system can be completely error free. Instead, communication links are rated with a maximum bit -12 error rate (BER), which is typically around 10 for highspeed communication equipment. Achieving a desired BER requires accounting for a number of standard deviations of random noise by using the appropriate value for N (see Table 1) in the formula in Equation 1. Tj = N × Rj + Dj July 2, 2013 Table 1. Standard Deviations of Random Noise BER N Rj at 200MHz Tj at 200MHz 12.723 137fs_rms 1.743ps 10 -11 13.412 137fs_rms 1.837ps 10 -12 14.069 137fs_rms 1.927ps 10 -13 14.698 137fs_rms 2.013ps 10 -10 Eq. 1 5 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Phase Noise Plots Phase jitter = 137fsrms, 200MHz carrier frequency; integration range: 12kHz–20MHz July 2, 2013 6 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Phase jitter = 153fsrms, 156.25MHz carrier frequency; integration range: 12kHz–20MHz July 2, 2013 7 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Phase jitter = 212fsrms, 100MHz carrier frequency; integration range: 12kHz–20MHz July 2, 2013 8 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Functional Characteristics HCSL Waveform Diagram HCSL Interface Application Rs = 33Ω PCI-Express Device Routing Rt = 50Ω July 2, 2013 9 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L LVDS Waveform Diagram LVDS Interface Application R1 = 33Ω R2 = 175Ω R3 = 140Ω R4 = 100Ω July 2, 2013 10 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SY75576L Package Information(14) 20-Pin TSSOP Note: 14. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2013 Micrel, Incorporated. July 2, 2013 11 Revision 1.0 [email protected] or (408) 955-1690