MP1492 2A, 4.2V-16V Input, Fast Transient Synchronous Step-down Converter The Future of Analog IC Technology DESCRIPTION FEATURES • • • The MP1492 is a fully integrated, high– efficiency 2A synchronous rectified step-down converter. The MP1492 operates at high efficiency over a wide output current load range. Adaptive Constant-On-Time (COT) control mode provides fast transient response, eases loop stabilization, and operates with a low-cost electrolytic capacitor. • • • • The MP1492 requires a minimum number of readily available standard external components and is available in an 8-pin SOIC ROHS compliant package. • Wide 4.2V to 16V Operating Input Range 2A Output Current Adaptive COT for Fast Transient Response Low RDS (ON) Internal Power MOSFETs Proprietary Switching Loss Reduction Technique Programmable Switching Frequency OCP, SCP, OVP, UVP Protection and Thermal Shutdown Output Adjustable from 0.805V to 13V APPLICATIONS • • • Digital Set Top Boxes Flat Panel Television and Monitors Distributed Power Systems All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VIN 1 R7 453k ON/OFF BST MP1492 8 499k IN 5 6 SW 4 3 VOUT 2.5V FREQ R1 41k BYP FB EN 7 R2 20k GND 2 MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 1 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER ORDERING INFORMATION Part Number MP1492DS* MP1492DS-A** OCP Protection Latch-off Mode Hiccup Mode Package Top Marking Free Air Temperature (TA) SOIC8 MP1492 MP1492-A -40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP1492DS–Z). For RoHS Compliant Packaging, add suffix –LF (e.g. MP1492DS–LF–Z) ** For Tape & Reel, add suffix –Z (e.g. MP1492DS-A–Z). For RoHS Compliant Packaging, add suffix –LF (e.g. MP1492DS-A–LF–Z) PACKAGE REFERENCE SOIC8 ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply Voltage VIN ....................................... 19V VSW ........................................-0.3V to VIN + 0.3V VBST ...................................................... VSW + 6V All Other Pins ..................................-0.3V to +6V Continuous Power Dissipation (TA = +25°C) (2) SOIC8 ..................................................... 1.39W Junction Temperature ..............................150°C Lead Temperature ....................................260°C Storage Temperature............... -65°C to +150°C SOIC8..................................... 90 ...... 45... °C/W Recommended Operating Conditions (3) Supply Voltage VIN ...........................4.2V to 16V Output Voltage VOUT .....................0.805V to 13V Operating Junction Temp. (TJ). -40°C to +125°C MP1492 Rev. 1.1 3/13/2012 (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 2 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameters Symbol Supply Current (Shutdown) IIN Supply Current (Quiescent, Not IIN Switching) HS Switch On Resistance HSRDS-ON LS Switch On Resistance LSRDS-ON Switch Leakage SWLKG Current Limit (5) ILIMIT One-Shot On Time Minimum Off Time Fold-back Off Time OCP hold-off time Feedback Voltage Feedback Current Soft Start Time EN Rising Threshold EN Threshold Hysteresis TON TOFF TFB TOC VFB IFB TSS VILEN VILEN EN Input Current IEN VIN Under Voltage Lockout INUVVth Threshold Rising VIN Under Voltage Lockout INUVHYS Threshold Hysteresis Thermal Shutdown Thermal Shutdown Hysteresis Condition VEN=0V Min VEN=2V, VFB=0.9V VEN=0V [VSW=0V or 12V] After Soft-Start Time-out R7=300kΩ,VOUT=1.2V Max 789 VFB=800mV 1.05 Units μA 1 mA 120 70 0 mΩ mΩ μA 10 3.0 ILIM=1 ILIM=1 VEN=2V VEN=0V Typ 5 A 250 130 1.25 50 805 10 1 1.35 500 2 0 150 821 50 1.6 ns ns μs μs mV nA ms V mV μA 3.1 V 300 mV 150 25 °C °C Note: 5) Guaranteed by design and characterization.. MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 3 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER PIN FUNCTIONS SOIC8 Pin # Name 1 IN 2 GND 3 SW 4 BST 5 BYP 6 EN 7 FB 8 FREQ MP1492 Rev. 1.1 3/13/2012 Description Supply Voltage. The MP1492 operates from a +4.2V to +16V input rail. C1 is needed to decouple the input rail. Use wide PCB traces and multiple vias to make the connection. System Ground. This pin is the reference ground of the regulated output voltage. For this reason care must be taken in PCB layout. Switch Output. Use wide PCB traces and multiple vias to make the connection. Bootstrap. A capacitor connected between SW and BST pins is required to form a floating supply across the high-side switch driver. Internal LDO output. Decouple with a 1µF ceramic capacitor. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. EN=1 to enable the MP1492. For automatic start-up, connect EN pin to VIN with a pull-up resistor. Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets the output voltage. Frequency. Setting Pin. Sets the full-load switching frequency driving CCM operation.. Connect a resistor R7 to IN to set the switching frequency. An optional 1nF decoupling capacitor can be added to improve any switching frequency jitter that may be present. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 4 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN=12V, VOUT=1.2V, L=2.2µH, TA=+25°C, unless otherwise noted. Line Regulation Load Regulation IOUT=2A 100 VIN=8V 95 0.2 1.00 0.1 0.80 0.60 0 90 85 0.40 -0.1 VIN=12V 80 -0.2 0.00 75 -0.3 -0.20 70 -0.4 65 -0.5 60 0.01 -0.6 0.1 1 2 -0.40 -0.60 -0.80 -1.00 0 IOUT (A) 5 10 1516 450 15 10 440 1.22 435 1.2 430 VOUT(V) FSW (kHZ) 20 425 420 415 5 IOUT (A) MP1492 Rev. 1.1 3/13/2012 2 400 -40 -20 VIN=12V VIN=16V 1.18 VIN=8V VIN=5V 1.16 1.12 405 No air flow 1.5 2 1.14 410 1 1.5 VOUT VS. IOUT 1.24 445 0.5 1 VOUT=1.2V, Freq=500kHz VIN=12V, VOUT=5V 0 0.5 IOUT (A) Frequency vs. Temperature 25 0 0 VIN (V) Case Temprature Rise vs. Load Current 30 VIN=12V 0.20 0 20 40 60 80 100 120140 1.1 0.01 0.1 1 10 IOUT(A) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 5 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, VOUT=1.2V, L=2.2µH, TA=+25°C, unless otherwise noted. Input/Output Voltage Ripple Input/Output Voltage Ripple Input/Output Voltage Ripple IOUT = 0A IOUT = 0.3A IOUT = 2A VOUT/AC 50mV/div. VOUT/AC 20mV/div. VOUT/AC 10mV/div. VIN/AC 50mV/div. VIN/AC 20mV/div. VIN/AC 100mV/div. VSW 10V/div. VSW 10V/div. VSW 10V/div. IL 1A/div. IL 2A/div. IL 2A/div. Start Up Through VIN Start Up Through VIN Shut Down Through VIN IOUT = 0A IOUT = 2A IOUT = 0A VOUT 500mV/div. VIN 10V/div. VOUT 500mV/div. VIN 10V/div. VOUT 500mV/div. VIN 10V/div. VSW 10V/div. VSW 10V/div. VSW 10V/div. IL 1A/div. IL 2A/div. IL 2A/div. Shut Down Through VIN Start Up Through EN Start Up Through EN IOUT =2A IOUT =0A IOUT = 2A VOUT 500mV/div. VIN 5V/div. VOUT 500mV/div. VEN 10V/div. VOUT 500mV/div. VEN 10V/div. VSW 10V/div. VSW 10V/div. VSW 10V/div. IL 2A/div. IL 1A/div. IL 2A/div. MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 6 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, VOUT=1.2V, L=2.2µH, TA=+25°C, unless otherwise noted. Shut Down Through EN Shut Down Through EN IOUT = 0A IOUT = 2A VOUT 500mV/div. VEN 10V/div. VOUT 500mV/div. VEN 10V/div. VSW 10V/div. VSW 10V/div. IL 2A/div. IL 2A/div. MP1492 Rev. 1.1 3/13/2012 VOUT/AC 20mV/div. VSW 10V/div. IL 2A/div. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 7 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER BLOCK DIAGRAM Figure 1—Function Block Diagram MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 8 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER OPERATION PWM Operation The MP1492 is a fully integrated synchronous rectified step-down switch converter. Adaptive constant-on-time (COT) control is employed to provide fast transient response and easy loop stabilization. At the beginning of each cycle, the high-side MOSFET (HS-FET) is turned ON when the feedback voltage (FB) is below the reference voltage (REF) which indicates insufficient output voltage. The ON period is determined by the input voltage and the frequency-set resistor as follows: 9.3 × R7 (kΩ) (1) TON (ns) = + 40ns VIN (V) − 0.4 After the ON period elapses, the HS-FET is turned off. It is turned ON again when FB drops below REF. By repeating operation in this way, the converter regulates the output voltage. The integrated low-side MOSFET (LS-FET) is turned on when the HS-FET is in its OFF state to minimize the conduction loss. There will be a dead short between input and GND if both HSFET and LS-FET are turned on at the same time. It’s called shoot-through. In order to avoid shootthrough, a dead-time (DT) is internally generated between HS-FET off and LS-FET on. When the output current is high, the HS-FET and LS-FET repeat on/off as described above. In this operation, the inductor current will never go to zero. It’s called continuous-conduction-mode (CCM) operation. In CCM operation, the switching frequency (Fs) is fairly constant. Light-Load Operation When the load current decreases, MP1492 reduces the switching frequency automatically to maintain high efficiency. As the output current reduces from heavy-load condition, the inductor current decreases as well, and eventually comes close to zero current. The LS-FET driver turns into tri-state (high Z) whenever the inductor current reaches zero level. The current modulator takes over the control of LS-FET and limits the inductor current to less than -1mA. Hence, efficiency at light-load condition is optimized. MP1492 Rev. 1.1 3/13/2012 Figure 2 Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is charged from VCC through N1 (Figure 3). N1 turns on when LS switches turns on and turns off when LS switch turns off. Switching Frequency Adaptive constant-on-time (COT) control is used in MP1492 and there is no dedicated oscillator in the IC. The input voltage is feed-forwarded to the on-time one-shot timer through the resistor R7. The duty ratio is kept as VOUT/VIN. Hence the switching frequency is fairly constant over the input voltage range. The switching frequency can be set as follows: FS (kHz) = 106 (2) 9.3 × R7 (kΩ ) VIN (V) × + TDELAY (ns) VIN (V) − 0.4 VOUT (V) Where TDELAY is the comparator delay, it’s about 40ns. MP1492 is optimized to operate at high switching frequency but with high efficiency. High switching frequency makes it possible to utilize small sized LC filter components to save system PCB space. Jitter and FB Ramp Slope Figure 3 and Figure 4 show jitter occurring in both PWM mode and skip mode. When there is noise in the VFB downward slope, the ON time of www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 9 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER HS-FET deviates from its intended location and produces jitter. It is necessary to understand that there is a relationship between a system’s stability and the steepness of the VFB ripple’s downward slope. The slope steepness of the VFB ripple dominates in noise immunity. The magnitude of the VFB ripple doesn’t directly affect the noise immunity directly. To realize the stability when no external ramp is used, usually the ESR value should be chosen as follow: RESR TSW T + ON 2 ≥ 0.7 × π COUT (3) TSW is the switching period. Ramp with small ESR Cap When the output capacitors are ceramic ones, the ESR ripple is not high enough to stabilize the system, and external ramp compensation is needed. Skip to application information section for design steps with small ESR caps. Figure 3—Jitter in PWM Mode L SW R4 Vo C4 IR4 IC4 R9 R1 IFB Ceramic FB Figure 4—Jitter in Skip Mode Ramp with Large ESR Cap In the case of POSCAP or other types of capacitor with larger ESR is applied as output capacitor. The ESR ripple dominates the output ripple, and the slope on the FB is quite ESR related. Figure 5 shows an equivalent circuit in PWM mode with the HS-FET off and without an external ramp circuit. Turn to application information section for design steps with large ESR caps. R2 Figure 6—Simplified Circuit in PWM Mode with External Ramp Compensation In PWM mode, an equivalent circuit with HS-FET off and the use of an external ramp compensation circuit (R4, C4) is simplified in Figure 6. The external ramp is derived from the inductor ripple current. If one chooses C4, R9, R1 and R2 to meet the following condition: ⎞ 1 1 ⎛ R × R2 < ×⎜ 1 + R9 ⎟ 2π × FSW × C4 5 ⎝ R1 + R 2 ⎠ (4) Where: SW Vo L FB R1 ESR POSCAP R2 Figure 5—Simplified Circuit in PWM Mode without External Ramp Compensation MP1492 Rev. 1.1 3/13/2012 IR4 = IC4 + IFB ≈ IC4 (5) And the ramp on the VFB can then be estimated as: VRAMP = VIN − VO R1 // R2 × TON × R 4 × C4 R1 // R2 + R9 (6) The downward slope of the VFB ripple then follows www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 10 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER VSLOPE1 = − VOUT − VRAMP = Toff R 4 × C4 (7) As can be seen from equation 7, if there is instability in PWM mode, we can reduce either R4 or C4. If C4 can not be reduced further due to limitation from equation 4, then we can only reduce R4. For a stable PWM operation, the Vslope1 should be design follow equation 8. TSW T + ON -RESRCOUT Io × 10-3 -Vslope1 ≥ 0.7 × π 2 VOUT + 2 × L × COUT TSW -Ton (8) Io is the load current. In skip mode, the downward slope of the VFB ripple is almost the same whether the external ramp is used or not. Figure 7 shows the simplified circuit of the skip mode when both the HS-FET and LS-FET are off. smoothly ramps up with the SS voltage. Once SS voltage reaches the same level of the REF voltage, it keeps ramping up, while REF takes over the PWM comparator. At this point, the soft start finishes, it enters steady state operation. The SS time is about 1ms. When the EN pin becomes low, the internal SS voltage is discharged through an internal current source. Once the SS voltage reaches REF voltage, it takes over the PWM comparator. The output voltage will decrease smoothly with SS voltage until zero level. Over-Current Protection (OCP) and ShortCircuit Protection (SCP) MP1492 has cycle-by-cycle over-current limiting control. The inductor current is monitored during the ON state. And it has two optional OCP/SCP protection modes: latch-off mode and hiccup mode. For MP1492DS, once it detects that the inductor current is higher than the current limit, the HSFET is turned off. At the same time, the OCP timer is started. The OCP timer is set as 50μs. If in the following 50μs, the current limit is hit for every cycle, then it’ll trigger OCP. The converter needs power cycle to restart after it triggers OCP. Figure 7—Simplified Circuit in skip Mode The downward slope of the VFB ripple in skip mode can be determined as follow: VSLOPE2 = − VREF ((R1 + R2 ) // Ro) × COUT (9) Where Ro is the equivalent load resistor. As described in Figure 4, VSLOPE2 in the skip mode is lower than that is in the PWM mode, so it is reasonable that the jitter in the skip mode is larger. If one wants a system with less jitter during ultra light load condition, the values of the VFB resistors should not be too big, however, that will decrease the ultra light load efficiency. Soft Start/Stop MP1492 employs soft start/stop (SS) mechanism to ensure smooth output during power up and power shut-down. When the EN pin becomes high, an internal SS voltage ramps up slowly. The SS voltage takes over the REF voltage to the PWM comparator. The output voltage MP1492 Rev. 1.1 3/13/2012 When the current limit is hit and the FB voltage is lower than 50% of the REF voltage, MP1492DS considers this as a dead short on the output. It’ll trigger OCP immediately. This is short-circuit protection (SCP). For MP1492DS-A, enters hiccup mode that periodically restarts the part when the inductor current peak value exceeds the current limit and VFB drops below the under-ltage (UV) threshold. Typically, the UV threshold is 50% below the REF voltage, In OCP/SCP, MP1492DS-A will disable the output voltage power, discharge internal soft-start cap, and then automatically try to soft –start again. If the over-current circuit condition still holds after soft-start ends, it repeats this operation cycle until the over-current circuit condition disappears, and output rises back to regulation level. Over/Under-voltage Protection (OVP/UVP) MP1492 monitors the output voltage through a resistor divided feedback (FB) voltage to detect www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 11 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER over and under voltage on the output. When the FB voltage is higher than 125% of the REF voltage, it’ll trigger OVP. Once it triggers OVP, the LS-FET is always on, while the HS-FET is off. It needs power cycle to power up again. When the FB voltage is below 50% of the REF voltage (0.805V), UVP will be triggered. Usually UVP comes with current limit is hit, hence it results in SCP. . UVLO protection MP1492 has under-voltage lock-out protection (UVLO). When the input voltage is higher than the UVLO rising threshold voltage, the MP1492 powers up. It shuts off when the input voltage is lower than the UVLO falling threshold voltage. This is non-latch protection. Thermal Shutdown Thermal shutdown is employed in MP1492. The junction temperature of the IC is monitored internally. If the junction temperature exceeds the threshold value (typically 150ºC), the converter shuts off. This is non-latch protection. There is about 25ºC hysteresis. Once the junction temperature drops around 125ºC, it initiates a SS. MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 12 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER APPLICATION INFORMATION Setting the Output Voltage-Large ESR Caps For applications that electrolytic capacitor or POS capacitor with a controlled output of ESR is set as output capacitors. The output voltage is set by feedback resistors R1 and R2. As figure 8 shows. considerable quiescent current loss while too large R2 makes the FB noise sensitive. It is recommended to choose a value within 5kΩ50kΩ for R2, using a comparatively larger R2 when Vo is low, etc.,1.05V, and a smaller R2 when Vo is high. And the value of R1 then is determined as follow: R2 (11) R= 1 Figure 8—Simplified Circuit of POS Capacitor First, choose a value for R2. R2 should be chosen reasonably, a small R2 will lead to considerable quiescent current loss while too large R2 makes the FB noise sensitive. It is recommended to choose a value within 5kΩ50kΩ for R2, using a comparatively larger R2 when Vo is low,etc.,1.05V, and a smaller R2 when Vo is high. Then R1 is determined as follow with the output ripple considered: 1 VOUT − ΔVOUT − VREF 2 (10) R1 = R2 VREF ΔVOUT is the output ripple determined by equation 19. R2 (VOUT -VFB(AVG) ) R4 +R9 MP1492 Rev. 1.1 3/13/2012 - The VFB(AVG) is the average value on the FB, VFB(AVG) varies with the Vin, Vo, and load condition, etc., its value on the skip mode would be lower than that of the PWM mode, which means the load regulation is strictly related to the VFB(AVG). Also the line regulation is related to the VFB(AVG) ,if one wants to gets a better load or line regulation, a lower Vramp is suggested once it meets equation 8. For PWM operation, VFB(AVG) value can be deduced from equation 12. R1 //R2 1 VFB(AVG) = VREF + VRAMP × 2 R1 //R2 + R9 (12) Usually, R9 is set to 0Ω, and it can also be set following equation 13 for a better noise immunity. It should also set to be 5 timers smaller than R1//R2 to minimize its influence on Vramp. R9 ≤ Figure 9—Simplified Circuit of Ceramic Capacitor Setting the Output Voltage-Small ESR Caps When low ESR ceramic capacitor is used in the output, an external voltage ramp should be added to FB through resistor R4 and capacitor C4.The output voltage is influenced by ramp voltage VRAMP besides R divider. The VRAMP can be calculated as shown in equation 6, R2 should be chosen reasonably, a small R2 will lead to VFB(AVG) 1 2π× C4 × 2FSW (13) Using equation 11 to calculate the output voltage can be complicated. To simplify the calculation of R1 in equation 11, a DC-blocking capacitor Cdc can be added to filter the DC influence from R4 and R9. Figure 10 shows a simplified circuit with external ramp compensation and a DC-blocking capacitor. With this capacitor, R1 can easily be obtained by using equation 14 for PWM mode operation. 1 (VOUT − VREF − VRAMP ) 2 (14) R1 = R2 1 VREF + VRAMP 2 Cdc is suggested to be at least 10 times larger than C4 for better DC blocking performance, and www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 13 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER should also not larger than 0.47μF considering start up performance. In case one wants to use a larger Cdc for a better FB noise immunity, combined with reducing R1 and R2 to limit the Cdc in a reasonable value without affecting the system start up. Be noted that even when the Cdc is applied, the load and line regulation are still Vramp related. The input capacitance value determines the input voltage ripple of the converter. If there is an input voltage ripple requirement in the system design, choose the input capacitor that meets the specification.The input voltage ripple can be estimated as follows: ΔVIN = IOUT V V × OUT × (1 − OUT ) FS × CIN VIN VIN (17) The worst-case condition occurs at VIN = 2VOUT, where: ΔVIN = I 1 × OUT 4 FS × CIN (18) Output Capacitor Figure10—Simplified Circuit of Ceramic Capacitor with DC blocking capacitor Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Ceramic capacitors are recommended for best performance. In the layout, it’s recommended to put the input capacitor as close as possible to the VIN pin. The capacitance varies significantly over temperature. Capacitors with X5R and X7R ceramic dielectrics are recommended because they are fairly stable over temperature. The capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. The input ripple current can be estimated as follows: ICIN = IOUT × VOUT V × (1 − OUT ) VIN VIN (15) The worst-case condition occurs at VIN = 2VOUT, where: ICIN = IOUT 2 (16) For simplification, choose the input capacitor whose RMS current rating is greater than half of the maximum load current. MP1492 Rev. 1.1 3/13/2012 The output capacitor is required to maintain the DC output voltage. Ceramic or POSCAP capacitors are recommended. The output voltage ripple can be estimated as: ΔVOUT = VOUT V 1 × (1 − OUT ) × (RESR + ) (19) FSW × L VIN 8 × FSW × COUT In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT = VOUT V × (1 − OUT ) 8 × FS × L × COUT VIN 2 (20) The output voltage ripple caused by ESR is very small. Therefore, an external ramp is needed to stabilize the system. The external ramp can be generated through resistor R4 and capacitor C4 following equation 4, 7 and 8. In the case of POSCAP or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. The ramp voltage generated from the ESR is high enough to stabilize the system. So the external ramp is not recommended. A minimum ESR value of 12mΩ is required to ensure stable operation of the converter. For simplification, the output ripple can be approximated to: ΔVOUT = VOUT V × (1 − OUT ) × RESR FS × L VIN www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. (21) 14 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER Maximum output capacitor limitation should be also considered in design application. MP1492 has an around 1ms soft-start time period. If the output capacitor value is too high, the output voltage can’t reach the design value during the soft-start time, and then it will fail to regulate. The maximum output capacitor value Co_max can be limited approximately by: CO _ MAX = (ILIM _ AVG − IOUT ) × Tss / VOUT (22) Where, ILIM_AVG is the average start-up current during soft-start period. Tss is the soft-start time. Inductor The inductor is required to supply constant current to the output load while being driven by the switched input voltage. A larger value inductor will result in less ripple current that will result in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule of thumb for determining the inductance to use is to allow the peak-to-peak ripple current in the inductor to be approximately 30~40% of the maximum switch current limit. Also, make sure that the peak inductor current is below the maximum switch current limit. The inductance value can be calculated by: L= VOUT V × (1 − OUT ) FS × ΔIL VIN (23) Where ΔIL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated by: ILP = IOUT + VOUT V × (1 − OUT ) 2FS × L VIN (24) Application Recommendation As Figure 8 shows, when output cap is electrolytic POSCAP, etc with large ESR, no external ramp is needed. Recommended parameters are listed below in Table 1 to Table 3 MP1492 Rev. 1.1 3/13/2012 Table 1—300kHz Recommended Parameters without External Ramp Compensation Recommended Conditions: VIN=12V, IOUT=2A VOUT (V) 1.2 2.5 3.3 L (μH) 3.3 3.3 3.3 R1 (kΩ) 12.1 30 40.2 R2 (kΩ) 26.1 14.3 13.3 R7 (kΩ) 402 820 1000 Table 2—500kHz Recommended Parameters without External Ramp Compensation Recommended Conditions: VIN=12V, IOUT=2A VOUT (V) 1.2 2.5 3.3 L (μH) 3.3 3.3 3.3 R1 (kΩ) 12.1 30 40.2 R2 (kΩ) 26.1 14.3 13.3 R7 (kΩ) 240 510 649 Table 3—700kHz Recommended Parameters without External Ramp Compensation Recommended Conditions: VIN=12V, IOUT=2A VOUT (V) 1.2 2.5 3.3 L (μH) 2.2 2.2 2.2 R1 (kΩ) 12.1 30 40.2 R2 (kΩ) 26.1 14.3 13.3 R7 (kΩ) 174 348 475 When output cap is ceramic caps with lower ESR, external ramp is needed as shown in Fig.9. Recommended parameters are as listed in Table 4 to Table 6 with R9=0Ω. Table 4—300kHz Recommended Parameters with External Ramp Compensation Recommended Conditions: VIN=12V, IOUT=2A VOUT (V) 1.2 2.5 3.3 L (μH) 3.3 3.3 3.3 R1 (kΩ) 12.1 30 40.2 R2 (kΩ) 26.1 14.3 12.7 R4 (kΩ) 330 698 698 C4 (pF) 220 220 220 R7 (kΩ) 402 820 1000 Table 5—500kHz Recommended Parameters with External Ramp Compensation Recommended Conditions: VIN=12V, IOUT=2A VOUT (V) 1.2 2.5 3.3 L (μH) 3.3 3.3 3.3 R1 (kΩ) 12.1 30 40.2 R2 (kΩ) 26.1 14.3 12.7 R4 (kΩ) 402 549 698 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. C4 (pF) 220 220 220 R7 (kΩ) 240 510 649 15 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER Table 7—Recommended Maximum Output Capacitor Value (FS=500 kHz) Recommended Conditions: VIN=12V, IOUT=2A Table 6—700kHz Recommended Parameters with External Ramp Compensation Recommended Conditions: VIN=12V, IOUT=2A VOUT (V) 1.2 2.5 3.3 L (μH) 2.2 2.2 2.2 R1 (kΩ) 12.1 30 40.2 R2 (kΩ) 26.1 14.3 12.7 R4 (kΩ) 330 549 698 C4 (pF) 220 220 220 VOUT (V) CO_MAX (μF) R7 (kΩ) 174 348 475 BST IN 1.8 2.5 3.3 5 680 570 390 330 220 The detailed application schematic is shown in Figure 11, 12 and Figure 13. The typical performance and circuit waveforms have been shown in the Typical Performance Characteristics section. For more possible applications of this device, please refer to related Evaluation Board Data Sheets. According to equation (22) and some design abundance are reserved, recommended maximum output capacitor value is shown in Table 7. 1 1.2 4 MP1492 8 FREQ 5 BYP 6 EN SW 7 GND FB 3 2 Figure 11—Typical Application Schematic with No External Ramp 1 BST IN 4 MP1492 8 FREQ 5 BYP SW 3 R9 0 FB EN 7 GND 6 2 Figure 12—Typical Application Schematic with Low ESR Ceramic Capacitor MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 16 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER 1 BST IN 4 MP1492 8 FREQ 5 BYP FB EN 3 7 Cdc 10nF GND 6 SW 2 Figure 13—Typical Application Schematic with Low ESR Ceramic Capacitor and DC Blocking Capacitor. Layout Recommendation 1) Put the input capacitors as close as possible to the IN pin. 2) Put the decoupling capacitor as close as possible to the VCC pin. 3) Put the inductor as close as possible to SW pin. Make the SW pad as large as possible to minimize the switching noise interference. 4) The FB pin is directly connected to the PWM comparator. It should be routed away from the noisy SW node. MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 17 MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER PACKAGE INFORMATION SOIC8 0.189(4.80) 0.197(5.00) 8 0.050(1.27) 0.024(0.61) 5 0.063(1.60) 0.150(3.80) 0.157(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.213(5.40) 4 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.013(0.33) 0.020(0.51) 0.0075(0.19) 0.0098(0.25) SEE DETAIL "A" 0.050(1.27) BSC SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) DETAIL "A" NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP1492 Rev. 1.1 3/13/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 18