MP1499 High Efficiency 5A Peak, 16V, 500kHz Synchronous Step Down Converter The Future of Analog IC Technology DESCRIPTION FEATURES The MP1499 is a high frequency synchronous rectified step-down switch mode converter with built in internal power MOSFETs. It offers a very compact solution to achieve 5A peak output current over a wide input supply range with excellent load and line regulation. The MP1499 has synchronous mode operation for higher efficiency over output current load range. Current mode operation provides fast transient response and eases loop stabilization. Full protection features include over current protection and thermal shut down. The MP1499 requires a minimum number of readily available standard external components and is available in a space saving 10-pin QFN (2x3mm) package. Wide 4.5V to 16V Operating Input Range 70mΩ/25mΩ Low RDS(ON) Internal Power MOSFETs Proprietary Switching Loss Reduction Technique Fixed 500kHz Switching Frequency Sync from 200kHz to 2MHz External Clock AAM Power Save Mode External Soft Start OCP Protection and Hiccup Thermal Shutdown Output Adjustable from 0.8V Available in a QFN10 (2x3mm) Package APPLICATIONS Digital Set Top Boxes Flat Panel Television and Monitors Distributed Power Systems All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION Efficiency vs. Output Current R5 10 VIN C1 22 9 BST SW EN/SYNC R3 100k 8 MP1499 FB 1 10 SS VCC C5 22nF C4 100nF 4 IN 3 V =3.3V 100 OUT C6 2 NC GND 5 6, 7 R8 33k 95 90 L1 3.3 R1 40.2k VOUT 3.3V/5A 85 80 VIN=12V VIN=5V 75 70 R2 13k C2 47 65 60 VIN=16V 55 50 0.01 0.10 1.00 10.00 OUTPUT CURRENT(A) MP1499 Rev. 1.0 7/26/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 1 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER ORDERING INFORMATION Part Number* MP1499GD Package QFN10 (2x3mm) Top Marking ADH * For Tape & Reel, add suffix –Z (e.g.MP1499GD–Z); PACKAGE REFERENCE TOP VIEW FB 1 10 SS VCC 2 9 IN EN/SYNC 3 8 SW BST 4 7 GND NC 5 6 GND ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance VIN ................................................. –0.3V to 17V VSW ...................................................................... -0.3V (-5V for <10ns) to 17V(19V for <10ns) VBST ........................................................ VSW+6V All Other Pins ............................ –0.3V to 6.5 V(2) (3) Continuous Power Dissipation (TA = +25°C) ........................................................... 1.92W Junction Temperature ...............................150C Lead Temperature ....................................260C Storage Temperature ................. -65C to 150C QFN10 (2x3mm) ..................... 65 ...... 13... C/W Recommended Operating Conditions (4) Supply Voltage VIN ........................... 4.5V to 16V Output Voltage VOUT ................ 0.807V to Vin-3V Operating Junction Temp. (TJ). -40°C to +125°C MP1499 Rev. 1.0 7/26/2012 (5) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) About the details of EN pin’s ABS MAX rating, please refer to page 10, EN/SYNC control section. 3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 2 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, TA = 25C, unless otherwise noted. Parameter Supply Current Supply Current (Shutdown) Supply Current (Quiescent) MOSFET HS Switch On Resistance LS Switch On Resistance Switch Leakage MOSFET Current Limit (6) Oscillator and Timer Oscillator Frequency Maximum Duty Cycle Minimum On Time(6) Sync Frequency Range Reference And Soft Start Symbol IIN Iq ILIMIT fSW DMAX TON MIN fSYNC VFB Feedback Current Soft-Start Current Enable And UVLO EN Rising Threshold EN Falling Threshold IFB ISS EN Turn Off Delay VIN Under Voltage Lockout Threshold-Rising VIN Under Voltage Lockout Threshold-Hysteresis VCC Regulator VCC Regulator VCC Load Regulation Thermal Protection Thermal Shutdown(6) Thermal Hysteresis(6) Min VEN = 0V VEN = 2V, VFB = 1V HSRDS-ON VBST-SW=5V LSRDS-ON VCC=5V SWLKG VEN = 0V, VSW =12V Feedback Voltage EN Input Current Condition 40% Duty Cycle VFB=750mV VFB=700mV Max Units 0.6 1 1 μA mA 1 mΩ mΩ μA 70 25 7 9 430 90 500 95 60 0.2 TA=25°C -40°C <TA<85°C (7) VFB=800mV VEN RISING VEN FALLING IEN Typ 791 787 A 580 2 8 807 807 10 11 823 827 50 14 1.2 1.1 1.4 1.25 1.6 1.4 kHz % ns MHz mV nA μA V V VEN=2V 2 μA VEN=0 0 μA 8 μs ENTd-off INUVVth 3.7 3.9 4.1 V INUVHYS 650 mV VCC 5 3 V % 150 20 ºC ºC ICC=5mA Notes: 6) Guaranteed by design. 7) Not tested in production and guaranteed by over-temperature characterization. MP1499 Rev. 1.0 7/26/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 3 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 3.3µH, TA = 25°C, unless otherwise noted. Disabled Supply Current vs. Input Voltage 900 800 700 600 500 400 300 200 4 6 8 10 12 14 16 INPUT VOLTAGE (V)) 18 V =0V 100 EN 90 80 70 60 50 40 30 20 10 0 0 Load Regulation 5 10 15 INPUT VOLTAGE (V) 20 1.0 475 450 425 400 -40 -20 0.4 VIN=5V IOUT=5A 0.2 0.0 0.0 -0.2 -0.4 VIN=16V IOUT=2.5A -0.6 -0.2 0 20 40 60 80 100 120 13 0.6 -0.1 500 15 CURRENT LIMIT (A) 0.2 VIN=12V 525 Current Limit vs. Duty Cycle VIN=5V-16V 0.8 0.1 550 Line Regulation 0.3 -0.3 Switching Frequency vs. Ambient Temperature SWITCHING FREQUENCY (kHz) VFB=1V 1000 DISABLED SUPPLY CURRENT (nA) Enabled Supply Current vs. Input Voltage 11 9 7 5 -0.8 0 1 2 3 4 OUTPUT CURRENT (A) MP1499 Rev. 1.0 7/26/2012 5 -1.0 5 6 7 8 9 10 11 12 13 14 15 16 3 10 20 30 40 50 60 70 80 INPUT VOLTAGE (V) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 4 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board of the Design Example section. VIN = 12V, VOUT = 3.3V, L = 3.3µH, TA = 25°C, unless otherwise noted. 100 95 VIN=5V 100 100 95 95 90 90 85 85 80 80 VIN=12V 75 70 75 70 VIN=16V 90 85 VIN=12V VIN=5V 75 VIN=16V 70 65 65 60 60 60 55 55 55 50 0.0 50 0.0 65 1.0 2.0 3.0 4.0 5.0 OUTPUT CURRENT (A) 1.0 2.0 3.0 4.0 VIN=12V 80 50 0.0 5.0 OUTPUT CURRENT (A) VIN=5V VIN=16V 1.0 2.0 3.0 4.0 5.0 OUTPUT CURRENT (A) Case Temperature Rise vs. Output Current 100 100 95 95 90 90 85 80 VIN=16V VIN=5V 70 65 65 60 60 55 55 50 0.0 50 0.0 2.0 3.0 4.0 40 VIN=16V 5.0 OUTPUT CURRENT (A) VOUT=3.3V VIN=6.5V 75 70 1.0 50 VIN=12V 85 VIN=12V 80 75 VIN=12V, IOUT=0A-5A, 4 layers PCB, Size: 6.5cmx6.5cm 60 30 20 VOUT=5V 10 1.0 2.0 3.0 4.0 0 5.0 0 VOUT=1.2V 1 2 3 4 5 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Case Temperature Rise vs. Output Current OUTPUT CURRENT (A) 70 60 50 VOUT=3.3V 40 30 20 VOUT=1.2V 10 0 0 1 2 3 4 OUTPUT CURRENT (A) MP1499 Rev. 1.0 7/26/2012 5 6 6 VIN=12V 5 OUTPUT CURRENT (A) 80 VIN=5V, IOUT=0A-5A, 4 layers PCB, Size: 6.5cmx6.5cm 4 3 VIN=5V 2 1 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 VOUT=1.8V 5 4 VOUT=3.3V 3 VOUT=5V 2 1 0 -40-30-20-10 0 10 20 30 40 50 60 70 OUTPUT VOLTAGE (V) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 5 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board of the Design Example section. VIN = 12V, VOUT = 3.3V, L = 3.3µH, TA = 25°C, unless otherwise noted. OUTPUT CURRENT (A) 6 Short Entry Short Recovery IOUT=0A IOUT=0A VOUT=1.8V 5 4 VOUT 2V/div. 3 VIN 10V/div. VOUT=3.3V 2 VOUT 2V/div. VIN 10V/div. VSW 5V/div. 1 0 -40-30-20-10 0 10 20 30 40 50 60 70 VSW 5V/div. IL 10A/div. IL 10A/div. Startup through Enable Startup through Enable Shutdown through Enable IOUT=0A IOUT=5A IOUT=0A VOUT 2V/div. VOUT 2V/div. VOUT 2V/div. VEN 5V/div. VEN 5V/div. VEN 5V/div. VSW 5V/div. VSW 5V/div. VSW 5V/div. Iinductor 1A/div. Iinductor 1A/div. Iinductor 5A/div. Shutdown through Enable IOUT=5A VOUT 2V/div. VEN 5V/div. MP1499 Rev. 1.0 7/26/2012 Startup through Input Voltage IOUT=0A IOUT=5A VOUT 2V/div. VOUT 2V/div. VIN 10V/div. VSW 5V/div. VIN 10V/div. VSW 5V/div. Iinductor 1A/div. Iinductor 5A/div. VSW 5V/div. Iinductor 5A/div. Startup through Input Voltage www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 6 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board of the Design Example section. VIN = 12V, VOUT = 3.3V, L = 3.3µH, TA = 25°C, unless otherwise noted. Shutdown through Input Voltage Shutdown through Input Voltage IOUT=0A IOUT=5A Input / Output Ripple IOUT=5A VOUT AC Coupled 20mV/div. VOUT 2V/div. VOUT 2V/div. VIN 10V/div. VIN 10V/div. VSW 5V/div. VSW 5V/div. Iinductor 1A/div. Iinductor 5A/div. VIN AC Coupled 200mV/div. VSW 10V/div. IL 5A/div. Load Transient Reponse IOUT=2.5A-5A VOUT AC Coupled 100mV/div. IOUT 2A/div. MP1499 Rev. 1.0 7/26/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 7 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER PIN FUNCTIONS Package Pin # Name 1 FB 2 VCC 3 EN/SY NC 4 BST 5 NC 6, 7 GND 8 SW 9 IN 10 SS MP1499 Rev. 1.0 7/26/2012 Description Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets the output voltage. To prevent current limit run away during a short circuit fault condition the frequency fold-back comparator lowers the oscillator frequency when the FB voltage is below 400mV. It is recommended to place the resistor divider as close to FB pin as possible. Vias should be avoided on the FB traces. Internal 5V LDO output. The driver and control circuits are powered from this voltage. Decouple with 0.1μF-0.22μF cap. And the capacitance should be no more than 0.22μF. EN=high to enable the MP1499. External clock can be applied to EN pin for changing switching frequency. For automatic start-up, connect EN pin to VIN with 100KΩ resistor. Bootstrap. A capacitor connected between SW and BST pins is required to form a floating supply across the high-side switch driver. No connection internal. This pin can connect to GND. System Ground. This pin is the reference ground of the regulated output voltage. For this reason care must be taken in PCB layout. Suggested to be connected to GND with copper and vias. Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is driven up to the VIN voltage by the high-side switch during the on-time of the PWM duty cycle. The inductor current drives the SW pin negative during the off-time. The on-resistance of the low-side switch and the internal body diode fixes the negative voltage. Use wide PCB traces and multiple vias to make the connection. Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The MP1499 operates from a +4.5V to +16V input rail. Low ESR, and low inductance capacitor C1 is needed to decouple the input rail. Place the input capacitor very close to this pin and connect it with wide PCB traces and multiple vias to make the connection. Soft Start. Connect on external capacitor to program the soft start time for the switch mode regulator. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 8 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER FUNCTIONAL BLOCK DIAGRAM IN VCC + - VCC Regulator RSEN Currrent Sense Amplifer Boost Regulator Oscillator HS Driver + 1pF EN/SYNC Reference 6.5V 1MEG SS 50pF 400k BST Current Limit Comparator Comparator On Time Control Logic Control + + - SW VCC LS Driver Error Amplifier GND FB Figure 1—Functional Block Diagram MP1499 Rev. 1.0 7/26/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 9 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER OPERATION The MP1499 is a high frequency synchronous rectified step-down switch mode converter with built in internal power MOSFETs. It offers a very compact solution to achieve 5A peak output current over a wide input supply range with excellent load and line regulation. The MP1499 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 90% of one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases, a 0.1uF ceramic capacitor for decoupling purpose is required. Error Amplifier The error amplifier compares the FB pin voltage with the internal 0.807V reference (REF) and outputs a current proportional to the difference between the two. This output current is then used to charge or discharge the internal compensation network to form the COMP voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Enable/SYNC control EN/Sync is a digital control pin that turns the regulator on and off. Drive EN high to turn on the regulator, drive it low to turn it off. There is an internal 1MΩ resistor from EN/Sync to MP1499 Rev. 1.0 7/26/2012 GND thus EN/Sync can be floated to shut down the chip. The EN pin is clamped internally using a 6.5V series-Zener-diode as shown in Figure 2. Connecting the EN input pin through a pullup resistor to the voltage on the VIN pin limits the EN input current to less than 100µA. For example, with 12V connected to Vin, RPULLUP ≥ (12V – 6.5V) ÷ 100µA = 55kΩ. Connecting the EN pin directly to a voltage source without any pullup resistor requires limiting the amplitude of the voltage source to ≤6V to prevent damage to the Zener diode. Figure 2—6.5V Zener Diode Connection The chip can be synchronized to external clock range from 200kHz up to 2MHz through this pin as soon as an external clock is added to this pin, with the internal clock rising edge synchronized to the external clock rising edge. Under-Voltage Lockout (UVLO) The MP1499 has under-voltage lock-out protection (UVLO). When the VCC voltage is higher than the UVLO rising threshold voltage, the MP1499 will be powered up. It shuts off when the VCC voltage is lower than the UVLO falling threshold voltage. This is non-latch protection. The MP1499 is disabled when the input voltage falls below 3.25 V. If an application requires a higher under-voltage lockout (UVLO), use the EN pin as shown in Figure 3 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the enable resistors to set the UVLO falling threshold (VSTOP) above 4.5V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply variations. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 10 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER high, the high-side power MOSFET turns on and remains on until VILsense reaches the value set by the COMP voltage. The internal clock resets every time when VCOMP is higher than VAAM. The SS capacitor value can be determined as follows: CSS nF TSS ms ISS A VREF V (1) If the output capacitors have large capacitance value, it’s not recommended to set the SS time too small. Otherwise, it’s easy to hit the current limit during SS. A minimum value of 4.7nF should be used if the output capacitance value is larger than 330μF. Power Save Mode for Light Load Condition The MP1499 has AAM (Advanced Asynchronous Modulation) power save mode for light load. The AAM voltage is set at 0.4V internally. Under the heavy load condition, the VCOMP is higher than VAAM. When clock goes MP1499 Rev. 1.0 7/26/2012 VOUT 1pF HS_driver Q S VAAM 50pF 400k VCOMP R - R1 - VFB + R2 VREF VIL sense + Figure 4—Simplified AAM Control Logic When the load current is light, the inductor peak current is set internally which is about 1A for VIN=12V, VOUT=3.3V, and L=3.3μH.The curve of inductor peak current vs. inductor is shown in Figure 5. Inductor Peak Current vs. Inductor INDUCTOR PEAK CURRENT (A) If the output is pre-biased to a certain voltage during startup, the IC will disable the switching of both high-side and low-side switches until the voltage on the internal soft-start capacitor exceeds the sensed output voltage at the FB pin. Clock - Soft-Start The MP1499 employs soft start (SS) mechanism to ensure smooth output during power-up. When the EN pin becomes high, an internal current source (11μA) charges up the SS capacitor. The SS capacitor voltage takes over the REF voltage to the PWM comparator. The output voltage smoothly ramps up with the SS voltage. Once the SS voltage reaches the same level as the REF voltage, it keeps ramping up while VREF takes over the PWM comparator. At this point, the soft start finishes and it enters into steady state operation. + Figure 3—Adjustable UVLO Under the light load condition, the value of VCOMP is low. When VCOMP is less than VAAM and VFB is less than VREF, VCOMP ramps up until it exceeds VAAM, during this time, the internal clock is blocked, thus the MP1499 skips some pulses for PFM (Pulse Frequency Modulation) mode and achieves the light load power save. 2.5 VOUT=1V VOUT=1.8V 2 1.5 1 VOUT=2.5V VOUT=3.3V 0.5 VOUT=5V 0 0 1 2 3 4 5 6 Figure5—Inductor Peak Current vs. Inductor Over-Current-Protection and Hiccup The MP1499 has cycle-by-cycle over current limit when the inductor current peak value www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 11 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER exceeds the set current limit threshold. Meanwhile, output voltage starts to drop until FB is below the Under-Voltage (UV) threshold, typically 50% below the reference. Once a UV is triggered, the MP1499 enters hiccup mode to periodically restart the part. This protection mode is especially useful when the output is dead-short to ground. The average short circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. The MP1499 exits the hiccup mode once the over current condition is removed. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, it shuts down the whole chip. When the temperature is lower than its lower threshold, typically 130°C, the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN through D1, M1, C4, L1 and C2 (Figure 6). If (VIN-VSW) is more than 5V, U1 will regulate M1 to maintain a 5V BST voltage across C4. A 10Ω resistor placed between SW and BST cap is strongly recommended to reduce SW spike voltage. MP1499 Rev. 1.0 7/26/2012 R4 Figure 6—Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. Three events can shut down the chip: EN low, VIN low and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 12 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER APPLICATION INFORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see Typical Application on page 1). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Typical Application on page 1). Choose R1 to be around 40kΩ. R2 is then given by: R2 R1 VOUT 0.807V 1 (2) The T-type network is highly recommended when VOUT is low, as Figure 7 shows. FB R1 RT 8 VOUT R2 Figure 7— T-type Network Table 1 lists the recommended T-type resistors value for common output voltages. Table 1—Resistor Selection for Common Output Voltages VOUT (V) 1 1.2 1.8 2.5 3.3 5 R1 (kΩ) 20.5(1%) 30.1(1%) 40.2(1%) 40.2(1%) 40.2(1%) 40.2(1%) R2 (kΩ) 84.5(1%) 61.9(1%) 32.4(1%) 19.1(1%) 13(1%) 7.68(1%) MP1499 Rev. 1.0 7/26/2012 IL(MAX ) ILOAD IL 2 (4) Under light load conditions below 100mA, larger inductance is recommended for improved efficiency. Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, two pieces 22µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: VOUT VOUT 1 VIN VIN (5) The worse case condition occurs at VIN = 2VOUT, where: IC1 A 1µH to 10µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 15mΩ. For most designs, the inductance value can be derived from the following equation. VOUT (VIN VOUT ) VIN IL fS Choose inductor current to be approximately 30% of the maximum load current. The maximum inductor peak current is: I C1 ILOAD RT (kΩ) 160(1%) 160(1%) 82(1%) 33(1%) 33(1%) 33(1%) Selecting the Inductor L1 Where ΔIL is the inductor ripple current. ILOAD 2 (6) For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. (3) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 13 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1μF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: VIN ILOAD V V OUT 1 OUT fS C1 VIN VIN VOUT V 1 OUT fS L1 VIN 1 (8) RESR 8 f C2 S Where L1 is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT V VOUT 1 OUT VIN 8 fS L1 C2 2 (9) In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT MP1499 Rev. 1.0 7/26/2012 VOUT V 1 OUT fS L1 VIN RESR External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external BST diode are: (7) Selecting the Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: VOUT The characteristics of the output capacitor also affect the stability of the regulation system. The MP1499 can be optimized for a wide range of capacitance and ESR values. (10) VOUT is 5V or 3.3V; and Duty cycle is high: D= VOUT >65% VIN In these cases, an external BST diode is recommended from the VCC pin to BST pin, as shown in Figure 8. Figure 8—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1-1uF. PC Board Layout (8) PCB layout is very important to achieve stable operation especially for VCC capacitor and input capacitor placement. For best results, follow these guidelines: 1) 2) 3) Use large ground plane directly connect to GND pin. Add vias near the GND pin if bottom layer is ground plane. Place the VCC capacitor to VCC pin and GND pin as close as possible. Make the trace length of VCC pin-VCC capacitor anode-VCC capacitor cathode-chip GND pin as short as possible. Place the ceramic input capacitor close to IN and GND pins. Keep the connection of input capacitor and IN pin as short and wide as possible. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 14 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER 4) 5) Route SW, BST away from sensitive analog areas such as FB. It’s not recommended to route SW, BST trace under chip’s bottom side. Place the T-type feedback resistor R8 close to chip to ensure the trace which connects to FB pin as short as possible. Notes: 8) The recommended layout is based on the Figure 9 Typical Application circuit on the next page. MP1499 Rev. 1.0 7/26/2012 Design Example Below is a design example following the application guidelines for the specifications: Table 2—Design Example VIN 12V VOUT 3.3V Io 5A Peak The detailed application schematic is shown in Figure 9. The typical performance and circuit waveforms have been shown in the Typical Performance Characteristics section. For more device applications, please refer to the related Evaluation Board Datasheets. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 15 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUITS VIN 9 1 C1A VCC C1B U1 VIN BST C1C 2 GND VCC NC 5 SW 8 C4 R3 100k EN/SYNC 1 3 GND C7 22nF 1 1 L1 VOUT 2 GND FB 1 R8 33k 1 C2A C6 33pF GND R1 40.2k C2B GND C2C GND GND1 6,7 10 SS GND C3 EN/SYNC SS 1 R5 10 MP1499GD 1 GND 4 1 R2 13k GND GND GND GND Figure 9—12V Input-3.3V/5A Peak Output VIN U1 9 1 C1A VCC C1B VIN BST C1C MP1499GD 1 GND GND 2 GND NC 4 R5 10 C3 5 VCC C4 SS GND 1 1 R3 100k GND 3 10 C7 22nF 8 1 L1 VOUT 2 VOUT 1 C2A C2B C2C C6 33pF EN/SYNC GND 1 SS 6,7 EN/SYNC SW FB 1 R8 33k R1 40.2k GND GND R2 7.68k GND GND GND1 GND GND GND GND Figure 10—12V Input-5V/5A Peak Output MP1499 Rev. 1.0 7/26/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 16 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER VIN U1 9 1 C1A VCC C1B VIN BST C1C MP1499GD 1 GND GND 2 GND NC 4 R5 10 C3 5 VCC C4 SS GND GND 3 10 1 L1 VOUT 2 VOUT1 C2A C2B C2C C6 47pF SS C7 22nF 1 1 EN/SYNC GND 1 8 FB 1 R8 82k GND R1 40.2k GND GND R2 32.4k 6,7 R3 100k EN/SYNC SW GND GND1 GND GND GND GND Figure 11—12V Input-1.8V/5A Peak Output VIN U1 9 1 C1A VCC C1B VIN BST C1C MP1499GD 1 GND GND 2 GND NC 4 R5 10 C3 5 VCC C4 SS GND 1 1 R3 100k GND 3 10 C7 22nF 8 1 L1 VOUT 2 1 VOUT C2A C2B C2C C6 47pF EN/SYNC GND 1 SS 6,7 EN/SYNC SW FB 1 R8 160k R1 20.5k GND GND R2 84.5k GND GND GND1 GND GND GND GND Figure 12—12V Input-1V/5A Peak Output MP1499 Rev. 1.0 7/26/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 17 MP1499 – 16V/5A PEAK SYNCHRONOUS STEP-DOWN CONVERTER PACKAGE INFORMATION QFN10 (2X3mm) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP1499 Rev. 1.0 7/26/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 18