MPS MP6219

MP6219
5V, 1A – 2A Programmable Current Limit
Power Distribution Switch
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP6219 is a protection device designed to
protect circuitry on the output from transients on
input. It also protects input from undesired shorts
and transients coming from the output.
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The MP6219 is an integrated power switch with
programmable current limit. The max load at the
output is current limited. This is accomplished by
utilizing a sense FET topology. The magnitude of
the current limit is controlled by an external
resistor.
An internal charge pump drives the gate of the
power device. It features a 44mΩ switch for high
efficiency and requires minimal external
components.
The MP6219 features current protection and
thermal shutdown for fault control. It also involves
UVLO and output over voltage protection.
Integrated 44mΩ FET
Adjustable Current Limit to 2A
Optimized for 5V Inputs
Enable Active High
1.1ms Soft-Start Rise Time
UL File # E322138
APPLICATIONS
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USB Power Distribution
PCI Bus Power
Notebook PC
Inrush Current Limit
Heavy Capacitive Loads
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The MP6219 is available in an 8-pin SOICE
package.
TYPICAL APPLICATION
1
Input
+5V
2
To USB
Peripheral
OUT
3 OUT
4
GND
IN
EN/FAULT
MP6219
N.C.
OUT
IPRGM
8
7
ON/OFF Input
or Fault Output
6
5
RPRGM
UL Recognized Component
MP6219 Rev.0.93
10/20/2010
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© 2010 MPS. All Rights Reserved.
1
MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
ORDERING INFORMATION
Part Number*
Package
Top Marking
Free Air Temperature (TA)
MP6219DN
SOIC8E (Exposed Pad)
MP6219DN
–40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP6219DN–Z).
For RoHS Compliant packaging, add suffix –LF (e.g. MP6219DN–LF–Z)
PACKAGE REFERENCE
TOP VIEW
1
8
2
7
3
6
4
5
ABSOLUTE MAXIMUM RATINGS (1)
IN, OUT, IPRGM ................................................ 8V
EN/FAULT ..................................................... 6V
Junction Temperature………….–40°C to +150°C
(2)
Continuous Power Dissipation
(TA = +25°C)
............................................................. 2.5W
Storage Temperature.............. –65°C to +155°C
Recommended Operating Conditions
Input Voltage…………………………….5V ± 10%
Operating Junct.Temp. ........... .-40°C to +125°C
MP6219 Rev.0.93
10/20/2010
Thermal Resistance (3)
θJA
θJC
SOIC8E ...................................50 ...... 10 ... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) Measured on JESD51-7 4-layer board.
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2
MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
ELECTRICAL CHARACTERISTICS
VIN = 5V, RPRGM=24Ω, COUT = 10µF, TJ=25°C, unless otherwise noted.
Parameters
Power FET
Symbol
Delay Time
tDLY
ON Resistance
RDSon
Off State Output Voltage
VOFF
Thermal Latch
Shutdown Temperature
Under/Over Voltage Protection
TSD
Output Clamping Voltage
VCLAMP
Under Voltage Lockout
Under Voltage Lockout (UVLO)
Hysteresis
Current Limit
Current Limit
Trip Current
Slew Rate
Output Rise Time
EN/Fault
Low Level Input Voltage
VUVLO
ILIM-SS
ILIM-OL
Intermediate Level Input Voltage
VI (INT)
High Level Input Voltage
High State Maximum Voltage
Low Level Input Current (Sink)
VIH
VI (MAX)
IIL
Supply Current
Enabling of chip to
ID=100mA, 12Ω resistive
load
TJ=25°C
TJ=80°C, Note 4
VIN=8Vdc, Enable=0Vdc,
RL=500Ω
Overvoltage Protection
VIN=8V
Turn on, VIN rising
RPRGM=24Ω
RPRGM=24Ω
VIL
Output Disabled
Thermal Fault, Output
Disabled
Output Enabled
VMIN
Max
0.2
44
95
Units
ms
82
120
mΩ
mV
°C
5.95
6.65
7.35
V
3.2
3.6
4.0
V
0.1
Note 5
VMAX
Typ
175
Tr
IQ
Minimum Operating Voltage for
UVLO
Min
VHYST
Maximum Fanout for Fault Signal
Maximum Voltage on Enable Pin
Total Device
Condition
1.4
2.0
3.0
V
2.7
1.1
0.80
1.6
ms
0.5
V
2.0
V
2.5
VENABLE=0V
Total number of chips that
can be connected for
simultaneous shutdown
Note 6
Device Operational, No load
Thermal Shutdown
Enable<0.5V
4.8
-28
1.5
0.5
A
A
V
V
-50
µA
3
Units
VIN
V
2.0
3.0
mA
V
Notes:
4) Guaranteed by design.
5) Measured from 10% to 90%.
6) Maximum Input Voltage to be≤6.0V if VIN ≥ 6.0V. Maximum Input Voltage to be VIN if VIN ≤ 6.0V.
MP6219 Rev.0.93
10/20/2010
www.MonolithicPower.com
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MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
PIN FUNCTIONS
Pin #
1
2, 3, 4
5
6
7
8
Description
Input to the device. 5V nominal Input Voltage
This pin is the output of the internal power FET.
A resistor between this pin and the OUTPUT pin sets the overload and short circuit
IPRGM
current limit levels.
N.C.
No Connect.
The EN/Fault pin is a tri-state, bi-directional interface. It can be used to enable the
output of the device by floating the pin, or disable the chip by pulling it to ground
EN/FAULT (using an open drain or open collector device). If a thermal fault occurs, the voltage
on this pin will go to an intermediate state to signal a monitoring circuit that the device
is in thermal shutdown.
GND
Negative Input Voltage to the Device. This is used as the internal reference for the IC.
Exposed Pad Connect Exposed Pad to GND plane proper thermal performance.
MP6219 Rev.0.93
10/20/2010
Name
IN
OUT
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MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VEN=3.3V, RPRGM=24Ω, COUT=10uF, TA=25°C, unless otherwise noted.
Supply Current,
Output Enabled vs.
Input Voltage
VEN=3.3V, no load
360
VEN=0V
1.2
1.15
1.1
IOUT=0.5A
3.5
4
4.5
5
5.5
58
57
340
56
55
54
320
53
52
51
300
3.5
1.05
6
4
INPUT VOTAGE (V)
120
V IN=5.5V
100
6
3.5
80
60
40
4
4.5
5
5.5
6
INPUT VOTAGE (V)
Trip Current Vs.
Input Voltage
3.5
2.5
HOLD CURRENT(A)
140
5.5
Hold Current vs.
Input Voltage
V IN=4V
V IN=4.5V
V IN=5V
160
5
TRIP CURRENT (A)
180
4.5
INPUT VOTAGE (V)
Input to
Output Voltage vs.
Load Current
INPUT TO
OUTPUT VOLTAGE(mV)
60
59
1.25
SUPPLY CURRENT (uA)
SUPPLY CURRENT (mA)
1.3
Static Drain-Source
On-State Resistance vs.
Input Voltage
Supply Current,
Output Disabled vs.
Input Voltage
2.2
1.9
3
2.5
2
20
0
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
1.6
3.5
3
Current Limit Response
Vs.
Peak Current
no COUT
25
20
15
10
5
0
6
3.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
6
Trip Current
and Hold Current vs.
R PRGM
4
TRIP CURRENT
AND HOLD CURRENT(A)
RESPONSE TIME(us)
30
1.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
Trip Current
3
2
1
Hold Current
0
0
5
10
15
20
25
30
0
20
40
60
80
100
120
PEAK CURRENT (A)
MP6219 Rev.0.93
10/20/2010
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MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VEN=3.3V, RPRGM=24Ω, COUT=10uF, TA=25°C, unless otherwise noted.
Turn On Delay
and Rise Time
with 1uF Load
Turn Off Delay
and Fall Time
with 1uF Load
COUT=1uF, no load
COUT=1uF, no load
VOUT
2V/div
VOUT
2V/div
EN
2V/div
EN
2V/div
VOUT
2V/div
EN
2V/div
400us/div
400us/div
400us/div
Short Circuit Current
Device Enabled into Short
and Thermal Shut Down
Short Circuit Current
Device Enabled into Short
EN floating
VOUT
2V/div
IOUT
1A/div
IOUT
1A/div
EN
2V/div
EN
2V/div
2V/div
40us/div
EN
200us/div
100ms/div
Trip Current with
Ramped Load on
Enabled Device
VOUT
2V/div
VOUT
2V/div
EN
2V/div
2200uF
IOUT
1A/div
IOUT
1A/div
4ms/div
MP6219 Rev.0.93
10/20/2010
1000uF
470uF
IOUT
2A/div
2ms/div
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100us/div
6
MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VEN=3.3V, RPRGM=24Ω, COUT=10uF, TA=25°C, unless otherwise noted.
VOUT
2V/div
VOUT
2V/div
EN=1.5V
EN
5V/div
Hold Current=2.2A
Trip Current=3.13A
IOUT
5A/div
Thermal Shutdown
IOUT
1A/div
100us/div
MP6219 Rev.0.93
10/20/2010
200ms/div
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MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
BLOCK DIAGRAM
IN
EN/
FAULT
Enable
Charge
Pump
OUT
Thermal
Shutdown
Current
Limit
I-LIMIT
UVLO
Voltage
Clamp
dv/dt
Control
GND
Figure 1—Functional Block Diagram
MP6219 Rev.0.93
10/20/2010
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MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
CURRENT LIMIT
The desired current limit is a function of the
external current limit resistor.
Table1-Current Limit vs. Current Limit Resistor
(VIN=5V)
Current Limit Resistor
Trip Current
Hold Current
24Ω
3.0A
2.0A
50Ω
2.25A
1.1A
100Ω
2.0A
0.6A
When the part is active, if load reaches trip
current (minimum threshold current triggering
overcurrent protection) or a short is present, the
part switches into to a constant-current (hold
current) mode. Part will be shutdown only if the
overcurrent condition stays long enough to
trigger thermal protection.
However, when the part is powered up by VCC or
EN, the load current should be smaller than hold
current. Otherwise, the part can’t be fully turned
on.
In a typical application using a current limit
resistor of 24Ω, the trip current will be 3A and the
hold current will be 2A. If the device is in its
normal operating state and passing 2A it will
need to dissipate only 176mW with the very low
on resistance of 44mΩ. For the package
dissipation of 50°C/Watt, the temperature rise will
only be + 8.8°C. Combined with a 25°C ambient,
this is only 33.8°C total package temperature.
During a short circuit condition, the device now
has 5V across it and the hold current clamps at
2A and therefore must dissipate 10W. At
50°C/watt, if uncontrolled, the temperature would
rise above the thermal protection threshold
(+175°C) and the device will shutdown to cause
the temperature to drop.
Proper heat sink must be used if the device is
intended to supply the hold current and not
shutdown. Without a heat sink, hold current
should be maintained below 600mA at + 25°C
and below 360mA at +85°C to prevent the device
from activating the thermal shutdown feature.
MP6219 Rev.0.93
10/20/2010
EN/FAULT PIN
The EN/Fault Pin is a Bi-Directional three level
I/O with a weak pull up current (28uA typical).
The three levels are low, mid and high. It
functions to enable/disable the part and to relay
Fault information.
EN/Fault pin as an input:
1.
Low and mid disable the part.
2.
Low, in addition to disabling the part,
clears the fault flag.
3.
High enables the part (if the fault flag is
clear).
EN/Fault pin as an output:
1.
The pull up current may (if not over
ridden) allow a “wired nor” pull up to
enable the part.
2.
An under voltage will cause a low on the
EN/Fault pin, and will clear the fault flag.
3.
A thermal fault will cause a mid level on
the EN/Fault pin, and will set the fault
flag.
The EN/Fault line must be above the mid level for
the output to be turned on.
The fault flag is a internal flip-flop that can be set
or reset under various conditions:
1.
Thermal Shutdown: set fault flag
2.
Under Voltage: reset fault flag
3.
Low voltage on EN/Fault pin: reset fault
flag
4.
Mid voltage on EN/Fault pin: no effect
Under a fault, the EN/Fault pin is driven to the
mid level.
There are 4 types of faults, and each fault has a
direct and indirect effect on the EN/Fault pin and
the internal fault flag.
In a typical application where there are multiple
MP6219 chips in a system, the EN/Fault lines are
typically connected together.
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MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
Table2-Fault Function Influence in Application
Fault description
Internal action
Short/over current
Limit current
Under Voltage
Output is turned off
Over Voltage
Limit output voltage
Shutdown part. The
part is latched off
until a UVLO or
externally driven to
ground.
Thermal Shutdown
Effect on Fault
Pin
Effect on
Flag
Effect on secondary
Part
none
Internally drives
EN/Fault pin to
Logic low
None
none
Flag is
reset
none
Secondary part output is
disabled, and fault flag is
reset.
None
Internally drives
EN/Fault pin
to mid level
Flag is Set
UNDER VOLTAGE LOCK OUT OPERATION
If the supply (input) is below the UVLO threshold,
the output is disabled, and the fault line is driven
low.
When the supply goes above the UVLO
threshold, the output is enabled and the fault line
is released. When the fault line is released it will
be pulled high by a 28uA current source. No
external pull up resistor is required. In addition,
the pull up voltage is limited to 5 volts.
THERMAL PROTECTION
When thermal protection is triggered, the output
is disabled and the fault line is driven to the mid
level. The thermal fault condition is latched
None
Secondary part output is
disabled.
(meaning the fault flag is set), and the part will
remain latched off until the fault (enable) line is
brought low. Cycling the power below the UVLO
threshold will also reset the fault flag.
PCB LAYOUT
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take below figure for reference.
Place RPRGM close to IPRGM pin and input cap
close to IN pin. Keep the N/C pin float. Put vias in
thermal pad and ensure enough copper area
near IN and OUT to achieve better thermal
performance.
VOUT
C3
RPRGM
5
4 OUT
N/C 6
3 OUT
EN/ FAULT 7
2 OUT
IPRGM
EN/ FAULT
GND 8
1
IN
C2
C1
GND
VIN
GND
Top Layer
Bottom Layer
Figure 2—PCB Layout
MP6219 Rev.0.93
10/20/2010
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MP6219 – PROGRAMMABLE CURRENT LIMIT (2A) POWER DISTRIBUTION SWITCH
PACKAGE INFORMATION
SOIC8E (EXPOSED PAD)
0.189(4.80)
0.197(5.00)
0.124(3.15)
0.136(3.45)
8
5
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.089(2.26)
0.101(2.56)
4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.051(1.30)
0.067(1.70)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.013(0.33)
0.020(0.51)
0.0075(0.19)
0.0098(0.25)
SIDE VIEW
0.050(1.27)
BSC
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0.050(1.27)
0.024(0.61)
0o-8o
0.016(0.41)
0.050(1.27)
0.063(1.60)
DETAIL "A"
0.103(2.62)
0.138(3.51)
RECOMMENDED LAND PATTERN
0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP6219 Rev. 0.93
10/20/2010
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MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
11