DS90LV001 800 Mbps LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the LLP (Leadless Leadframe Package) package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance. A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator. An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE. The DS90LV001 is offered in two package options, an 8 pin LLP and SOIC. Features ■ ■ ■ ■ ■ ■ ■ Single +3.3 V Supply LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Receiver input threshold < ±100 mV Fast propagation delay of 1.4 ns (typ) Low jitter 800 Mbps fully differential data path 100 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps ■ Compatible with ANSI/TIA/EIA-644-A LVDS standard ■ 8 pin SOIC and space saving (70%) LLP package ■ Industrial Temperature Range Connection Diagram Top View 10133805 Order Number DS90LV001TM, DS90LV001TLD See NS Package Number M08A, LDA08A Block Diagram 10133802 © 2008 National Semiconductor Corporation 101338 www.national.com DS90LV001 800 Mbps LVDS Buffer February 19, 2008 DS90LV001 Maximum Package Power Dissipation at 25°C M Package 726 mW Derate M Package 5.8 mW/°C above +25°C LDA Package 2.44 W Derate LDA Package 19.49 mW/°C above +25°C ESD Ratings Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage (EN) LVDS Receiver Input Voltage (IN +, IN−) LVDS Driver Output Voltage (OUT +, OUT−) LVDS Output Short Circuit Current Junction Temperature Storage Temperature Range Lead Temperature Range Soldering (4 sec.) −0.3V to +4V −0.3V to (VCC + 0.3V) ≥2.5kV ≥250V (HBM, 1.5kΩ, 100pF) (EIAJ, 0Ω, 200pF) −0.3V to +4V Recommended Operating Conditions −0.3V to +4V Continuous +150°C −65°C to +150°C Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature +260°C Min 3.0 0 −40 Typ 3.3 +25 Max 3.6 VCC +85 Units V V °C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Symbol Parameter Conditions Min Typ Max Units VCC V LVCMOS/LVTTL DC SPECIFICATIONS (EN) VIH High Level Input Voltage 2.0 VIL Low Level Input Voltage 0.8 V IIH High Level Input Current VIN = 3.6V or 2.0V, VCC = 3.6V +7 +20 μA IIL Low Level Input Current VIN = GND or 0.8V, VCC = 3.6V ±1 ±10 μA VCL Input Clamp Voltage ICL = −18 mA −0.6 −1.5 V 325 450 mV 20 mV 1.375 V 20 mV ±1 ±10 μA GND LVDS OUTPUT DC SPECIFICATIONS (OUT) VOD Differential Output Voltage RL = 100Ω ΔVOD Change in Magnitude of VOD for Complimentary Output States Figure 1 and Figure 2 VOS Offset Voltage RL = 100Ω ΔVOS Change in Magnitude of VOS for Complimentary Output States Figure 1 IOZ Output TRI-STATE Current EN = 0V, VOUT = VCC or GND IOFF Power-Off Leakage Current VCC = 0V, VOUT = 3.6V or GND ±1 ±10 μA IOS Output Short Circuit Current (Note 4) EN = VCC, VOUT+ and VOUT− = 0V −16 −24 mA IOSD Differential Output Short Circuit Current (Note 4) EN = VCC, VOD = 0V −7 −12 mA 0 +100 mV 250 1.080 1.19 LVDS RECEIVER DC SPECIFICATIONS (IN) VTH Differential Input High Threshold VTL Differential Input Low Threshold VCM = +0.05V, +1.2V or +3.25V VCMR Common Mode Voltage Range VID = 100mV, VCC = 3.3V IIN Input Current VIN = +3.0V ΔIIN Change in Magnitude of IIN −100 0 3.25 V ±1 ±10 μA ±1 ±10 μA 1 6 μA VIN = 0V 1 6 μA VCC = 3.6V or 0V VIN = 0V VIN = +3.0V VCC = 3.6V or 0V 0.05 mV SUPPLY CURRENT ICCD Total Supply Current EN = VCC, RL = 100Ω, CL = 5 pF 47 70 mA ICCZ TRI-STATE Supply Current EN = 0V 22 35 mA www.national.com 2 Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3) Symbol Min Typ Max Units tPHLD Differential Propagation Delay High to Low Parameter RL = 100Ω, CL = 5pF Conditions 1.0 1.4 2.0 ns tPLHD Differential Propagation Delay Low to High Figure 3 and Figure 4 1.0 1.4 2.0 ns tSKD1 Pulse Skew |tPLHD − tPHLD| (Notes 5, 6) 20 200 ps tSKD3 Part to Part Skew (Notes 5, 7) 0 tSKD4 Part to Part Skew (Notes 5, 8) tLHT Rise Time (Note 5) RL = 100Ω, CL = 5pF 200 tHLT Fall Time (Note 5) Figure 3 and Figure 5 200 tPHZ Disable Time (Active High to Z) RL = 100Ω, CL = 5pF tPLZ Disable Time (Active Low to Z) Figure 6 and Figure 7 tPZH Enable Time (Z to Active High) tPZL Enable Time (Z to Active Low) tDJ LVDS Data Jitter, Deterministic (Peak-to-Peak) (Note 9) VID = 300mV; PRBS = 223 − 1 data; VCM = 1.2V at 800Mbps (NRZ) tRJ LVDS Clock Jitter, Random (Note 9) VID = 300mV; VCM = 1.2V at 400MHz clock 60 ps 400 ps 320 450 ps 310 450 ps 3 25 ns 3 25 ns 25 45 ns 25 45 ns 100 135 ps 2.2 3.5 ps Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Note 3: All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. Note 4: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and temperature) range. Note 6: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 7: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Note 8: tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with RG142B cable exhibit a tDJ = 21ps and tRJ = 1.8ps. 3 www.national.com DS90LV001 AC Electrical Characteristics DS90LV001 DC Test Circuits 10133803 FIGURE 1. Differential Driver DC Test Circuit 10133808 FIGURE 2. Differential Driver Full Load DC Test Circuit AC Test Circuits and Timing Diagrams 10133806 FIGURE 3. LVDS Output Load 10133807 FIGURE 4. Propagation Delay Low-to-High and High-to-Low www.national.com 4 DS90LV001 10133809 FIGURE 5. LVDS Output Transition Time 10133801 FIGURE 6. TRI-STATE Delay Test Circuit 10133804 FIGURE 7. Output active to TRI-STATE and TRI-STATE to active output time 5 www.national.com DS90LV001 DS90LV001 Pin Descriptions (SOIC and LLP) Pin Name Pin # Input/Output GND 1 P Ground Description IN − 2 I Inverting receiver LVDS input pin IN+ 3 I Non-inverting receiver LVDS input pin NC 4 VCC 5 P Power Supply, 3.3V ± 0.3V. No Connect OUT+ 6 O Non-inverting driver LVDS output pin OUT - 7 O Inverting driver LVDS output pin EN 8 I Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRI-STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL levels. DAP NA NA Die Attach Pad or DAP (LLP Package only). The DAP is NOT connected to the device GND nor any other pin. It is still recommended to connect the DAP to a GND plane of a PCB for enhenced heat dissipation. Typical Applications Backplane Stub-Hider Application 10133811 www.national.com 6 DS90LV001 Cable Repeater Application 10133810 PCB LAYOUT AND POWER SYSTEM BYPASS Circuit board layout and stack-up for the DS90LV001 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the DS90LV001 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. There are more common practices which should be followed when designing PCBs for LVDS signaling. Please see application note AN-1108 for guidelines. In addition, application note AN-1187 has additional information specifically related to LLP recommendations. Application Information MODE OF OPERATION The DS90LV001 can be used as a "stub-hider." In many systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on the individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns and PCB designs often make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the LLP (Leadless Leadframe Package) package, can improve system performance by allowing the receiver to be placed very close to the main transmission line either on the backplane itself or very close to the connector on the card. Longer traces to the LVDS receiver may be placed after the DS90LV001. This very small LLP package is a 75% space savings over the SOIC package. INPUT FAILSAFE The receiver inputs of the DS90LV001 do not have internal failsafe biasing. For point-to-point and multidrop applications with a single source, failsafe biasing may not be required. When the driver is off, the link is in-active. If failsafe biasing is required, this can be accomplished with external high value resistors. Using the equations in the LVDS Owner"s Manual Chapter 4, the IN+ should be pull to VCC (3.3V) with 20kΩ and the IN− should be pull to GND with 12kΩ. This provides a slight positive differential bias, and sets a known HIGH state on the link with a minimum amount of distortion. 10133815 7 www.national.com DS90LV001 Typical Performance Curves Output High Voltage vs Power Supply Voltage Output Low Voltage vs Power Supply Voltage 10133816 10133817 Output Short Circuit Current vs Power Supply Voltage Differential Output Short Circuit Current vs Power Supply Voltage 10133818 10133819 www.national.com 8 DS90LV001 Output TRI-STATE Current vs Power Supply Voltage Offset Voltage vs Power Supply Voltage 10133820 10133821 Differential Output Voltage vs Power Supply Voltage Differential Output Voltage vs Load Resistor 10133822 10133823 Power Supply Current vs Frequency Power Supply Current vs Power Supply Voltage 10133825 10133824 9 www.national.com DS90LV001 TRI-STATE Power Supply Current vs Power Supply Voltage Differential Transition Voltage vs Power Supply Voltage 10133827 10133826 Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature 10133828 www.national.com 10133836 10 DS90LV001 Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature 10133829 10133837 Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature 10133830 10133838 11 www.national.com DS90LV001 Differential Propagation Delay vs Differential Input Voltage Differential Propagation Delay vs Common-Mode Voltage 10133831 10133832 Peak-to-Peak Output Jitter at VCM = 0.4V vs Differential Input Voltage Peak-to-Peak Output Jitter at VCM = 2.9V vs Differential Input Voltage 10133833 www.national.com 10133835 12 Peak-to-Peak Output Jitter at VCM = 1.2V vs Ambient Temperature 10133834 10133839 13 www.national.com DS90LV001 Peak-to-Peak Output Jitter at VCM = 1.2V vs Differential Input Voltage DS90LV001 Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS90LV001TM See NS Package Number M08A Order Number DS90LV001TLD See NS Package Number LDA08A www.national.com 14 DS90LV001 Notes 15 www.national.com DS90LV001 800 Mbps LVDS Buffer Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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