74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 • • • • • • • • • Internal Look-Ahead Circuitry for Fast Counting Carry Output for N-Bit Cascading Fully Synchronous Operation for Counting Synchronously Programmable Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs DW OR N PACKAGE (TOP VIEW) RCO QA QB GND GND GND GND QC QD LOAD 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 CLR CLK A B VCC VCC C D ENP ENT description This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters; however, counting spikes may occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock-input waveform. These counters are fully programmable in that they may be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when power is applied, it progresses to the normal sequence within two counts as shown in the state diagram. The clear function for the 74AC11162 is synchronous, and a low level at the clear (CLR) input drives all four of the flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels on the count-enable (ENP and ENT) inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL on the Q outputs). EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 description (continued) The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output. Both ENP and ENT must be high to count, and ENT is fed foward to enable RCO. RCO thus enabled produces a high-level pulse while the count is 9 (HLLH). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at the ENP or ENT inputs are allowed regardless of the level of the clock input. These counters feature fully independent clock circuits. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times. The 74AC11162 is characterized for operation from – 40°C to 85°C. logic symbol† CLR LOAD ENT ENP CLK A B C D 20 10 11 12 19 18 17 14 13 state diagram CTRDIV10 5CT = 0 M1 M2 3CT = 9 G3 0 1 2 3 4 15 5 14 6 13 7 RCO G4 C5/2,3,4+ 1, 5D 1 2 4 8 2 3 8 9 QA QB QC 12 QD † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 10 9 8 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 logic diagram (positive logic) LOAD ENT ENP 10 11 1 RCO 12 LD † CK † CLK CLR 19 CK 20 LD R M1 G2 A 1,2T/1C3 G4 18 2 QA 3D 4R M1 G2 B 1,2T/1C3 G4 17 3 QB 3D 4R M1 G2 1,2T/1C3 G4 C 14 8 QC 3D 4R M1 G2 D 1,2T/1C3 G4 13 9 QD 3D 4R † For the sake of simplicity, the routing of the complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 logic symbol (Load) LD M1 (Toggle Enable) TE G2 (Clock) CK G4 (Data) D 3D (Inverted Reset) R 4R Q (Output) 1, 2T/1C3 logic diagram, each D/T flip-flop (positive logic) CK LD TE LD † TG TG Q LD † CK † D CK † TG CK † CK † R † The origins of the signals LD and CK are shown in the logic diagram of the overall device. 4 POST OFFICE BOX 655303 TG • DALLAS, TEXAS 75265 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 output sequence Illustrated below is the following sequence: 1. Clear outputs to zero 2. Preset to BCD seven 3. Count to eight, nine (RCO high), zero, one, two, and three 4. Inhibit CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Outputs QC QD RCO 7 8 9 0 1 2 Count Sync Clear 3 Inhibit† Preset † Counting is inhibited if either or both of ENT and ENP are low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±125 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions (see Note 2) VCC VIH VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 4.5 V VCC = 3 V VIL Low-level input voltage MIN NOM MAX 3 5 5.5 0.9 1.35 0 Output voltage 0 IOH High-level output current VCC = 3 V VCC = 4.5 V 6 VCC = 4.5 V VCC = 4.5 V 24 • DALLAS, TEXAS 75265 V V –4 – 24 – 24 Input transition rise or fall rate POST OFFICE BOX 655303 VCC VCC VCC = 4.5 V VCC = 3 V TA Operating free-air temperature NOTE 2: Unused or floating inputs must be held high or low. V 1.65 Input voltage dt/dv V 3.85 VCC = 4.5 V VCC = 4.5 V Low-level output current V 2.1 3.15 VI VO IOL UNIT V 12 V 24 0 10 ns/ V – 40 85 °C 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = – 50 µA VOH IOH = – 4 mA Ci MAX MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 3.94 3.8 IOL = – 24 mA A 5.5 V 4.94 4.8 IOH = – 75 mA† 5.5 V IOL = 12 mA IOL = 24 mA II ICC TYP 4.5 V IOL = 50 µA VOL TA = 25°C MIN IOL = 75 mA† VI = VCC or GND VI = VCC or GND, VI = VCC or GND UNIT V 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V IO = 0 MAX V 1.65 5.5 V ± 0.1 ±1 µA 5.5 V 8 80 µA 5V 3.5 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1) TA = 25°C MIN MAX fclock tw Clock frequency 0 Pulse duration CLK low or high A, B, C, D LOAD tsu Setup time before CLK↑ ↑ th Hold time, all synchronous inputs after CLK↑ 66 MIN MAX UNIT 0 66 MHz 7.5 7.5 6 6 6 6 ENT, ENP 7.5 7.5 CLR low or high 7.5 7.5 1 1 ns ns ns timing requirements, VCC = 5 V ± 0.5 V (see Figure 1) TA = 25°C MIN MAX fclock tw Clock frequency 0 Pulse duration CLK low or high tsu Setup time before CLK↑ ↑ th Hold time, all synchronous inputs after CLK↑ 110 MIN MAX UNIT 0 110 MHz 4.5 4.5 A, B, C, D 4 4 LOAD 5 5 ENT, ENP 6 6 4.5 4.5 1 1 CLR low or high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns 7 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 66 CLK RCO CLK (LOAD high) Any Q CLK (LOAD low) lo ) Any Q ENT RCO MIN MAX 66 UNIT MHz 1.5 10.5 14.1 1.5 15.9 1.5 12.1 15.8 1.5 18 1.5 8.7 11.7 1.5 13.2 1.5 10.2 14.4 1.5 16 1.5 8.7 11.2 1.5 12.6 1.5 10.4 14.1 1.5 16 1.5 5.8 7.6 1.5 8.5 1.5 6.9 9.9 1.5 11 ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) CLK RCO CLK (LOAD high) Any Q lo ) CLK (LOAD low) Any Q ENT RCO TA = 25°C MIN TYP MAX MIN 110 110 MAX UNIT MHz 1.5 7.7 9.9 1.5 11.2 1.5 8.3 11.9 1.5 12.6 1.5 6.4 8.4 1.5 9.5 1.5 7.4 10.5 1.5 11.9 1.5 6 7.9 1.5 9 1.5 7.2 10.1 1.5 11.5 1.5 4 5.5 1.5 6 1.5 5 7.4 1.5 8.8 ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 8 TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 54 pF 74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION Timing Input (see Note B) From Output Under Test VCC 50% 0V th tsu CL = 50 pF (see Note A) 500 Ω VCC Data Input 50% 50% 0V SETUP AND HOLD TIMES LOAD CIRCUIT VCC Input (see Note B) 50% VCC 50% VCC 0V VCC High-Level Input 50% tPLH 50% 0V In-Phase Output tw Low-Level Input tPHL 50% VCC VCC 50% tPLH tPHL 50% 0V Out-of-Phase Output VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL PROPAGATION DELAY TIMES PULSE DURATION NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. For testing fmax and pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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