SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 • • • • • • • • • DW OR N PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Single Down/Up Count Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs RCO QA QB GND GND GND GND QC QD MAX/MIN 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 D/U CLK A B VCC VCC C D CTEN LOAD description The 74ACT11191 is a synchronous, 4-bit binary reversible up/down counter. A synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condition meeting the stable setup and hold times. logic symbol† CTEN CTRDIV16 G1 M2 [DOWN] 2(CT=0)Z6 3(CT=15)Z6 M3 [UP] 1,2−/1,3+ G4 6,1,4 C5 12 20 D/U CLK 19 LOAD 11 A B C D 18 5D 17 10 2 [1] 3 [2] 14 8 [4] 13 1 9 [8] MAX/MIN RCO QA QB QC QD † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−1 SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 description (continued) These counters are fully programmable; that is, they may be preset to any number between 0 and 15 by placing a low on the load input and entering the desired data at the data inputs. The outputs will change to agree with the data inputs independently of the level of the clock input. This feature allows the counter to be used as a modulo-N divider by simply modifying the count length with the preset inputs. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. The ripple clock output (ROC) produces a low-level output pulse under those same conditions but only while the clock input is low. The counter can easily be cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. The 74ACT11191 is characterized for operation from − 40°C to 85°C. 2−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 logic diagram (positive logic) 10 CTEN D/U CLK LOAD A MAX/MIN 12 1 RCO 20 19 11 18 S 2 C1 1D QA R B 17 S C1 3 QB 1D R 14 C S C1 8 QC 1D R D 13 S C1 9 QD 1D R • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−3 SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 typical load, count, and inhibit sequences Illustrated below is the following sequence: 1. 2. 3. 4. Load (preset) to binary thirteen Count up to fourteen, fifteen (maximum), zero, one, and two Inhibit Count down to one, zero (minimum), fifteen, fourteen, and thirteen. LOAD A B Data Inputs C D CLOCK D/U CTEN QA QB QC QD MAX/MIN RCO 13 14 15 0 1 2 Count Up 2 2 Inhibit Load 2−4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 1 0 15 14 Count Down 13 SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions MIN MAX 4.5 5.5 V High-level input voltage 2 V Low-level input voltage 0.8 V VCC VCC V −24 mA VCC VIH Supply voltage VIL VI Input voltage 0 VO IOH Output voltage 0 IOL Dt /Dv Low-level output current TA Operating free-air temperature High-level output current Input transition rise or fall rate UNIT V 24 mA 0 10 ns/ V − 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = − 50 mA A VOH II ICC DICCw Ci MIN 4.5 V 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 IOH = − 24 mA 5.5 V 4.94 4.8 IOH = − 75 mA} 5.5 V IOL = 50 mA A VOL TA = 25°C MIN TYP MAX IOL = 24 mA IOL = 75 mA} VI = VCC or GND VI = VCC or GND, One input at 3.4 V 3.85 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 1.65 ±1 5.5 V 8 80 mA 5.5 V 0.9 1 mA VI = VCC or GND 5V 4 ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. • V ± 0.1 5.5 V POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • UNIT V 4.5 V 5.5 V IO = 0 Other inputs at GND or VCC MAX mA pF 2−5 SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 LOAD low tw tsu Pulse duration CLK high or low Setup time Hold time MAX UNIT 0 65 MHz 4 4 7.7 7.7 Data before LOAD↓ 3 3 CTEN before CLK↑ 7.5 7.5 D/U before CLK↑ 8.5 8.5 LOAD inactive before CLK↑ th 65 MIN 2 2 Data after LOAD↓ 2.5 2.5 CTEN after CLK↑ 1.5 1.5 D/U after CLK↑ 0.5 0.5 ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 2−6 FROM (INPUT) TO (OUTPUT) LOAD Any Q LOAD MAX/MIN LOAD RCO A, B, C, or D Any Q A, B, C, or D MAX/MIN A, B, C, or D RCO CLK RCO CLK Any Q CLK MAX/MIN D/U RCO D/U MAX/MIN CTEN RCO • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • MIN TA = 25°C TYP MAX MIN MAX 65 95 4 7.6 10.8 65 4 12.2 3.8 7.4 10.5 3.8 11.9 5.2 9.7 13.9 5.2 15.8 4.7 9.5 13.6 4.7 15.4 5.4 10.5 15.1 5.4 17.1 5.8 11 15.7 5.8 17.9 4.5 7.6 10.1 4.5 11.6 3.7 7.1 10.3 3.7 11.7 5.1 9.5 13.6 5.1 15.4 4.7 9.2 13.4 4.7 15.2 5.5 10.3 14.8 5.5 17.2 5.9 10.9 15.5 5.9 18 4.4 7.4 9.5 4.4 11 3.5 6.7 9.5 3.5 10.8 3.6 6.7 9.2 3.6 10.4 4.2 7.1 9.4 4.2 10.8 UNIT MHz 5 8 10.3 5 11.7 5.3 8.6 11.5 5.3 13.1 4.4 8.4 11.7 4.4 13.1 4.2 8.8 11.3 4.2 13 3.2 6.9 9.6 3.2 11 3.6 7.2 10.3 3.6 11.6 3.9 6.4 8.2 3.9 9.2 2.8 6 8.4 2.8 9.5 ns ns ns ns ns ns ns ns ns ns ns ns SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, f = 1 MHz TYP UNIT 68 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) 3V 500 Ω Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS LOAD CIRCUIT 3V Input (see Note B) 3V Timing Input (see Note B) 0V Data Input 1.5 V 0V tPHL tPLH 1.5 V In-Phase Output th tsu 1.5 V 50% VCC 3V 1.5 V tPLH tPHL 1.5 V 0V Out-of-Phase Output VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−7 SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 2−8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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