PSEMI PE42850

Product Specification
PE42850
Product Description
The PE42850 is a HaRP™ technology-enhanced SP5T
high power RF switch supporting wireless applications up
to 1 GHz. It offers maximum power handling of 42.5 dBm
continuous wave (CW). It delivers high linearity and
excellent harmonics performance. It has both a standard
and attenuated RX mode. No blocking capacitors are
required if DC voltage is not present on the RF ports.
The PE42850 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Package Type
32-lead 5x5 mm QFN
UltraCMOS® SP5T RF Switch
30 - 1000 MHz
Features
 Dual mode operation: SP5T or SP3T
 HaRP™ technology enhanced
 Fast settling time
 No gate and phase lag
 No drift in insertion loss and phase
 Up to 45 dBm instantaneous power
in 50Ω
 Up to 40 dBm instantaneous power
< 8:1 VSWR
 36 dB TX to RX isolation
 Low harmonics of 2fo and 3fo = -90 dBc
(1.15:1 VSWR)
 ESD performance
 1.5kV HBM on all pins
Figure 2. Functional Diagram of SP3T
Configuration
ANT can be tied to TX1 and TX2 or TX3 and TX4
Document No. DOC-14614-2 │ www.psemi.com
Figure 3. Functional Diagram of SP5T
Configuration
SP5T, standard configuration
DOC-02178
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12
PE42850
Product Specification
Table 1. Electrical Specifications @ -40 to +85°C, VDD = 2.3 to 5.5V, VssEXT = 0V or VDD = 3.4 to 5.5V,
VssEXT = -3.4V (ZS = ZL = 50Ω ) unless otherwise noted1
Parameter
Path
Condition
Min
Operating frequency
Insertion loss
2
Insertion loss2
(un-attenuated state)
Typ
30
ANT-TX
ANT-RX
Max
Unit
1000
MHz
Active TX port 1, 2, 3 or 4 @ rated power (-40°C, +25°C)
30–520 MHz
520–1000 MHz
0.25
0.35
0.30
0.45
dB
dB
Active TX port 1, 2, 3 or 4 @ rated power (+85°C)
30–520 MHz
520–1000 MHz
0.30
0.45
0.35
0.55
dB
dB
Active RX port (-40°C, +25°C)
30–520 MHz
520–1000 MHz
0.50
0.65
0.60
0.80
dB
dB
Active RX port (+85°C)
30–520 MHz
520–1000 MHz
0.60
0.70
0.70
0.85
dB
dB
1
1.2
dB
16.8
1575 MHz for GPS RX, < -10 dBm, +25°C
ANT-RX
Active RX port
30–1000 MHz
15.2
16
Isolation (supply biased)
TX - TX
30–520 MHz
520–1000 MHz
33
29
36
30
dB
dB
Isolation (supply biased)
TX - RX
30–520 MHz
520–1000 MHz
34
29
36
30
dB
dB
2
Insertion loss (attenuated state)
dB
Unbiased isolation
VDD, V1, V2, V3 = 0V
ANT - TX
+27 dBm
6
dB
Unbiased isolation
VDD, V1, V2, V3 = 0V
ANT - RX
+27 dBm
14
dB
Un-attenuated state
30–520 MHz
520–1000 MHz
22
18
27
22
dB
dB
Un-attenuated state, 1575 MHz for GPS RX, < -10 dBm, +25°C
10
14
dB
Attenuated state, optimized without attenuator engaged
30–520 MHz
520–1000 MHz
16
13
21
18
dB
dB
30–520 MHz
520–1000 MHz
21
15
28
17
dB
dB
Return loss2
Return loss2
ANT-RX
ANT-TX
2nd and 3rd harmonic
(< 1.15:1 VSWR)
TX
30–520 MHz @ +40.0 dBm
521–870 MHz @ +38.5 dBm
871–1000 MHz @ +37.5 dBm
-90
-81
dBc
2nd and 3rd harmonic
(< 8:1 VSWR)
TX
30–520 MHz @ +40.0 dBm (pulsed signal, at 10% duty cycle3)
521–870 MHz @ +38.5 dBm (pulsed signal, at 10% duty cycle3)
871–1000 MHz @ +37.5 dBm (pulsed signal, at 10% duty cycle3)
-82
-74
dBc
2nd and 3rd harmonic
(50Ω source/load impedance)
TX
30–1000 MHz @ +45.0 dBm (pulsed signal, at 10% duty cycle3)
-80
-71
dBc
2nd and 3rd harmonic
(50Ω source/load impedance)
TX
30–1000 MHz @ +42.5 dBm (CW)
-84
-75
dBc
1000 MHz
45.5
Input 0.1 dB compression point4
IIP3
ANT-TX
RX
Un-attenuated state
Attenuated state
dBm
42
33
dBm
dBm
Settling time
From 50% control until harmonics within specifications
30
Switching time
50% CTRL to 90% or 10% RF
15
70
µs
µs
Notes: 1. In a 2TX-1RX SP3T configuration, TX1 and TX2 are tied and TX3 and TX4 are tied respectively. Refer to Application Note AN35 for SP3T performance data
2. Narrow trace widths are used near each port to improve impedance matching. Refer to evaluation board layouts (Figure 23) and schematic (Figure 24) for details
3. 10% of 4620 µs period
4. The input 0.1 dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power PIN
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. DOC-14614-2 │ UltraCMOS® RFIC Solutions
PE42850
Product Specification
25 GND
16
VssEXT
26 GND
15
V1
27 GND
14
V2
28 ANT
13
V3
29 GND
12
VDD
30 GND
11
GND
31 GND
10
GND
GND
9
32 GND
Figure 4. Pin Configuration (Top View)1
Note 1: Pins 1, 3, 5, 7, 9, 10, 17, 19, 20, 22, 24, 26, 27, 29, 30 and 31 can be
N/C if deemed necessary by the customer
Table 2. Pin Descriptions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage (normal
mode, VssEXT = 0V)
VDD
2.3
5.5
V
Supply voltage (bypass
mode, VssEXT = -3.4V,
VDD ≥ 3.4V for full spec.
compliance)
VDD
2.7
5.5
V
Negative supply voltage
(bypass mode)
VssEXT
-3.6
-3.2
V
Supply current (normal
mode, VssEXT = 0V)
IDD
130
200
µA
Supply current (bypass
mode, VssEXT = -3.4V)
IDD
50
80
µA
Negative supply current
(bypass mode, VssEXT =
-3.4V)
ISS
-40
Digital input high
(V1, V2, V3)
VIH
1.17
3.6
V
Digital input low
(V1, V2, V3)
VIL
-0.3
0.6
V
3.4
-16
µA
TX RF input power2,3
(VSWR ≤ 8:1)
PIN-TX
40
dBm
TX RF input power2,3
(50Ω source/load
impedance)
PIN-TX
45
dBm
Pin #
Pin Name
1, 3, 5-7, 911, 17-20,
22, 24-27,
29-32
GND
Ground
TX RF input power2
(50Ω source/load
impedance, CW)
PIN-TX
42.5
dBm
2
TX12
Transmit pin 1
ANT RF input power,
unbiased (VSWR ≤ 8:1)
PIN-ANT
27
dBm
4
TX21,2
Transmit pin 2
27
dBm
RX2
PIN-RX
8
Receive pin
RX RF input power2
(VSWR ≤ 8:1)
12
VDD
Supply voltage (nominal 3.3V)
85
°C
13
V3
Digital control logic input 3
135
°C
14
V2
Digital control logic input 2
15
V1
Digital control logic input 1
16
VssEXT3
21
TX32
Transmit pin 3
23
TX41,2
Transmit pin 4
28
2
Pad
Notes:
Description
Table 3. Operating Ranges1
External Vss negative voltage control
ANT
Antenna pin
GND
Exposed pad: ground for proper operation
Operating temperature
range (case)
Operating junction
temperature
TOP
Tj
-40
Notes: 1. In a 2TX-1RX SP3T configuration, TX1 and TX2 are tied and TX3
and TX4 are tied respectively. Refer to Application Note AN35 for
SP3T performance data
2. Supply biased
3. Pulsed, 10% duty cycle of 4620 µs period
1. To operate the part as a 2TX-1RX SP3T, tie TX1 to TX2 and TX3
to TX4 respectively. Refer to Application Note AN35 for SP3T
performance data
2. RF pins 2, 4, 8, 21, 23 and 28 must be at 0V DC. The RF pins do
not require DC blocking capacitors for proper operation if the 0V DC
requirement is met
3. Use VssEXT (pin 16, VssEXT = -VDD) to bypass and disable internal
negative voltage generator. Connect VssEXT (pin 16) to GND (VssEXT =
0V) to enable internal negative voltage generator
Document No. DOC-14614-2 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 12
PE42850
Product Specification
Table 4. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Switching Frequency
Symbol
Min
Max
Unit
VDD
-0.3
5.5
V
Digital input voltage
(V1, V2, V3)
VCTRL
-0.3
3.6
V
TX RF input power1(50Ω
source/load impedance)
PIN-TX
45
dBm
TX RF input power1
(VSWR ≤ 8:1)
PIN-TX
40
dBm
ANT RF input power, unbiased
(VSWR ≤ 8:1)
PIN-ANT
27
dBm
RX RF input power1
(VSWR ≤ 8:1)
PIN-RX
27
dBm
150
°C
Storage temperature range
TST
Maximum case temperature
TCASE
85
°C
Tj
200
°C
VESD
1500
V
VESD
200
V
Peak maximum junction
temperature
(10 seconds max)
2
ESD voltage HBM , all pins
3
ESD Voltage MM , all pins
-65
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
Optional External Vss Control (VssEXT)
Notes: 1. Supply biased
2. Human Body Model (MIL-STD 883 Method 3015)
3. Machine Model (JEDEC JESD22-A115)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
5x5 mm QFN package is MSL3.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 12
The PE42850 has a maximum 10 kHz switching
rate when the internal negative voltage generator
is used (pin 16 = GND). The rate at which the
PE42850 can be switched is only limited to the
switching time (Table 1) if an external negative
supply is provided (pin 16 = VssEXT).
For proper operation, the VssEXT control pin must
be grounded or tied to the Vss voltage specified in
Table 3. When the VssEXT control pin is grounded,
FETs in the switch are biased with an internal
voltage generator. For applications that require the
lowest possible spur performance, VssEXT can be
applied externally to bypass the internal negative
voltage generator.
Spurious Performance
The typical spurious performance of the PE42850
is -130 dBm when VssEXT = 0V (pin 16 = GND). If
further improvement is desired, the internal
negative voltage generator can be disabled by
setting VssEXT = -3.4V.
Table 5. Truth Table
Path
V3
V2
V1
ANT – RX Attenuated
L
L
L
ANT – TX1
L
L
H
ANT – TX2
L
H
L
L
H
H
ANT – RX
H
L
L
ANT – TX3
H
L
H
ANT – TX4
H
H
L
ANT – TX3 and TX41
H
H
H
ANT – TX1 and TX2
®
1
Note 1: In a 2TX-1RX SP3T configuration, TX1 and TX2 are tied and TX3 and
TX4 are tied respectively. Refer to Application Note AN35 for SP3T
performance data
Document No. DOC-14614-2 │ UltraCMOS® RFIC Solutions
PE42850
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 5. Insertion Loss vs. Temp (TX)
Figure 6. Insertion Loss vs. VDD (TX)
Figure 7. Insertion Loss vs. Temp
(RX, Un-Attenuated)
Figure 8. Insertion Loss vs. VDD
(RX, Un-Attenuated)
Figure 9. Insertion Loss vs. Temp
(RX, Attenuated)
Figure 10. Insertion Loss vs. VDD
(RX, Attenuated)
Document No. DOC-14614-2 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 12
PE42850
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 11. Return Loss vs. Temp (ANT)
Figure 12. Return Loss vs. VDD (ANT)
Figure 13. Return Loss vs. Temp (TX)
Figure 14. Return Loss vs. VDD (TX)
Figure 15. Return Loss vs. Temp
(RX, Attenuated)
Figure 16. Return Loss vs. VDD
(RX, Attenuated)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 12
Document No. DOC-14614-2 │ UltraCMOS® RFIC Solutions
PE42850
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 17. Return Loss vs. Temp
(RX, Un-Attenuated)
Figure 18. Return Loss vs. VDD
(RX, Un-Attenuated)
Figure 19. Isolation vs. Temp (TX-TX)
Figure 20. Isolation vs. VDD (TX-TX)
Figure 21. Isolation vs. Temp (TX-RX)
Figure 22. Isolation vs. VDD (TX-RX)
Document No. DOC-14614-2 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 12
PE42850
Product Specification
Thermal Data
Though the insertion loss for this part is very low,
when handling high power RF signals, the junction
temperature rises significantly.
Table 6. Theta JC
Parameter
Theta JC (+85°C)
Min
Typ
20
Max
Unit
C/W
VSWR conditions that present short circuit loads to
the part can cause significantly more power
dissipation than with proper matching.
Special consideration needs to be made in the
design of the PCB to properly dissipate the heat
away from the part and maintain the 85°C maximum
case temperature. It is recommended to use best
design practices for high power QFN
packages: multi-layer PCBs with thermal vias in a
thermal pad soldered to the slug of the package.
Special care also needs to be made to alleviate
solder voiding under the part.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 12
Document No. DOC-14614-2 │ UltraCMOS® RFIC Solutions
PE42850
Product Specification
Evaluation Kit
Figure 23. Evaluation Board Layouts
The PE42850 Evaluation Kit board was designed
to ease customer evaluation of the PE42850 RF
switch.
The evaluation board in Figure 23 was designed
to test the part in the 5T configuration. DC power
is supplied through J10, with VDD on pin 9, and
GND on the entire lower row of even numbered
pins. To evaluate a switch path, add or remove
jumpers on V1 (pin 3), V2 (pin 5), and V3
(pin 7) using Table 5 (adding a jumper pulls the
CMOS control pin low and removing it allows the
on-board pull-up resistor to set the CMOS control
pin high). Pins 11 and 13 of J10 are N/C.
The ANT port is connected through a 50Ω
transmission line via the top SMA connector, J1.
RX and TX paths are also connected through 50Ω
transmission lines via SMA connectors. A
50Ω through transmission line is available via
SMA connectors J8 and J9. This transmission line
can be used to estimate the loss of the PCB over
the environmental conditions being evaluated. An
open-ended 50Ω transmission line is also provided
at J7 for calibration if needed.
Narrow trace widths are used near each part to
improve impedance matching.
PRT-50283
Document No. DOC-14614-2 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 12
PE42850
Product Specification
Figure 24. Evaluation Board Schematic
.200 X .012TRACE
J1
50 OHM
1
SMA
32
31
30
29
28
27
26
25
2
2 SMA
.200 X .012 TRACE
50 OHM
J4
1
2
SMA
J6
.200 X .012 TRACE
50 OHM
1
2
3
4
5
6
7
8
GND
TX1
GND
TX2
GND
GND
GND
RX
U1
PE4285 0
9
10
11
12
13
14
15
16
SMA
Z1
1
Open Line
1
SMA-DNI
J7
2
R1
1M
R2
1M
R3
1M
SMA
24
23
22
21
20
19
18
17
.200 X .012 TRACE
2
Through Lin
e
1
1
SMA-DNI
SMA-DNI
2
J5
1
2
J10
1
3
5
7
9
11
13
J9
2
J3
50 OHM
SMA
Z=50 Ohm
J8
50 OHM
1
GND
TX4
GND
TX3
GND
GND
GND
GND
GND
GND
NC
VDD
V3
V2
V1
VSS
1
2
.200 X .012 TRACE
33 GND
1
GND
GND
GND
GND
ANT
GND
GND
GND
.200 X .012 TRACE
50 OHM
J2
C4
C3
DNI
C5
0.01u
C6
100pF
C7
100pF
2
4
6
8
10
12
14
2
4
6
8
10
12
14
HEADER14
C8
100pF
1
3
5
7
9
11
13
DNI
DOC-14626
Notes: 1. Use 101-0316-02 PCB
2. 32 mil Width, 10 mil Gaps, 28 mil Core, 4.3 Er, and 2.1 mil Cu
Notes:
1. USE 101-0316 -02 PCB.
2. All Transmission Lines are 50 Ohms
32mil Width, 10mil Gaps, 28mil Core, 4.3 Er, and 2.1mil Cu
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 12
Document No. DOC-14614-2 │ UltraCMOS® RFIC Solutions
PE42850
Product Specification
Figure 25. Package Drawing
32-lead 5x5 mm QFN
A
0.10 C
(2X)
5.00
3.30±0.05
B
17
0.50
24
16
5.00
25
3.30±0.05
Pin #1 Corner
8
1
3.50
DOC-01872
0.10
0.05
0.05 C
C A B
C
ALL FEATURES
SEATING PLANE
0.203
Ref.
5.20
RECOMMENDED LAND PATTERN
0.90 MAX
0.10 C
5.20
3.35
DETAIL A
BOTTOM VIEW
TOP VIEW
3.35
32
9
0.10 C
(2X)
0.50
(X28)
0.575
(x32)
3.50
0.24±0.05
(X32)
0.290
(x32)
0.375±0.05
(X32)
SIDE VIEW
0.05
C
Figure 26. Top Marking Specification
42850
YYWW
ZZZZZZ
= Pin 1 designator
YYWW = Date code, last two digits of the year and work week
ZZZZZZ = Six digits of the lot number
17-0085
Document No. DOC-14614-2 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 12
PE42850
Product Specification
Figure 27. Tape and Reel Drawing
Tape Feed Direction
Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.02
2. Camber not to exceed 1 mm in 100 mm
3. Material: PS + C
4. Ao and Bo measured as indicated
5. Ko measured from a plane on the inside bottom of the
pocket to the top surface of the carrier
6. Pocket position relative to sprocket hole measured as
true position of pocket, not pocket hole
Ao = 5.25 mm
Bo = 5.25 mm
Ko = 1.1 mm
Pin 1
Top of
Device
Device Orientation in Tape
Table 7. Ordering Information
Order Code
Description
Package
Shipping Method
PE42850MLBA-X
PE42850 SP5T RF switch
Green 32-lead 5x5 mm QFN
500 units / T&R
PE42850MLBA-Z
PE42850 SP5T RF switch
Green 32-lead 5x5 mm QFN
3000 units / T&R
EK42850-03
PE42850 Evaluation kit
Evaluation kit
1 / Box
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Advance Information: The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use
of this information. Use shall be entirely at the user’s own risk.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 12
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of
the following U.S. Patents: http://patents.psemi.com.
Document No. DOC-14614-2 │ UltraCMOS® RFIC Solutions