RICHTEK RT9807

RT9807
Micro-Power Voltage Detector with Manual Reset
General Description
Features
The RT9807 is a micro-power voltage detector with
deglitched manual reset input which supervises the power
supply voltage level for microprocessors (μP) or digital
systems. It provides internally fixed threshold levels
ranging from 1.2V to 3.3V with 0.1V per step, which covers
most digital applications. It features low supply current of
3μA.
z
Monitor System Voltages from 0.9V to 5.5V
z
Capacitor-Adjustable Reset Timeout Period
Manual Reset Input
Low Quiescent Current
High Accuracy ±1.5%
Low Functional Supply Voltage 0.9V
N-Channel Open-Drain Output
Small SOT-23-5 Package
RoHS Compliant and Halogen Free
The RT9807 performs supervisory function by sending out
a reset signal whenever the VDD voltage falls below a
preset threshold level. The timeout period of this reset
signal can be adjusted via an external capacitor. Once
VDD recovers above the threshold level, the reset signal
will be released after a certain delay time. To manually
pull reset signal low, just pull the manual reset input (MR)
below the specified logic-low level.
The RT9807 is available in an SOT-23-5 package.
Ordering Information
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Applications
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Computers
Controllers
Intelligent Instruments
Critical uP and uC Power Monitoring
Portable/Battery-Powered Equipment
Pin Configurations
(TOP VIEW)
RT9807Package Type
B : SOT-23-5
VDD
CT
5
4
Lead Plating System
G : Green (Halogen Free and Pb Free)
Output Voltage
12 : 1.2V
13 : 1.3V
:
32 : 3.2V
33 : 3.3V
Note :
2
RST GND MR
SOT-23-5
Typical Application Circuit
R
470k
Richtek products are :
`RoHS
3
compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable
for use in SnPb or Pb-free soldering processes.
Marking Information
VDD
RT9807
5
1
VDD
RST
CIN
1uF
3
MR
GND
2
CT 4
Reset
CCT
10nF
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
DS9807-01 April 2011
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RT9807
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
RST
Reset Output Pin. (Open drain)
2
GND
Ground Pin.
3
MR
Manual Reset Pin.
4
CT
Connect an external capacitor for setting reset timeout period.
5
VDD
Supply Voltage Input Pin.
Function Block Diagram
N-MOSFET
-
VDD
+
Comparator
VREF
Timeout
Setting
GND
Manual
Reset
MR
Absolute Maximum Ratings
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CT
(Note 1)
Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------Reset Output Voltage, RST --------------------------------------------------------------------------------------------Other Pins ------------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOT-23-5 -------------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOT-23-5, θJA --------------------------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions
z
RST
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
0.4W
250°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
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DS9807-01 April 2011
RT9807
Electrical Characteristics
(TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.9
--
5.5
V
--
3
5
μA
Operating VDD Range
VDD
Supply Current
IDD
Reset Threshold
VTH
1.2
--
3.3
V
Threshold Voltage Accuracy
ΔVTH
−1.5
--
1.5
%
Threshold Voltage Hysteresis
VHYS
--
50 x VTH
--
mV
--
100
--
ppm/°C
VTH = 3V, VDD = 4.5V
Reset Threshold Tempco
VDD Drop to Reset Delay
tRP
Drop = VTH – 250mV
--
100
--
μs
RST Output Voltage Low
(Note 5)
VOL
VDD < VTH(min.), ISINK = 3.5mA
--
--
0.4
V
VIH
0.7VDD
--
--
VIL
--
--
0.25VDD
MR Glitch Rejection
--
80
--
ns
MR to Reset Propagation Delay tMR
--
2
--
μs
MR Pull-up Resistance
RMR
--
20
--
kΩ
Reset Timeout Period
tRP
3.35
4.375
5.40
--
0.275
--
CT Source Current
IRAMP
--
240
--
CT Source Threshold Voltage
VTH-RAMP
--
0.65
--
V
--
33
--
mV
Logic-High
MR Input
Threshold voltage
Logic-Low
CCT = 1500pF
CCT = 0pF
CT Threshold Hysteresis
V
ms
nA
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3
thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. The voltage VOL can be calculated by VOL = VDD - Ir x R. Where R is the pull-up resistor and Ir is the current flowing through
the pull-up resistor. For typical application R = 100kΩ, VOL is less than 0.2V.
DS9807-01 April 2011
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RT9807
Typical Operating Characteristics
Supply Current vs. Input Voltage
CT Threshold Voltage vs. Temperature
6
Supply Current (μA)
5
TA = 125°C
TA = 85°C
TA = 25°C
4
3
TA = −40°C
2
1
CT Threshold Voltage (V)
0.67
0.66
Rising
0.65
0.64
0.63
Falling
0.62
0.61
CT Open
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
R = 470kΩ
0.6
5.5
-50
-25
0
150
100
10
1
VDD = 5V, R = 470kΩ
0.1
1
10
100
VDD Drop Reset Delay Time (μs)
Reset Delay Time (ms)
1000
0.01
75
100
125
VDD = 5V, CT Open, R = 470kΩ
130
110
90
70
50
1000
-50
-25
0
Capacitance (nF)
25
50
75
100
125
Temperature (°C)
Power On Reset Delay Time vs. Temperature
Detector Threshold vs. Temperature
1.7
350
1.65
Rising
1.6
Falling
1.55
1.5
1.45
VDD = 5V, CT Open, R = 470kΩ
1.4
-50
-25
0
25
50
Temperature (°C)
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75
100
125
Power On Reset Delay Time (μs)
Detector Threshold (V)
50
VDD Drop Reset Delay Time vs. Temperature
Reset Delay Time vs Capacitance
10000
0.1
0.001
25
Temperature (°C)
Input Voltage (V)
300
250
200
150
VDD = 5V, CT Open, R = 470kΩ
100
-50
-25
0
25
50
75
100
125
Temperature (°C)
DS9807-01 April 2011
RT9807
Application Information
The RT9807 provides adjustable reset delay time to fit
the need of a variety of μP applications. The reset delay
time of the RT9807 can be adjusted by connecting a
capacitor between the CT pin and GND. The CT capacitor
must fit the need of low-leakage (<10nA), and it is
recommended to use a ceramic capacitor such as X7R or
NPO type.
VCC
0.18 x 106 x CCT (μF)
VDD
RST
GND
CT
R1
CCT
Figure 2. Voltage Divider
When the VDD voltage exceeds the VDD threshold voltage,
a current source will start to charge the CT capacitor and
the CT voltage will rise. When the CT voltage exceeds
0.65V, the RST voltage will change from low to high.
Therefore, there is a delay time between the point of VDD
reaching its threshold voltage and the RST active-high
point. The delay time can be calculated according to the
following equation.
0.58
RT9807
R1
Reset Delay Time Setting
tDELAY (μ s) =
R
The rising and falling of the VCC and RST voltage can be
explained in five steps as shown in the following diagram.
1
2
3
4
5
B
VCC
A
Hysteresis
range
+ 220
VCC_TH
VCC_TH – Hysteresis Voltage
Minimum Operation Voltage
GND
VDD Threshold
Voltage
VDD Voltage
GND
RST Voltage
0.65V
Power-On Reset
Delay Time
VCT
GND
GND
Drop Reset
Delay Time
RST Voltage
Figure 3. Operation Diagram
GND
1. RST voltage is pulled up to VCC voltage.
Delay Time
Figure 1. Delay Time
Operating with a Voltage Divider
The voltage detector monitors the VCC voltage to generate
a reset signal when VCC is higher than the detecting level.
The detecting level is determined by an external resistive
voltage divider.
R1 ⎞
⎛
VCC_TH = VTH x ⎜ 1 +
, VTH : Threshold Voltage.
R2 ⎟⎠
⎝
R1 ⎞
⎛
VCC_HYS = VHYS x ⎜ 1 +
⎟
R2
⎝
⎠
DS9807-01 April 2011
2. When the VCC voltage is down to the detector threshold
voltage (Point A), RST voltage becomes low level.
3. When the VCC voltage is lower than minimum operating
voltage, the RST voltage is indefinite. In the case of
open drain type, RST voltage is equal to pull-up voltage.
4. RST voltage becomes low level.
5. When the VCC voltage exceeds the threshold voltage
(Point B), the internal source current will start to charge
CT capacitor. The RST voltage will go high after a delay
time when the CT capacitor voltage reaches 0.65V.
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RT9807
Interfacing to Other Voltages
TA = 25°C can be calculated by the following formula :
The RT9807 is an open-drain voltage detector that can
provide different voltage level of reset signals for processor
application. As shown in Figure 4, the open-drain output
can be connected to another voltage level less than 5.5V.
This allows for easy logic compatibility to various
microprocessors.
P D(MAX) = (125°C − 25°C) / (250°C/W) = 0.4W for
SOT-23-5 package
5V
0.50
470k
RT9807
RST
RST
VDD
3.3V
1µF
GND
Figure 4
Manual Reset Input
Many processor based products require manual reset
capability, allowing the user or external logic circuitry to
initiate a reset. A logic low on MR asserts reset. Reset
remains asserted while MR is low and for the reset timeout
period after MR returns high. Connect a normally open
momentary switch from MR to ground to create a manual
reset function.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
Maximum Power Dissipation (W)
5V
System
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. For RT9807 package, the derating curve
in Figure 5 allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation.
Single Layer PCB
0.45
0.40
0.35
0.30
0.25
0.20
SOT-23-5
0.15
0.10
0.05
0.00
0
25
50
125
Layout Considerations
CT is a precise current source. When developing the
layout for the application, be careful to minimize board
capacitance and leakage currents around this pin.
Traces connected to CT should be kept as short as
possible. Traces carrying high-speed digital signals and
traces with large voltage potentials should be routed as
far from CT as possible. Leakage current and stray
capacitance (e.g., a scope probe) at this pin can cause
errors in the reset delay time.
R
where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
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100
Figure 5. Derating Curve for RT9807 Package
PD(MAX) = ( TJ(MAX) − TA ) / θJA
For recommended operating conditions specification of
the RT9807, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For SOT-23-5 package, the thermal resistance
θJA is 250°C/W on the standard JEDEC 51-3 single layer
thermal test board. The maximum power dissipation at
75
Ambient Temperature (°C)
RST
1
GND
2
MR
3
5
VDD
CIN
SW
GND
CCT
4
CT
CCT should be placed as
close as possible to the IC.
Figure 6. PCB Layout Guide
DS9807-01 April 2011
RT9807
Outline Dimension
H
D
L
B
C
b
A
A1
e
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.889
1.295
0.035
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.356
0.559
0.014
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-5 Surface Mount Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS9807-01 April 2011
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