RT9730 Charging System Safety Device General Description Features The RT9730 is an integrated circuit (IC) designed to replace passive device in charging system with extra protection function. It is optimized to protect low voltage system from up to 28V high voltage input. The IC monitors the input voltage to make sure all parameters are operating in normal range. It also monitors its own temperature and turns off the MOSFET when the chip temperature exceeds 140°C. When the input voltage exceeds the threshold, the IC turns off the power MOSFET within 1μs to remove the power before any damage occurs. User can monitor the adapter input voltage from the CHRIN pin, which has 50mA current capability. The gate of the P-MOSFET will be controlled by the external charging controller from GATDRV pin if all parameters are operating in normal range. z z z z z z z No External Blocking Diode Requiring μs Over Voltage Turn Off Time of Less Than 1μ High Accuracy Protection Thresholds Over Temperature Protection High Immunity of False Triggering Under Transients Thermal Enhanced 8-Lead WDFN Package RoHS Compliant and Halogen Free Applications z z z z Cellular Phones Digital Cameras PDAs and Smart Phones Portable Instruments Pin Configurations ACIN ACIN GND NC Ordering Information 9 8 7 6 5 OUT OUT CHRIN GATDRV WDFN-8L 2x2 RT9730 Package Type QW : WDFN-8L 2x2 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Marking Information JF= : Product Code JF=W W : Date Code Richtek products are : ` 1 2 3 4 GND (TOP VIEW) The RT9730 is available in a WDFN-8L 2x2 tiny package to achieve best solution for PCB space and total BOM cost saving considerations. RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Typical Application Circuit VIN CIN 1µF SOC RT9730 ACIN CHRIN COUT 1µF GATDRV CHRIN GATEDRV OUT OUT GND 1µF 0.2 VBAT Battery DS9730-01 April 2011 www.richtek.com 1 RT9730 Functional Pin Description Pin No. Pin Name 1, 2 ACIN 3, GND 9 (Exposed pad) Pin Function Input Power Source Pin. It can withstand up to 30V input. Analog Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.. 4 NC No Internal Connection. 5 GATDRV External control pin for controlling the P-MOSFET by charging controller. 6 CHRIN Voltage is equal to VIN as VIN in power good range and providing ≅25mA for system at most. OUT Connect to OUT resistor and OUT pin of charging controller. 7, 8 Function Block Diagram SW ACIN CHRIN Control Logic MUX GATDRV OUT SW GND INOVP www.richtek.com 2 UVLO OTP DS9730-01 April 2011 RT9730 Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VIN -----------------------------------------------------------------------------------------------Output (as VIN > VOUT, normal mode) --------------------------------------------------------------------------------Output (as sleep mode) -------------------------------------------------------------------------------------------------Other Pins ------------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-8L 2x2 -------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-8L 2x2, θJA --------------------------------------------------------------------------------------------------------WDFN-8L 2x2, θJC -------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z −0.3V to 30V −0.3V to 7V −0.3V to 4.5V −0.3V to 6V 0.833W 120°C/W 8.2°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 5V, TA = 25°C, unless otherwise specified) Parameter VIN Under Voltage Lockout Threshold VIN Under Voltage Lockout Hysteresis VIN Bias Current Min Typ Max Unit 2.5 2.7 2.9 V -- 100 -- mV When enable -- 200 600 μA As ACIN floating -- 5 10 μA Operation Voltage 4.3 -- 6.5 V Operation Current -- -- 1 A Input OVP Reference Voltage VINOVP 6 6.25 6.5 V Input OVP Hysteresis -- 60 100 mV Input OVP Propagation Delay -- -- 1 μs OTP Rising Thershold -- 140 -- °C OTP Hysteresis -- 20 -- °C -- -- 500 mΩ -- -- 3 Ω Reverse Leakage Symbol VUVLO Test Conditions VIN Rising ΔVUVLO ILEAKAGE Protections Power MOSFET RDS(ON) Between ACIN to OUT RDS(ON) Between ACIN to CHRIN DS9730-01 April 2011 RDS(ON)_OUT RDS(ON)_CHRIN Measure @ 500mA. 4.3V < VIN < 6V Measure @ 50mA. 4.3V < VIN < 6V www.richtek.com 3 RT9730 Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 4 DS9730-01 April 2011 RT9730 Typical Operating Characteristics CHRIN RDS(ON) vs. Input Voltage 3.0 450 2.8 400 2.6 350 2.4 R DS(ON) (ohm) (Ω) OUT Current (mA) OUT Current vs. GATDRV Voltage 500 300 250 200 150 100 50 0 2.2 2.0 1.8 1.6 1.4 2.5 2.7 2.9 ACIN = 5V, OUT = Open, CHRIN = 50mA, GATDRV = 5V 1.2 ACIN = 4.5V, RLOAD = 9.1Ω 1.0 3.1 3.3 3.5 3.7 2.7 3.1 3.5 OUT RDS(ON) vs. Input Voltage 2.4 2.2 R DS(ON) (Ω) (ohm) (Ω) RDS(ON) (ohm) 0.6 0.5 0.4 0.3 0.2 2.0 1.8 1.6 1.4 1.2 1.0 ACIN = 5V, OUT = 500mA, CHRIN = Open, GATDRV = 0V 2.7 3.1 3.5 ACIN = 5V, OUT = Open, CHRIN = 50mA, GATDRV = 5V 0.8 0.6 3.9 4.3 -40 -25 -10 4.7 5 50 65 80 95 110 125 120 0.6 100 Supply Current (μA) 0.5 R DS(ON) (Ω) (ohm) 35 Supply Current vs. Temperature RDS(ON) vs. Temperature 0.4 0.3 0.2 0 20 Temperature (°C) Input Voltage (V) 0.1 4.7 CHRIN RDS(ON) vs. Temperature 0.7 0 4.3 2.6 0.8 0.1 3.9 Input Voltage (V) GATDRV Voltage (V) 80 60 40 20 ACIN = 5V, OUT = 500mA, CHRIN = Open, GATDRV = 0V -40 -25 -10 5 20 35 50 0 65 80 Temperature (°C) DS9730-01 April 2011 95 110 125 ACIN = 5V, OUT = Open, CHRIN = Open, GATDRV = 5V -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.richtek.com 5 RT9730 Input OVP Propagation Delay OVP vs. Temperature 6.50 CHRIN = 1kΩ, GATDRV = ACIN ACIN 6.25 OVP (V) 6.00 5.75 5.50 5.25 5.00 -40 -25 -10 5 20 35 50 CHRIN (1V/Div) ACIN = 5V, OUT = Open, CHRIN = 1kΩ, GATDRV = 5V 65 80 95 110 125 Time (500ns/Div) Temperature (°C) Input OVP Recovery Delay CHRIN = 1kΩ, GATDRV = ACIN ACIN CHRIN (1V/Div) Time (1μs/Div) www.richtek.com 6 DS9730-01 April 2011 RT9730 Application information Operation State Internal Over Temperature Protection (OTP) The operation state is shown in the following Figure 1. At power-off state, the RT9730 will check whether VIN is > The RT9730 monitors its own internal temperature to prevent thermal failures. When the internal temperature reaches 140°C with a built-in hysteresis of 20°C, the IC turns off the power MOSFET. The IC does not resume operation until the internal temperature drops below 120°C. UVLO threshold. If VIN is higher than the UVLO threshold, the RT9730 will check whether the junction temperature is over the OTP threshold. If the junction temperature is higher than the OTP threshold, the internal P-MOSFET will be turned off. If the junction temperature is lower than the OTP threshold, the RT9730 will check whether VIN is higher than the OVP threshold or not, if VIN is higher than the OVP threshold, the RT9730 will turn off the internal PMOSFET immediately within 1μs. If all of the checks including VIN > UVLO, TJ < OTP and VIN < OVP are ok, the IC will operate normally. Start VIN > UVLO Y TJ > OTP N Power-Off Status Y OTP Status PFET=OFF N VIN > OVP Normal Status N P-MOSFET = ON and Control by GATDRV Y OVP Status P-MOSFET = Off(Fast) Figure 1. Operation State Diagram for OVP Function Input Over Voltage Protection (OVP) The RT9730 monitors the input voltage to prevent abnormally high input voltage from causing output system failures. When the input voltage exceeds the threshold, the RT9730 will turn off the power MOSFET within 1μs to prevent damage to the electronics in the handheld system. The hysteresis for the input OVP threshold is 100mV. When the input voltage returns to normal operation voltage range, the RT9730 re-enables the MOSFET. The RT9730 can with stand an input voltage up to 30V without suffering damage. Input Under Voltage Protection (UVLO) The RT9730 monitors input voltage to prevent abnormally low input voltage from causing output system failures. The RT9730 input under voltage protection threshold is set to 2.7V. When the input voltage is under the threshold, the RT9730 will turn off the power MOSFET within 1μs. When the input voltage returns to normal operation voltage range, the RT9730 re-enables the MOSFET. System Operation Description Figure 2 shows the connection of RT9730 in a system diagram. The OUT pin of the SOC will sense the voltage of the 0.2Ω sense resistor and the voltage of the VBAT pin. Then, the GATDRV pin of the SOC can control the MOSFET of the RT9730 accordingly to determine the level of the charge current. The power of the SOC is provided by the CHRIN pin of the RT9730. The RT9730 also provides OVP function to the SOC. Once the input voltage at the ACIN pin is higher than the OVP level, the RT9730 will shutdown to prevent the SOC from damage. If the voltage of the battery connected to the VBAT pin is full, the RT9730 stops charging by turning off the OUT pin. Input and output capacitors of 1μF are recommended to be placed as close to the IC as possible. RT9730 CHRIN VIN DS9730-01 April 2011 COUT 1µF ACIN CIN 1µF GATDRV Battery Voltage Monitor The RT9730 monitors the battery voltage by the OUT pin. When the battery voltage exceeds the voltage level of (VIN − 0.2V), the RT9730 will turn off the MOSFET and the battery will not be charged. The RT9730 will recharge the battery when the battery voltage is lower than the voltage level of (VIN − 0.2V). SOC CHRIN GATEDRV OUT OUT GND 1µF 0.2 VBAT Battery Figure 2. Application Diagram of RT9730 with SOC www.richtek.com 7 RT9730 Thermal Considerations Layout Consideration For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : The RT9730 is a protection device. Careful PCB layout is necessary. For best performance, place all peripheral components as close to the IC as possible. A short connection is highly recommended. The following guidelines should be strictly followed when designing a PCB layout for the RT9730. ` The exposed pad, GND, must be soldered to a large ground plane for heat sinking and noise prevention. The through-hole vias located at the exposed pad is connected to the ground plane of internal layer. ` ACIN traces should be wide to minimize inductance and handle the high currents. The trace running from input to chip should be placed carefully and shielded strictly. ` The capacitors must be placed close to the part. The connection between pins and capacitor pads should be copper traces without any through-hole via connection. PD(MAX) = (TJ(MAX) − TA) / θJA For recommended operating condition specifications of the RT9730, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WDFN8L 2x2 packages, the thermal resistance, θ JA , is 120°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for WDFN-8L 2x2 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT9730 package, the derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W) 0.9 From Adapter ACIN ACIN CIN GND NC 1 2 3 4 GND where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. 9 8 7 6 5 OUT OUT CHRIN GATDRV To Baseband Gate Controller To Battery To Baseband Charger Controller GND Input capacitor must be placed between GND and ACIN to reduce noise. The exposed pad and GND should be connected to a strong ground plane for heat sinking and noise prevention. The capacitor must be placed between GND and CHRIN to reduce noise. Figure 4. PCB Layout Guide Four-Layer PCB 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curves for RT9730 Packages www.richtek.com 8 DS9730-01 April 2011 RT9730 Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 1.950 2.050 0.077 0.081 D2 1.000 1.250 0.039 0.049 E 1.950 2.050 0.077 0.081 E2 0.400 0.650 0.016 0.026 e L 0.500 0.300 0.020 0.400 0.012 0.016 W-Type 8L DFN 2x2 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9730-01 April 2011 www.richtek.com 9