RT9941 Power Management ICs for Handheld Device General Description Features The RT9941 is a complete power management IC (PMIC) for handheld device platform. This PMIC contains a fully integrated linear charger for a single cell Lithium Ion battery, five LDO linear regulators and two high efficiency buck converters, a comparator, a reset and an I2C serial interface z The linear charger integrates LDO, MOSFET pass element and thermal-regulation circuitry. The proprietary thermalregulation circuitry limits the die temperature when fast charging or while exposed to high ambient temperatures, allowing maximum charging current without damaging the IC. z z The LDO linear regulators provide high power supply rejection rate and have only 45μVRMS of output noises for 100Hz to 10kHz frequency range to power noise sensitive RF sections. The RT9941 is available in WQFN-40L 5x5 package. Ordering Information RT9941 z Package Type QW : WQFN-40L 5x5 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : ` ` Adapter & Battery Two Input with Auto Power Dynamic Path. ` PWR_IN LDO support continuous 1.5A, peak 2A current ` 4.5V to 5.5V Operation Voltage Range with Max. Input 18V from PWR_IN Pin ` Switch Well for LDO and Charger Power MOSFET ` Set Charge Current by ISETA Pin ` Charge Status Indicator ` Interrupt for PWR_IN Plug In/Out Time Out and Charger Done. ` Battery Temperature Monitoring Hysteretic Buck ` Buck 1 for DDR Memory, Adjustable Voltage and 600mA Output Current 2 ` Buck 2 for PDN with 25mV/step I C Adjustable 800mA Output Current ` Max. Efficiency Up to 90% LDO ` LDO1 : 3.3V/500mA for I/O, Default ON ` LDO2 : 1.2V/80mA for PLL, Default ON 2 ` LDO3 : 1.2V/80mA for Pre-Core. I C Adiustable, Sync. with Buck2, Default ON ` LDO4 : 2.5V/50mA for AVDD of USB, ADC, TSC, Default ON ` LDO5 : 3.3V/50mA for AVDD of USB, Default ON ` Minimize the External Component Counts Other ` System Reset ` Low Voltage Detector 2 ` I C Compatible Interface ` Power ON Timing Control RoHS Compliant and Halogen Free ` to program one buck and one regulator output voltages as well as power on timing control for complete flexibility. The two step-down converters are optimized for small size inductor and high efficiency applications. They utilize a proprietary hysteretic PWM control scheme that switches with nearly fixed frequency and is adjustable, allowing the customer to trade some efficiency for smaller external component as desired. Charger z RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Applications Suitable for use in SnPb or Pb-free soldering processes. z z DS9941-01 April 2011 GPS and PDA Handheld Devices www.richtek.com 1 RT9941 Pin Configurations PWR_HOLD CLK PWR_ON HP_PWR VSYS VSYS PWR_ID PWR_IN PWR_IN ISETU (TOP VIEW) 40 39 38 37 36 35 34 33 32 31 nCHG_S ISETA TS TIMER VOUT2 VIN3 VOUT3 VOUT1 VIN2 VOUT4 1 30 2 29 3 28 4 27 5 26 GND 6 25 7 24 8 23 41 9 22 21 10 DATA BATT BATT FB1 PGND1 LX1 VIN1 LX2 PGND2 FB2 PWR_EN S1 GND S2 nLBO LBI nRESET nINT VOUT5 nPBSTAS 11 12 13 14 15 16 17 18 19 20 WQFN-40L 5x5 Typical Application Circuit RT9941 LDO1 (S1 and S2 Control) 500mA 8 VOUT1 1µF LDO2 (S1 and S2 Control) 200mA 5 VOUT2 1µF 7 LDO3 80mA 1µF 1µF LDO5 (I2C Control) 50mA 11 VOUT5 1µF 35, 36 VSYS To VIN1, VIN2, VIN3 22µF 28, 29 + 200k BATT 4.7µF LX2 23 100mA From CPU, uP USB Adapter www.richtek.com 2 220pF 100k PGND2 22 VIN1 24 3 TS 2 ISETA 4 C TIMER 0.1µF 510 TIMER VSYS 10µF VSYS GND 6 4.7µF 16 LBI nRESET 13 nINT 100k 32 PWR_HOLD 40 ISETU 18 S2 19 S1 20 PWR_EN 37 PWR_ID VSYS 17, Exposed Pad (41) nPBSTAS 12 1 nCHG_S 100k VIN3 100k 100k 14 39k 500mA V BUCK2 1.2V/600mA 4.7µF 10µF R SET 2k (750mA) V BACK1 L2 2.2µH FB2 21 NTC VSYS 120pF PGND1 26 VIN2 9 VSYS V BUCK1 1.8V/600mA 4.7µF 100k 100k 38, 39 PWR_IN +5V (Adapter / USB) L1 2.2µH FB1 27 VOUT3 10 VOUT4 LDO4 (I2C Control) 50mA LX1 25 nLBO 15 DATA 30 CLK 31 100k 100k 4.7k 4.7k VSYS V BACK1 VSYS VSYS VSYS VSYS PWR_ON 33 VSYS HP_PWR 34 RTC Alarm Wake Up DS9941-01 April 2011 RT9941 Functional Pin Description Pin No. Pin Name 1 nCHG_S 2 ISETA Pin Function This pin indicates the status of the battery charger. Open Drain Output and Active Low. PWR_IN Charge Current Setting Pin. 3 TS Temperature Sense Pin. 4 TIMER Charge Time Setting. 5 VOUT2 6 VIN3 7 VOUT3 1.2V/80mA LDO regulator. This pin must be shorted to VSYS, VIN1 and VIN2. Connect a 4.7μF ceramic capacitor from VIN3 to GND. 1.2V/80mA LDO Regulator with 25mV/Step Adjustable. 8 VOUT1 9 VIN2 10 VOUT4 11 VOUT5 12 nPBSTAS 13 nRESET 14 nINT 15 nLBO 16 LBI 3.3V/500mA LDO Regulator. Must be shorted to VSYS, VIN1 and VIN3. Connect a 10μF ceramic capacitor from VIN2 to GND. 2.5V/50mA LDO Regulator. 18 S2 19 S1 20 PWR_EN 3.3V/50mA LDO Regulator. Push-Button Status Pin. This pin is used to inform the power good state to processor. Open Drain Output and Active Low. This pin provides a 200ms reset signal during power-up to initialize a processor. Open Drain and Active Low. This pin must be Active Low to inform processor the interrupt events happened, Open Drain Output and Active Low. Low-Battery indication. Open Drain Output and Active Low. Low-Battery Detection. This pin is used to monitor the VSYS Voltage and the internal reference voltage is 1V Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. LDO1 & LDO2 Output Voltage Setting, Directly Connect VSYS to Pull High, GND to Pull Low. LDO1 & LDO2 Output Voltage Setting, Directly Connect VSYS to Pull High, GND to Pull Low. Buck2 & LDO2 Enable Pin from Processor. 21 FB2 Voltage Feedback2. FB2 Regulates to 0.6V nominal. 22 PGND2 Buck 2’s Power Ground. 23 LX2 24 VIN1 25 LX1 Inductor Connection to the Drains of the Internal N- MOSFETs and P-MOSFETs. This pin must be shorted to VSYS, VIN2, and VIN3. Connect a 10μF ceramic capacitor from VIN1 to GND. Inductor Connection to the Drains of the Internal N-MOSFETs and P-MOSFETs. 26 PGND1 Buck 1’s Power Ground. 27 FB1 Voltage Feedback1. FB1 Regulates to 0.6V Nominal. 17, GND 41 (Exposed Pad) 28,29 BATT 30 DATA Main Battery Supply Input Terminal. This pin delivers charging current and monitors battery voltage. Data Input/output for Serial Interface. 31 CLK Clock Input for Serial Interface. 32 PWR_HOLD Logic Low Signal from Processor to Turn Off the PMU. To be continued DS9941-01 April 2011 www.richtek.com 3 RT9941 Functional Pin Description Pin No. Pin Name 33 PWR_ON 34 HP_PWR 35,36 Pin Function Active High Power On / Off Key Input. This pin has an Internal 2μA Pull-Down Current to GND. When the push button is closed, It Is shorted to SYS, not Ground. This input is de-bounced with 320ms (typ). Logic High Signals Connection of Hands Free Kit. This Pin Has an Internal 2μA Pull-Down Current to GND. This Input is De-bounced with 320ms (typ). Connect this pin to System with a minimum 22μF ceramic capacitor to GND. This pin must be shorted to VIN1, VIN2, and VIN3 VSYS 37 PWR_ID Power Source Input Detection Pin. 38,39 PWR_IN Power Source Input. Connect a 4.7μF Ceramic Capacitor from this pin to GND. ISETU USB Charge Current Setting Pin. 40 Function Block Diagram PWR_ID PWR_IN Control Circuit SW VSYS BATT S2 S1 VIN1 LX1 Buck1 ISETU ISETA TS TIMER nCHG_S Li-lon Linear Charger Control PGND1 FB1 UVLO Thermal Shutdown nRESET Reset nPBSTAS LX2 PWR_ON HP_PWR 2µA 2µA 320ms Debounce Buck2 320ms Debounce ON/OFF 2 Control & I C Interface Buck1 OK PWR_HOLD nLBO VSYS + LDO1 VOUT1 LDO2 VOUT2 LDO3 VOUT3 LDO4 VOUT4 VIN2 VOUT5 LDO5 LBI www.richtek.com 4 FB2 PWR_EN VIN3 1V - nINT DATA CLK PGND2 GND DS9941-01 April 2011 RT9941 Absolute Maximum Ratings z z z z z z z z z z z z z z (Note 1) PWR_IN ---------------------------------------------------------------------------------------------------- 0V to 7V PWR_HOLD, PWR_ON, HP_PWR, DATA, CLK, nCHG_S, ISETA, TS, TIMER, nPBSTAS, nRESET, nINT, nLBO, LBI, S2, PWR_EN, PWR_ID ------------------------------ −0.3V to VSYS + 0.3V FB2, FB1, LX2, LX1 -------------------------------------------------------------------------------------- −0.3V to VIN1 + 0.3V VOUT2, VOUT3 ------------------------------------------------------------------------------------------- −0.3V to VIN3 + 0.3V VOUT1, VOUT4, VOUT5 ------------------------------------------------------------------------------- −0.3V to VIN2 + 0.3V VIN1, VIN2, VIN3 ----------------------------------------------------------------------------------------- VSYS−0.3V to VSYS + 0.3V BATT, VSYS ----------------------------------------------------------------------------------------------- 0V to 5.5V ISETU ------------------------------------------------------------------------------------------------------- −0.3V to PWR_IN + 0.3V ≤ 6V Power Dissipation, PD @ TA = 25°C WQFN-40L 5x5 ------------------------------------------------------------------------------------------- 2.778W Package Thermal Resistance (Note 2) WQFN-40L 5x5, θJA -------------------------------------------------------------------------------------- 36°C/W WQFN-40L 5x5, θJC ------------------------------------------------------------------------------------- 7°C/W Junction Temperature ------------------------------------------------------------------------------------ 150°C Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------- 260°C Storage Temperature Range --------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV MM (Machine Mode) ------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z (Note 4) Junction Temperature Range --------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------- −40°C to 85°C Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. To be continued DS9941-01 April 2011 www.richtek.com 5 RT9941 Electrical Characteristics Electrical Characteristics (General) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit 3.3 -- 5.5 V System Operating Range Input Supply Voltage VIN Without PWR_IN Shutdown Supply Current ISHDN VBATT = 4.2V, VOUT1 to 5, LX1, LX2 to ground. 4 10 15 μA VBATT = 3.7V, PWR_EN = L, Only Buck1, LDO1, LDO3 Turn On -- 120 200 μA VBATT = 3.7V -- 100 -- μA VSYS Rising -- 3.2 -- V VSYS Falling -- 2.5 -- V Threshold -- 160 -- °C Hystersis -- 10 -- °C Sleep Mode Supply Current Deep Sleep Mode Supply Current System Voltage Lockout Under Voltage Lockout Thermal Shutdown Logic and Control Inputs Input Low Level PWR_HOLD, PWR_ON, HP_PWR, DATA, CLK, PWR_EN, PWR_ID -- -- 0.4 V Input High Level PWR_HOLD, PWR_ON, HP_PWR, DATA, CLK, PWR_EN, PWR_ID 1.5 -- -- V PWR_HOLD, DATA, CLK, PWR_EN −1 -- 1 μA PWR_ON = 0.4V -- 2 -- μA HP_PWR = 0.4V -- 2 -- μA -- 320 -- ms -- 65 -- mV Input Current PWR_ON Pull-down Current to GND HP_PWR Pull-down Current to GND PWR_ON, HP_PWR De-bounce Filter nINT, nPBSTAS, nRESET, nLBO Pull Down Voltage www.richtek.com 6 Source Current = 5mA DS9941-01 April 2011 RT9941 Electrical Characteristics (Buck Converter 1) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Output Adjustable Range Typ 0.6 FB Threshold Voltage VFB1 Falling FB1 Threshold Line Regulation VIN = 2.7V to 5.5V ILIM On-Resistance Max Unit 2.5 V 0.582 0.6 0.618 V -- 1.5 -- %/V -- 12 -- mV P-MOSFET Switch 1000 1500 2000 N-MOSFET Switch -- 700 -- P-MOSFET Switch, ILX = −40mA -- 0.3 -- N-MOSFET Switch, ILX = 40mA -- 0.38 -- -- 30 -- mA Min Typ Max Unit VREF -- 2.5 V 0.582 0.6 0.618 V -- 1.5 -- %/V -- 12 -- mV P-MOSFET Switch 1000 1500 2000 N-MOSFET Switch -- 700 -- P-MOSFET Switch, ILX = −40mA -- 0.4 -- N-MOSFET Switch, ILX = 40mA -- 0.4 -- -- 30 -- mA 0.5 -- 0.7 V -- 12.5 -- mV FB1 Threshold Voltage Hysteresis Current Limit Min Rectifier Off Current Threshold mA Ω Electrical Characteristics (Buck Converter 2) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Output Adjustable Range Default FB2 Threshold Voltage VFB2 Falling FB2 Threshold Line Regulation VIN = 2.7V to 5.5V FB2 Threshold Voltage Hysteresis Current Limit On-Resistance ILIM Rectifier Off Current Threshold Programmable FB2 Voltage Each Programmable FB2 Voltage Step DS9941-01 April 2011 V FB2 Falling mA Ω www.richtek.com 7 RT9941 Electrical Characteristics (VOUT1 (LDO1) ) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions lLOAD = 200mA & VIN = 3.7V Min Typ Max Unit 3.201 3.3 3.399 V -- -- 200 mA Output Voltage V OUT1 Output Current IOUT Current Limit ILIM V OUT1 = 0V -- 500 850 mA Dropout Voltage V DROP lLOAD = 200mA -- 150 -- mV Line Regulation V OUT1 + 0.4V ≤ VBATT = VIN1 ≤ 5.5V, ILOAD = 200mA -- 2.4 -- mV Load Regulation V IN1 = 3.7V, 50μA < ILOAD < 200mA -- 25 -- mV Power Supply Rejection. ΔVOUT/ΔV IN F = 10Hz − 10kHz, C OUT = 1μF, V OUT > 2.5V, ILOAD = 30mA -- 60 -- dB Min Typ Max Unit 1.164 1.2 1.236 V -- -- 80 mA VOUT2 = 0V -- 400 -- mA Line Regulation VOUT2 + 0.4V ≤ V BATT = VIN1 ≤ 5.5V, lLOAD = 80mA -- 2.4 -- mV Load Regulation VIN1 = 3.7V, 50μA < lLOAD < 80mA -- 25 -- mV Power Supply Rejection. ΔVOUT/ΔV IN F = 10Hz − 10kHz ,C OUT = 1μF lLOAD = 30mA -- 60 -- dB Min Typ Max Unit 1.164 1.2 1.236 V -- -- 80 mA VOUT3 = 0V -- 400 -- mA Line Regulation VOUT3 + 0.4V ≤ VBATT = VIN1 ≤ 5.5V, lLOAD = 80mA -- 2.4 -- mV Load Regulation 50μA < lLOAD < 80mA -- 25 -- mV Power Supply Rejection. ΔVOUT/ΔVIN F = 1kHz ,COUT = 1μF lLOAD = 30mA -- 60 -- dB Note : All output capacitors are ceramic and X7R/X5R type. Electrical Characteristics (VOUT2 (LDO2) ) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Output Voltage VOUT2 Output Current IOUT Current Limit ILIM Conditions lLOAD = 80mA & VIN = 3.7V Note : All output capacitors are ceramic and X7R/X5R type. Electrical Characteristics (VOUT3 (LDO3) ) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Output Voltage VOUT3 Output Current I OUT Current Limit I LIM Conditions lLOAD = 80mA & VIN = 3.7 V Note : All output capacitors are ceramic and X7R/X5R type. www.richtek.com 8 DS9941-01 April 2011 RT9941 Electrical Characteristics (VOUT4 (LDO4) ) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit 2.425 2.5 2.575 V -- -- 50 mA Output Voltage VOUT4 Output Current IOUT Current Limit ILIM VOUT4 = 0V -- 400 -- mA Dropout Voltage VDROP lLOAD = 50mA -- 50 -- mV Line Regulation VOUT4 + 0.4V ≤ VBATT = VIN1 ≤ 5.5V, lLOAD = 50mA -- 2.4 -- mV Load Regulation 50μA < lLOAD < 50mA -- 25 -- mV Power Supply Rejection. ΔVOUT/ΔVIN F = 1kHz , COUT = 1μF, lLOAD = 30mA -- 60 -- dB Min Typ Max Unit 3.201 3.3 3.399 V -- -- 50 mA lLOAD = 50mA & VIN = 3.7 V Note : All output capacitors are ceramic and X7R/X5R type. Electrical Characteristics (VOUT5 (LDO5) ) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Output Voltage VOUT5 Output Current IOUT Current Limit ILIM VOUT5 = 0V -- 400 -- mA Dropout Voltage VDROP lLOAD = 50mA -- 50 -- mV Line Regulation VOUT5 + 0.4V ≤ VBATT = VIN1 ≤ 5.5V, lLOAD = 50mA -- 2.4 -- mV Load Regulation 50μA < lLOAD < 50mA -- 25 -- mV Power Supply Rejection. ΔVOUT/ΔVIN F = 1kHz, C OUT = 1μF, lLOAD = 30mA -- 60 -- dB lLOAD = 50mA & VIN = 3.7 V Note :All output capacitors are ceramic and X7R/X5R type. DS9941-01 April 2011 www.richtek.com 9 RT9941 Electrical Characteristics (Li-Ion Charger) (VPWR_IN = 5V, VBATT = 4V, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit 4.5 -- 5.5 V -- -- 100 μA Input Voltage Range and Input Current PWR_IN Input Operation Voltage Range PWR_ID Current ISETU Pull High Current ISETU = 0V -- 0.5 -- μA PWR_IN Standby Current VBATT = 4.2V -- 300 500 μA PWR_IN UVP Current VPWR_IN = 4V, VBATT = 3V -- 150 250 μA -- 3.7 -- V ISETU = H -- 450 500 ISETU = L -- -- 100 PWR_ID = L -- 2300 -- IBATT = 60mA 4.158 4.2 4.242 V 4.8 5 5.2 V -- 350 -- mΩ -- -- 150 mΩ VPWR_IN − V BATT -- 150 -- mV VBATT = 3.5V -- 2.5 -- V 100 -- 1200 mA PWR_IN UVP Voltage PWR_IN Current Limit PWR_ID = H mA Voltage Regulation BATT Regulation Voltage System Regulation Voltage PWR_IN Power FET RDS(ON) System to Battery RDS(ON) PWR_IN to SYS Switch Turn On Current Regulation ISETA Set Voltage (Fast Charge Phase) Full Charge Setting Range IAC = 1A Timer TIMER Pin Source Current VTIMER = 2V -- 1 -- μA Pre-charge Fault Time CTIME R = 0.1μF -- 2460 -- s Charge Fault Time CTIMER = 0.1μF -- 19700 -- s -- 2.8 -- V -- 100 -- mV Precharge BATT Pre-Charge Threshold BATT Pre-Charge Threshold Hysteresis Pre-Charge Current VBATT < Batt Pre-charge Threshold -- 10 -- % Recharge Threshold BATT Re-Charge Falling Threshold Hysteresis VREG − VBATT -- 100 -- mV ISETA Pin Voltage -- 250 -- mV I/nCHG_S = 5mA -- 300 -- mV Charge Termination Detection Termination Current Ratio (default) Logic Input/Output nCHG_S Pull Down Voltage To be continued www.richtek.com 10 DS9941-01 April 2011 RT9941 Parameter Symbol Conditions Min Typ Max Unit -- 125 -- °C 94 100 106 μA 2.45 2.5 2.55 V 0.485 0.5 0.515 V Min Typ Max Unit Protection Thermal Regulation TS Pin Source Current TS Pin Low Threshold Voltage TS Pin High Threshold Voltage V TS = 1.5V Electrical Characteristics (RESET & Low Battery) (VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions nRESET Threshold With respect to Buck2, Rising -- 87 -- % nRESET Active Time-out Period From Buck2 ≥ 87% until RESET = High -- 200 -- ms LBI Reference Voltage Falling -- 1 -- V LBI Hysteresis -- 50 -- mV LBI Leakage Current −1 -- 1 μA DS9941-01 April 2011 www.richtek.com 11 RT9941 Typical Operating Characteristics Buck2 Efficiency vs. Output Current 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Buck1 Efficiency vs. Output Current 100 60 VBATT=3.2V VBATT=3.6V VBATT=4V 50 40 30 20 60 50 40 VBATT=3.2V VBATT=3.6V VBATT=4V 30 20 10 10 VBuck1 = 1.8V 0 0.001 0.01 0.1 VBuck2 = 1.2V 0 0.001 1 0.01 Output Current (A) Buck1 Load Regulation 1.9 1 Buck2 Load Regulation 1.32 VBuck1 = 1.8V VBuck2 = 1.35V 1.29 Output Voltage (V) 1.86 Output Voltage (V) 0.1 Output Current (A) 1.82 VBATT = 4V 1.78 VBATT = 3.6V 1.74 1.7 1.26 1.23 VBATT = 4V 1.2 VBATT = 3.6V 1.17 1.14 1.11 1.66 1.08 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 Output Current (A) 0.2 0.3 0.4 0.5 0.6 Output Current (A) Power On VBuck1, VBuck2, VLDO1, VLDO2 Power On VPWR_EN, VLDO2, VLDO4, VLDO5 VPWR_EN (5V/Div) VLDO2 (2V/Div) VLDO3 (1V/Div) VBuck2 (1V/Div) VLDO1 (500mV/Div) VLDO4 (200mV/Div) VBuck1 (2V/Div) VLDO5 (200mV/Div) VBATT = 4V Time (50μs/Div) www.richtek.com 12 0.1 VBATT = 4V Time (50μs/Div) DS9941-01 April 2011 RT9941 I2C Power On LDO4, LDO5 Power On nRESET Response CLK (5V/Div) VPWR_EN (2V/Div) DATA (5V/Div) LDO4 (2V/Div) nRESET (5V/Div) VBATT = 4V LDO5 (2V/Div) VBATT = 4V Time (50ms/Div) Time (25μs/Div) I2C Power Off LDO4, LDO5 Normal to Sleep Mode CLK (5V/Div) VPWR_EN (1V/Div) DATE (5V/Div) VBuck2 (1V/Div) LDO4 (2V/Div) VLDO2 (1V/Div) LDO5 (2V/Div) VBATT = 4V VBATT = 4V Time (25μs/Div) Time (10ms/Div) Normal to Deep Sleep Mode Buck1 Output Voltage Ripple DATA (5V/Div) VBATT = 4V, IOUT = 500mA VBuck1 (2V/Div) VBuck2 (5V/Div) VLX1 (2V/Div) VLDO1 5V/Div) VLDO2 (2V/Div) VBuck1 (20mV/Div) VLDO3 (2V/Div) VLDO4 (5V/Div) VLDO5 5V/Div) VBATT = 4V Time (100μs/Div) DS9941-01 April 2011 ILX1 (500mA/Div) Time (500ns/Div) www.richtek.com 13 RT9941 Buck2 Output Voltage Ripple Buck1 Load Transient Response VBATT = 4V, IOUT = 500mA VBATT = 4V, IOUT = 0.1A to 0.6A VBuck1 (50mV/Div) VLX2 (2V/Div) VBuck2 (20mV/Div) ILX2 (500mA/Div) I Buck1 (200mA/Div) Time (500ns/Div) Time (250μs/Div) Buck2 Load Transient Response Buck Frequency vs. Input Voltage 2.5 VBATT = 4V, IOUT = 0.1A to 0.6A Buck1 2.25 VBuck2 (50mV/Div) Frequency (MHz)1 2 1.75 Buck2 1.5 1.25 1 0.75 0.5 I Buck2 (200mA/Div) 0.25 IBuck1 = IBuck2 = 200mA 0 Time (250μs/Div) 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 Input Voltage (V) LDO1 Load Transient Response LDO1 Load Regulation 3.36 VBATT = 4V, IOUT = 50mA to 500mA VLDO1 (50mV/Div) VBATT = 3.8V Output Voltage (V) 3.34 3.32 3.3 3.28 I LDO1 (200mA/Div) 3.26 Time (100μs/Div) 0 0.04 0.08 0.12 0.16 0.2 Output Current (A) www.richtek.com 14 DS9941-01 April 2011 RT9941 LDO1 Dropout Voltage vs. Temperature ILDO1 = ILDO2 = ILDO3 = -10 ILDO4 = ILDO5 = 30mA 120 -20 100 -30 PSRR (dB) Dropout Voltage (mV) LDO PSRR 0 140 80 60 -40 -50 LDO1 LDO2 LDO3 LDO4 LDO5 -60 -70 40 -80 20 -90 IOUT1 = 200mA 0 -40 -15 10 35 60 -100 100 85 1,000 Charge Current vs. RISETA Charge Current vs. BATT Voltage 1200 1200 PWRID = L, RISETA = 1.5kΩ VPWRIN = 5V, VBATT = 4V, PWRID = L PWRIN = 5V 1000 Charge Current (mA) 1000 Charge Current (mA) 100,000 Frequency (Hz) Temperature (°C) 800 PWRIN = 4.5V 600 400 800 600 400 200 200 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 VBATT (V) IBATT (2A/Div) 3 4.5 6 7.5 9 10.5 12 13.5 15 Charger Power Path at USB Mode IBATT IPWRIN VSYS VPWRIN ISYS VPWRIN = 5V, VBATT = 4V, PWRID = L, ISYS = 0 to 2.4A Time (1ms/Div) ISYS = 0 to 2.4A VBATT VBATT DS9941-01 April 2011 1.5 RISETA (kΩ) (kΩ) Charger Power Path at AC Mode I PWRIN (2A/Div) VBATT (2V/Div) V SYS (2V/Div) I SYS (2A/Div) V PWRIN (2V/Div) 10,000 I PWRIN (2A/Div) VBATT (2V/Div) I SYS (2A/Div) V PWRIN (2V/Div) IBATT (2A/Div) V SYS (2V/Div) IPWRIN ISYS VPWRIN VSYS IBATT VPWRIN = 5V, VBATT = 4V, PWRID = H, USBID = H Time (1ms/Div) www.richtek.com 15 RT9941 PWRIN Insert Response IBATT (2A/Div) I PWRIN (2A/Div) PWRIN Remove Response IBATT (2A/Div) IBATT IPWRIN I PWRIN (2A/Div) VBATT VSYS IPWRIN VBATT VSYS VBATT (2V/Div) VBATT (2V/Div) V SYS (2V/Div) V PWRIN (2V/Div) V SYS (2V/Div) V PWRIN (2V/Div) VPWRIN VPWRIN = 5V, VBATT = 3.8V, PWRID = L Time (1ms/Div) www.richtek.com 16 IBATT VPWRIN VPWRIN = 5V, VBATT = 3.8V, PWRID = L Time (250ms/Div) DS9941-01 April 2011 RT9941 Application Information I2C Start and Stop Conditions Both DATA and CLK remain high when the bus is not busy. A high-to-low transition of DATA, while CLK is high is defined as the Start condition. A low-to-high transition of the data line while CLK is high is defined as the Stop condition. I2C Acknowledge The number of data bytes between the start and stop conditions for the Transmitter and Receiver are unlimited. Each 8bit byte is followed by an Acknowledge Bit. The Acknowledge Bit is a high level signal put on DATA by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an Acknowledge after each byte it receives. Also a master receiver must generate an Acknowledge after each byte it receives that has been clocked out of the slave transmitter. The device that Acknowledges must pull down the DATA line during the acknowledge clock pulse, so that the DATA line is stable low during the high period of the Acknowledge clock pulse (set-up and hold times must also be met). A master receiver must signal an end of data to the transmitter by not generating an acknowledge signal on the last byte that has been clocked out of the slave. In this case, the transmitter must leave DATA high to enable the master to generate a stop condition. I2C System Configuration A device on the I2C Bus which generates a “message” is called a “Transmitter” and a device that receives the message is a “Receiver”. The device that controls the message is the “Master” and the devices that are controlled by the “Master” are called “Slaves”. I2C Write Command. The RT9941 writing address set 9C hex and write command and data to set internal register. TYPE I : Send the address and one command by I2C (Figure 3). SCL A6 SDA A5 A0 W A 0 Dx4 Dx0 A 01 or 10 or 11 START Write command Acknowledge from the master. from the slave. Acknowledge STOP from the slave. START command from the master. Figure 1. I2C Transmission Flow in the RT9941 VSYS Processor RT9941 SCL SDA SDO Master Slave Figure 2. I2C Function Block in the RT9941 DS9941-01 April 2011 www.richtek.com 17 RT9941 Address START W A6 A5 A4 A3 A2 A1 A0 The 2nd Word 9 0 0 0 1 D14 D13 D12 D11 D10 0 1 0 0 1 1 D34 D33 D32 D31 D30 D24 D23 D22 D21 D20 STOP Figure 3. I2C One Command Flow in the RT9941 Table 1. Register Mapping Table (Underline is default) D1 D2 D3 Bit7 Bit6 Bit5 Bit4 Bit3 0 0 0 0 0 LDO5 LDO4 0 0 0 1 0 1 Bit2 Bit0 Select Group DS_RDY 0 1 0 1 0 OFF ON OFF ON None 1 Bit1 1 PWR_DS[1] 0 Reserved 1 0 Deep Sleep Enter to Power on Recognition Deep Sleep VPROG for LDO5 VPROG for LDO5 VPROG for LDO4 VPROG for LDO4 Z51 Z50 Z41 Z40 VPROG for Buck2, and LDO3 VPROG for Buck2, and LDO3 V4 V3 Charger ON/OFF 0 1 0 1 OFF ON VPROG for VPROG for VPROG for Buck2, and Buck2, and Buck2, and LDO3 LDO3 LDO3 V2 V1 V0 V4 V3 V2 V1 V0 LDO3 Output Voltage (V) Buck2 FB Voltage (V) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X[3] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 1.0 1.025 1.05 1.075 1.1 1.125 1.15 1.175 1.2 (Default) 1.225 1.25 1.275 1.3 1.325 1.35 1.375 1.4 0.5 0.5125 0.525 0.5375 0.55 0.5625 0.575 0.5875 0.6 (Default) 0.6125 0.625 0.6375 0.65 0.6625 0.675 0.6875 0.7 Note a : To enter deep sleep mode, DS_RDY and PWR_DS need to be set. Note b : If Charger ON/OFF is “0”, the charger will suspend in any external condition until this bit is “1”. Note c : “X” means don’t care www.richtek.com 18 DS9941-01 April 2011 RT9941 Z41 Z40 0 0 1 1 0 1 0 1 LDO4 Output Voltage (V) 1.8 2.5 (Default) 2.85 3.3 Z51 Z50 LDO5 Output Voltage (V) 0 0 1.2 0 1 1.5 1 0 3.0 1 1 3.3 (Default) 2 TYPE II : Send address and two commands by I C (Figure 4). 2 I C Address W A6 A5 A4 A3 A2 A1 A0 0 START 9 The 2nd Word 0 0 0 x x G2 G1 G0 18 The 3rd Word G2:0 = 3'b000 0 1 E15 E14 E13 E12 E11 E10 1 0 E25 E24 E23 E22 E21 E20 27 STOP STOP Figure 4. I2C Two Commands Flow in the RT9941 Group 0 (Bit2 = 0, Bit1 = 0, Bit0 = 0) E1 E2 Bit7 Bit6 0 1 1 Bit5 LDO3 0 OFF 0 Bit4 LDO2 1 ON 0 OFF 1 ON PWR_IN IN PWR_IN OUT 0 1 None Mask 0 None 1 Mask Bit3 LDO1 0 1 OFF ON PWR_ID Bit2 Buck1 0 OFF Bit1 Buck2 1 ON 0 OFF Reserved 1 ON TIME OUT 0 1 0 1 None Mask (Keep this bit =1) None 1 Mask Bit0 PWR_EN 0 1 None Mask CHG DONE 0 None 1 Mask I2C Read Command. The RT9941 reading address set 9D hex and read the interrupt status from internal register (Figure 5). Address START g R A5 A4 A3 A2 A1 A0 1 9 Read register B7 B6 B5 B4 B3 B2 B1 B0 18 STOP Figure 5. I2C Read Command of the RT9941 Table 2. The Default Status of Interrupt Registers for I2C Reading (No PWR_IN) Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name Default PWR_IN 0 PWR_OUT 1 PWR_ID 0 Reserved 1 Time Out 0 1 0 0 0 PWR_DS 0 DS9941-01 April 2011 www.richtek.com 19 RT9941 LDO1 & LDO2 Voltage Setting Pin S1 and S2 are tri-stat input to set LDO1 and LDO2 voltage. Connect to VSYS directly to pull high and GND to pull low. The Voltage setting table is listed in Table 3. Table 3. LDO1 & LDO2 Voltage Setting S1 S2 LDO1 (V) LDO2 (V) L H 3.3 1.2 H L 2.8 1.2 H H 2.5 1.2 L F 1.8 1.2 F H 2.5 1.3 F F 1.8 1.3 H F 3.3 1.3 F L 2.5 1.0 L L 3.0 1.2 Power Sequence If the PWR_IN and VSYS pin voltages are below the internal UVLO threshold, all IC blocks are disabled and the RT9941 is not operational. When an external power source or battery with voltage greater than the UVLO voltage threshold is applied to VSYS pins, the internal RT9941 references are powered up and biasing internal circuits. When all the main internal supply rails are active, the RT9941 I2C registers are set to the power-up default values. If a power good fault is not present at the end of the power good check mode and then NORMAL mode starts. In this mode of operation, the I2C registers define the RT9941 operation, and must be able to handle all issues regarding power on/off the handheld device. The PWR_ON and PWR_HOLD pins determine the power on/off status of the handset. Logic high on PWR_ON pin is the normal way of powering up a handset. The PWR_ON signal is held high for at least 320 ms; Buck1, 2 and LDO1, 3 are turned on; when Buck2 reaches 87% of its final value, a 200ms reset timer is started at after which nRESET is asserted high, and then the handheld device processor is initialized and will assert PWR_HOLD high to maintain power on. This wrap around constitutes the PWR_ON button can be released (return to low state) and the power remains on. If, however, PWR_ON is released before the PWR_HOLD signal is asserted, then Buck1, 2 and LDO1, 3 will be turned off. All output could be turned off by the processor asserting PWR_HOLD low, if PWR_ON = Low. The RT9941's default power output voltages for SiRF TitanII and A4 platform are listed in Table 4 as following : Table 4. The RT9941 for Samsung Platform Power Terminology Control Pin Default Output Voltage Buck1 Buck2 LDO1 LDO2 LDO3 LDO4 PWR_ON PWR_EN PWR_ON PWR_EN PWR_ON I C 1.8V 1.2V Only auto start up in the First time by PWR_ON SiRF Titan II VDDIO_MEM A4 www.richtek.com 20 VDD_PDN 3.3V 1.2V VDDIO VDD_PLL VDDIO_PLL 1.2V 2 LDO5 2 I C 2.5V 3.3V Only auto start Only auto start up up in the First in the First time by time by PWR_EN PWR_EN VDDA2V5_USB, VDDIO_TSC VDDA3V3_ USB VDD_PRE VDDA_TSC, VREF_ADC DS9941-01 April 2011 RT9941 VSYS CLK 2 2 I C Decoder DATA nINT I C Registers and NonVolatile Memory Interrupt Controller VMEM VSYS Host Processor nPBSTAS nRESET PWR_HOLD PWR_EN HP_PWR PWR_ON Sequencing & Operating Mode Setting System and Battery Charger Control Logic VSYS PWR_IN BATT VSYS Figure 6. Power and Interface Module LDO1, 2 voltage setting by Pin S1 and S2 LDO2 and Buck2 can be turned on/off by the external PWR_EN pin. The I2C will be activated if the Buck1 is enabled. LDO 4,5 can be turn on by PWR_EN pin in the first power on sequence. LDO 1, 2, 3, 4, 5 and Buck1, 2 output voltages can turned on and off by I2C. LDO 3, 4, 5 and Buck2 output voltages can be programmed by I2C. PWR_ON 300ms VDD_PRE LDO3 VDD_PDN BUCK2 LDO1 BUCK1 10µs VDD_IO, VDDIO_PLL 100µs VDDIO_MEM, VREF_MEM 100µs PWR_EN VDD_PLL, VDDA_PLL LDO2 LDO4 LDO5 100µs VDDA2V5_USB, VDDIO_TSC VDDA_TSC, VREF_ADC VDDA3V3_USB 300µs PWR_HOLD 2 I C: LDO4/5_EN nRESET 200ms Figure 7. RT9941 POWER ON/OFF Timing Diagram DS9941-01 April 2011 www.richtek.com 21 RT9941 Sleep Mode The external host can set the RT9941 in sleep mode using the GPIO configuration. In the sleep mode, change the PWR_EN signal to set different output on/off status : 1. Buck2 and LDO2 will be disabled when the PWR_EN is turned off to enter the sleep mode. 2. When the PWR_EN is turned on, the Buck2 and LDO2 are enabled and the reset signal from the RT9941 remains high. Deep Sleep Mode In Deep Sleep Mode, an I2C register is used to control the RT9941 to turn off specific power output. To enter deep sleep mode operation, the RT9941 is needed to set I2C register bits, both DS_RDY = 1 and PWR_DS = 1. After the RT9941 receiving the command by I2C interface , It will just remain Buck1 turn on and all the other power output will be turned off, The RT9941 output reset signal will be driven to low state to processor. If the PWR_ON signal is set to high again, the RT9941 output will be waken up and recovered to the previous state. For recording this deep sleep mode wake up situation, the PWR_DS = 0 and DS_RDY keep high must be made to acknowledge the processor (Figure 8). Power on sequence Power off sequence Deep-sleep Mode Normal Mode Wake up sequence Normal Mode Set PWR_ON to Hi TO Wake up PWR_ON LDO3 Buck2 LDO1 Buck1 Set DS_RDY = 1 and PWR_DS = 1 2 I C Command nRESET T1 T2 Notes 1 : T1 at least 650µs for internal LVR setting up time, is about 2ms to wait PLL stable Other time interval is dependent on power stable. Notes 2 : After wake up sequence from Deep-sleep Mode, the power on sequence to Normal Mode is similar to when powering on initially. Figure 8. RT9941 Deep Sleep Mode Timing Diagram The relationship between I2C register and different mode setting is listed in Table 5. Table 5. Different mode setting by PWR_DS and DS_RDY System Mode Normal Mode (Default Status) To Enter Deep Sleep Mode Power on From Deep Sleep Mode www.richtek.com 22 PWR_DS DS_RDY 0 1 0 0 1 1 DS9941-01 April 2011 RT9941 Interrupt Mode The RT9941 interruption controller monitors multiple system status parameters and signals to the host when one of the monitored parameters toggled, as a result of system status change. If the external interrupt event happened, the internal interrupt flag of the RT9941 will be triggered. The interrupt flag with no mask will set the nINT to low state. The host processor receivers the active low signal and then try to read the interrupt register by I2C interface. The interrupt controller setting and function in register are listed in the Table 6. Table 6. Interrupt Register Table Register Name Default F un ction Bit7 PW R _IN 0 If PW R_IN Bit6 PW R _OU T 1 Bit5 PW R _ID 0 If PW R_IN= Lo, this bit w ill be set. If PW R_IN =H & PW R_ID=H T his bit will be set. Bit4 Reserved 1 Bit3 T IM E_OUT 0 T his bit will be set if tim e out. Bit2 CHG_DONE 0 Bit1 DS _RDY 0 Bit0 PW R_DS 0 T his bit will be set if charge done. Yes If PM U enter to deep sleep m ode, this bit No will be set. If PM U power on from deep sleep m ode, No this bit need to be s et. = Hi, this bit will be set. INT Even t Yes Yes Yes No Yes If this internal interrupt event is set without mask, the interrupt controller will set nINT to low if any interrupt behavior happened. Then processor will be acknowledged by nINT and then read register status by I2C interface. PMU will accept this READ OK status and let the nINT return to high (Figure 9). If this internal interrupt register is set with mask, the interrupt controller will not set nINT to low even external real interrupt event happened (Figure 10). Interrupt Event Interrupt Mask = 0 CLK DATA READ OK nINT Figure 9. Interrupt without Mask Interrupt Event Interrupt Mask = 1 SET MASK = 0 CLK DATA nINT READ OK Figure 10. Interrupt with Mask DS9941-01 April 2011 www.richtek.com 23 RT9941 PWR_ON & HP_PWR & nPBSTAS Connecting external signal such as head phone can start up the power sequence of power management circuit. When the RT9941 detects a HP_PWR rising edge signal and generates a over 320ms pulse. All RT9941 output will be turned on even the without recognizing PWR_ON signal. The handheld device processor is initialized and will assert PWR_HOLD to high to maintain the RT9941 power remains on. This power on behavior is same as PWR_ON signal asserted. nPBSTAS signal is an inverter of PWR_ON with 320ms de-bounced to inform SOC or uP that power on button has been pressed. PWR_ON & HP_PWR & nPBSTAS timing control diagram in the Figure 11. PWR_ON HP_PWR nPBSTAS LDO3 Buck2 LDO1 Buck1 320ms nRESET 200ms PWR_HOLD Figure 11. PWR_ON & HP_PWR & nPBSTAS Timing Diagram Buck Converters The RT9941 step-down converters are optimized for high efficiency over a wide load range, small external component size, low output ripple, and excellent transient response. The DC/DC converters also feature an optimized on-resistance internal MOSFET switch and synchronous rectifier to maximize the efficiency and minimize the external components. The RT9941 utilizes a proprietary hysteretic PWM control scheme that switches with nearly fixed frequency, allowing the customer to trade some efficiency for smaller external component, as desired. If one buck converter is not used, please make LX = open, FB = IN, and PGND = GND. VSYS CIN Zero-Current ZC Detection Current Limit OC Logic + Buffer VREF + - Reference L LX R1 VOUT CFF R2 PGND COUT FB Figure 12. Step-down Converter Block Diagram www.richtek.com 24 DS9941-01 April 2011 RT9941 Setting the Output Voltage Select an output voltage between 0.6V and 2.5V by connecting FB to a resistive voltage divider between LX and GND. Choose R2 for a reasonable bias current in the resistive divider. A wide range of resistor values is acceptable, but a good starting point is to choose R2 as 100kΩ. Then, R1 is given by : ( ) VOUT = R1 + 1 × VFB1 , where VFB1 is the feedback reference voltage (0.6V typ.) R2 Below table is the default value of resistor and CFF for different output voltages. VBuck (V) R1 (k) R2 (k) CFF (pF) 1.2 100 100 220 1.8 200 100 120 2.5 316 100 120 Inductor Selection The RT9941 step-down converters operate with inductors of 1μH to 4.7μH. Low inductance values are physically smaller but require faster switching, which results in some efficiency loss. The inductor's DC current rating only needs to match the maximum load current of the application because the RT9941 step-down converters feature zero current overshoot during startup and load transients. The recommended inductor is 2.2μH. For optimum voltage positioning load transients, choose an inductor with DC series resistance in the 50mΩ to 150mΩ range. For higher efficiency at heavy loads (above 200mA) or minimal load regulation (but some transient overshoot), the resistance should be kept below 100mΩ. For light load applications up to 200mA, much higher resistance is acceptable with very little impact on performance. Output Capacitor Selection The output capacitor, COUT, is required to keep the output voltage ripple small and to ensure the regulation loop stability. COUT must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their characteristics of small size, low ESR, and small temperature coefficients. Due to the unique feedback network, the output capacitance can be very low. For most applications, a 4.7μF capacitor is sufficient. Feedforward Capacitor Selection The feedforward capacitor, CFF, sets the feedback loop response, controls the switching frequency, and is critical in obtaining the best efficiency possible. Choose a small ceramic X7R capacitor with value given by : CFF = L × 10 R1 Select the closest standard value to CFF as possible. Charger The RT9941 has an integrated charger with power path integrated MOSFETs. This topology, shown in the simplified block diagram (Figure 13), enables the goal of using an external input power to run the system and charge the battery. The power path has single inputs that can be used to select either an external AC_DC adapter or USB port by PWR_ID pin and different charging current by limitation. The RT9941 connects the end equipment main power rail and charges the battery pack by the BATT pin. DS9941-01 April 2011 www.richtek.com 25 RT9941 USB/AC Adapter System Power Bus Q1 PWR_IN VSYS CC/CV Dynamic Battery Supplement LDO Q2 Battery BATT + Power Path Control, nCHG_S System power and Current PWR_ID limit selection Current Scaling and Charger Suspend Li NTC TS ISETA RSET Figure 13. Charger Block Diagram and Required External Components The RT9941 charger uses current, voltage, and thermal control loops to charge and protect a single Li+ battery cell. One enable input PWR_ID pin is supplied to set charging current limits. During pre-charge and fast-charge phases, the charger output status is pulled low. As the battery voltage approaches 4.2V, the charging current is reduced. When the charging current drops below 10% of charging current setting and the battery voltage equals 4.2V, the nCHG_S output pin goes high impedance, signaling a full battery and set the internal I2C register bit CHG DONE. If the charger done is not masked, the interrupt flag will be trigged. At any time during charging, if the RT9941 internal I2C register bit, Charger ON/OFF, is clear. Then the charger enters suspend mode, charging stops, and nCHG_S goes high impedance. Battery Charge Management Function The RT9941 supports charging of single-cell Li-Ion battery packs. The charge process is executed in three phases: precharge (or preconditioning), constant current and constant voltage. A typical charge profile and flow chart are shown in Figure 14 & 15. Precharge Phase Programmed Charge Current Fast Charge Phase Constant Voltage Phase & Standby Phase Recharge Phase 4.2V 4.1V Recharge Threshold 1/10 Programmed Charge Current 2.8V Precharge Threshold Charge Complete Figure 14. Typical Charge Profile www.richtek.com 26 DS9941-01 April 2011 RT9941 UVLO > VIN < OVP 2 & I C = ON &VIN > BATT YES BATT < 4.1V 0.5V < TS < 2.5V YES YES BATT>2.8V NO Fast-CHG State ICHG_fast = 1000mA @RSET = 1.5k⎝ NO Power Off State PFET = OFF Pre-CHG State ICHG_pre = 0.1 x ICHG_fast NO Any State if VIN < UVLO or VIN > OVP or 2 I C = OFF or VIN < BATT Check Thermal Temp.<125°C NO Decrease ICHG_fast Temp.<125°C YES Charge Done State ICHG = 0A YES ICHG<0.1*ICHG_fast NO Figure 15. Charge Flow Chat Power-Path Management The power path and charge management block operate independently of the other RT9941 circuits. Internal circuits check battery parameters (pack temperature, battery voltage and charge current) and system parameters, setting the power path MOSFETs operating modes automatically. The RT9941 has integrated comparators that monitor the battery voltage, Power input pin voltage and the SYS pin voltage. The data generated by those comparators is used by the power path control logic to define which of the integrated power path switches is active. A typical auto power path management profile is shown in Figure 16 & 17. PWR_IN 5V SYS 4.65V 4.2V BATT 4.0V 0V 3A 2A IBATT 1A ISYS 0 IPWR_IN -1A -2A -3A T1 T2 T3 T4 T5 T6 T7 Figure 16. Typical Power Path Management Profile DS9941-01 April 2011 www.richtek.com 27 RT9941 AC supply SYS & BATT SYS > BATT (T1,T2,T6,T7) YES BATT supply SYS SYS < BATT (T8) ACOK? NO ACOK? NO YES AC Current Limit NO YES NO AC supply SYS & BATT Reduce charge current SYS = 4.2V > BATT (T3,T5) NO YES ACOK? AC Current Limit YES SYS Load > AC Current Limit NO YES AC & BATT supply SYS SYS < BATT (T4) NO Figure 17. Power Path Management Flow Chart The RT9941 powers the system while independently charging the battery. This feature reduces the charge and discharge cycles on the battery, allows for proper charge termination, and allows the system to run with an absent or defective battery pack. This feature gives the system priority on input power, allowing the system to power up with a deeply discharged battery pack. This feature works as follows: Case 1: AC Mode (PWR_ID = LOW) In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (Figure 18). The output SYS is regulated at 5.0 V. If the system load exceeds the capacity of the supply, the output voltage drops down to the battery's voltage. When in AC mode, the battery is charged through the switch Q2 based on the charge rate set on the ISETA input pin. This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting, or removal of the input supply. If the voltage on the VSYS pin drops to a preset value(4.2V) due to a limited amount of input current, then the battery charging current is reduced until the VSYS stops dropping. If the system continues increasing load to exceed the AC adapter capacity, the battery will start to discharge to VSYS. Adapter PWR_IN From adapter V+ LDO V+ VSYS GND Q1 ID GND PWR_ID Power Path Control, System power and Current limit selection Figure 18. RT9941 Powered by AC Adapter www.richtek.com 28 DS9941-01 April 2011 RT9941 Case 2: USB Mode (PWR_ID = High) In this case, the system load is powered from a USB port through the internal switch Q1 (Figure 19). Note that in this case, Q1 regulates the total current to the 450mA level as selected on the input. The output, SYS, is regulated to 5V. The system's power management is responsible for keeping its system load below the USB current. Otherwise, the output drops (VSYS) to the battery voltage; therefore, the system should have a low-power mode for USB power application. USB USB port from PC or Notebook VBUS Q1 LDO VBUS D+ D- GND PWR_IN VSYS PWR_ID ID GND Power Path Control, System power and Current limit selection Figure 19. RT9941 Powered byUSB Port Table 7. PWR_IN Input Current and Charger Current-Limit Selection PWR_ID PWR_IN Current Limit Expected Input Type Charger Current Limit Hi 450mA USB 450mA Lo 2.3A AC adapter (2.5V/Rset)*600 Charge-Current Selection When powered from a USB port, the input current is available to 0.5 A. For AC-Adapter input applications (PWR_ID = Low) requiring a different current requirement, set the charging current with an external resistor (RSET) from ISETA to GND. Calculate charge current as follows : Charge Current = 2.5/ RSET(kΩ) x 600 (mA) The RT9941 offers ISETA pin to determine the AC charge rate from 100mA to 1A. Charge-Status Output nCHG_S is an open-drain output that indicates charger status and can be used with an external LED. nCHG_S goes low during charging. When VBAT equals 4.2V and the charging current drops below 10% of the setting charge current, nCHG_S goes high impedance and the RT9941 internal I2C register bit CHG DONE will be set. Connect a pull-up resistor between nCHG_S and VSYS to indicate charge status. Soft-Start To prevent input transients, the change rate of the charge current is limited when the charger is turned on or changes its current compliance. It takes approximately 1ms for the charger to go from 0mA to the maximum fast-charge current. Temperature Monitoring The RT9941 monitors the battery temperature by measuring the voltage between the TS and GND pins. The RT9941 has an internal current source to provide the bias for most common 10kΩ negative-temperature thermistor (NTC) with the battery. DS9941-01 April 2011 www.richtek.com 29 RT9941 VBATT ITS Temperature Sense + A + A VBATT ITS NTC TS Battery 0.1uF to 10uF VTS = RTS × 100uA Figure 20. Connection of Battery Temperature Monitor Temperature Sense TS RT1 NTC Battery 0.1uF to 10uF RT2 R × (RT1 + RNTC ) VTS = ITS × T2 RT1 + RT2 + RNTC Figure 21. Connection of Battery Temperature Monitor With Divider The RT9941 compares the voltage on the TS pin against the internal VTS thresholds to determine if charging is allowed. When the temperature outside the VTS thresholds is detected, the device immediately stops the charger. Charging is resumed when the VTS is recovered to the operation range. However, the user may modify thresholds by adding external resistors to change biasing voltage. Timer As a safety mechanism, the charger has a user programmable timer that monitors the pre-charge and fast charge time. This timer (charge safety timer) is started at the beginning of the pre-charge and fast charge period. The safety charge timeout value is set by the value of an external capacitor connected to the TIMR pin (CTIMR), if pin TIMR is short to GND, the charge safety timer is disabled. As CTIMR = 0.1μF, TFAULT is CTIMR (F) x 1.97 x 1011 secs = 19700 secs and TPRECH = TFAULT /8 As timer fault, re-plug-in power or I2C ON/OFF charger again can release the fault condition. SYS Output The RT9941 contains a SYS output which can be regulated up to 5V. Bypass SYS to GND with a 22μF or larger ceramic capacitor to improve the transient droops. When charging a battery, the load on SYS is serviced first and the remaining available current goes to charge the battery. Battery PRE-CHARGE During a charge cycle, if the battery voltage is below the VPRECH threshold and the RT9941 applies a pre-charge mode to the battery. This feature revives deeply discharged cells and protects battery life. The RT9941 internally determines the pre-charge rate as 10% of the fast charge current. Thermal Regulation The RT9941 features a thermal limit that reduces the charge current when the die temperature exceeds +125°C. As the temperature increases, the RT9941 features a junction temperature regulation loop. If the power dissipation of the IC results in a junction temperature greater than the thermal regulation threshold (125°C), the RT9941 throttles back on the charge current in order to maintain a junction temperature around the thermal regulation threshold (125°C). The RT9941 monitors the junction temperature, TJ, of the die and disconnects the battery from the input if TJ exceeds 125°C. This operation continues until junction temperature falls below the thermal regulation threshold (125°C) by the hysteresis level. This feature prevents the maximum power dissipation from exceeding typical design conditions. www.richtek.com 30 DS9941-01 April 2011 RT9941 Capacitor Selection Connect a ceramic capacitor from PWR_IN to GND as close to the IC as possible for proper stability. For most applications, connect a 4.7μF ceramic capacitor from IN to GND as close to the IC as possible. Linear Regulators The RT9941 offers five Integrated Linear Regulators, designed to be stable over the operating load range with the use of external ceramic capacitors. All the LDO have an ON/OFF control which can be set by I2C commands and have integrated switches that discharge each output to ground when the LDO is turned off. The LDO 1, 3 will be turn on in the first time of PWR_ON button be pressed and LDO2 will be turned on when PWR_EN = 1. LDO 4, 5 need to be turned on/off by I2C command. The LDO4,5 also support four voltage setting by I2C control. LDO1 and LDO2 voltages are set by the S1, S2 pin, see Table 3. Low-Battery Detector nLBO is an open-drain output that typically connects to the BATT FAULT input of the processor to indicate the battery has been removed or discharged. nLBO is typically pulled up to VSYS. LBI monitors the input voltage (usually connect to VSYS) and triggers the nLBO output (Figure 22). nLBO is high impedance when the voltage from LBI exceeds the battery rising threshold VLBITH =1.05V (typ.). nLBO is low when the voltage from LBI falls below the low-battery falling threshold VLBITH =1V (typ) (Figure 23). Connecting LBI to two-resistor voltage divider to detect the external resistor embedded in a battery pack and is also used as a pack ID function. When system first power up or back from deep sleep mode , LBI will check the VSYS voltage. If VSYS voltage is lower than setting voltage, system will not power up or wake up. If the low-battery-detector feature is not required, connect nLBO to ground and connect LBI to SYS. nLBO + VSYS LBI SYS 1V - LBI Figure 22. LBI and nLBO Application Circuit 1V 1.05V nLBO Figure 23. Typical LBI Rising and Falling Threshold Voltage. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / θJA Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9941, where TJ(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-40L 5x5 packages, the thermal resistance θJA is 36°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = ( 125°C - 25°C) / (36°C/W) = 2.778W for WQFN-40L 5x5 packages DS9941-01 April 2011 www.richtek.com 31 RT9941 Maximum Power Dissipation (W) The maximum power dissipation depends on operating ambient temperature for fixed TJ (MAX) and thermal resistance θJA. For RT9941 packages, the Figure 24 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Layout Considerations For the best performance of the RT9941, the following PCB Layout guidelines must be strictly followed. ` Place the input and output capacitors as close as possible to the input and output pins. ` Keep the main power traces as possible as wide and short. Four Layers PCB ` To minimize EMI, the switching area connected to LX inductor should be smallest possible. ` Place the feedback components as close as possible to the FB pin and keep these components away from the noisy devices. Also, the feed forward capacitor CFF trace is sensitive to the magnetic field that the inductor generates. Please keep the CFF trace away from the inductor and use a via and run the trace between ground layers. WQFN-40L 5x5 0 25 50 75 100 125 ` Connect the GND and Exposed Pad to a strong ground plane for maximum thermal dissipation and noise protection. Ambient Temperature (°C) Figure 24. Derating Curves for RT9941 Packages GND GND CPWR_IN ISETU PWR_IN PWR_IN PWR_ID VSYS VSYS HP_PWR PWR_ON PWR_HOLD CLK VSYS R1 R14 VSYS 1 30 2 29 3 28 4 27 5 6 Place input and output capacitors (connected to the ground) as close as possible to the IC. 25 7 24 8 23 41 9 22 21 10 DATA BATT BATT FB1 PGND1 LX1 VIN1 LX2 PGND2 FB2 C5 VOUT5 nPBSTAS nRESET nINT nLBO LBI GND S2 S1 PWR_EN 11 12 13 14 15 16 17 18 19 20 C4 high-current path should be made as short and wide as possible. GND 26 GND R9 R6 R7 VSYS R4 R5 VSYS R8 Keep the voltage feedback network very close to the IC, but away from Inductor & LX. R13 40 39 38 37 36 35 34 33 32 31 nCHG_S R2 ISETA R3 TS GND C6 TIMER VOUT2 C2 GND VIN3 C3 CIN3 VOUT3 VOUT1 C1 VIN2 CIN2 VOUT4 GND CSYS VSYS GND CBATT Buck1 CFF1 R11 R10 L1 CIN1 L2 R13 CBuck1 R12 GND CBuck2 CFF2 Buck2 Connect the inductors, output capacitors, and feedback resistors as close to the IC as possible and keep the traces short, direct, and wide. Figure 25. PCB Layout Guide www.richtek.com 32 DS9941-01 April 2011 RT9941 Outline Dimension D SEE DETAIL A D2 L 1 E2 E e b 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. A1 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 4.950 5.050 0.195 0.199 D2 3.250 3.500 0.128 0.138 E 4.950 5.050 0.195 0.199 E2 3.250 3.500 0.128 0.138 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 40L QFN 5x5 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9941-01 April 2011 www.richtek.com 33