RICHTEK RT9945

RT9945
Power Management ICs for Handheld Device
General Description
Features
The RT9945 is a complete power management IC (PMIC)
for handheld device platform. This PMIC contains a fully
integrated linear charger for a single cell Lithium Ion battery,
five LDO linear regulators and two high efficiency buck
converters, a comparator, a reset and an I2C serial interface
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` Adapter/USB & Battery Two Input with Auto Power
to program one buck and one regulator output voltages as
well as power on timing control for complete flexibility.
The linear charger integrates LDO, MOSFET pass element,
and thermal-regulation circuitry. The proprietary thermalregulation circuitry limits the die temperature when fast
charging or while exposed to high ambient temperatures,
allowing maximum charging current without damaging the
IC.
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The two step-down converters are optimized for small size
inductor and high efficiency applications. They utilize a
proprietary hysteretic PWM control scheme that switches
with nearly fixed frequency and is adjustable, allowing the
customer to trade some efficiency for smaller external
component, as desired. The output current is guaranteed
up to 600mA, while quiescent current is a low 40μA (typ).
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The LDO linear regulators provide high power supply
rejection rate and have only 45uVRMS of output noises for
100Hz to 10kHz frequency range to power noise sensitive
RF sections.
The RT9945 is available in WQFN-40L 5x5 package.
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Ordering Information
RT9945
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
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Richtek products are :
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RoHS compliant and compatible with the current require-
Dynamic Path.
` PWR_IN LDO Support Continuous 1.5A, Peak 2A
Current
` 4.5V to 5.5V Operation Voltage Range with Max.
18V Input Voltage
` Switch Well for LDO and Charger Power MOSFET
` Set Charge Current by ISETA Pin
` Charge Status Indicator
` Interrupt for PWR_IN Plug In/Out, Time Out and
Charger Done.
` Battery Temperature Monitoring
Hysteretic Buck
` Buck 1 for Memory, Adjustable Voltage and 600mA
Output Current
2
` Buck 2 for Core voltage with 25mV/step I C
Adjustable, 600mA Output Current
` Max. Efficiency Up to 90%
LDO
` LDO1 : 3.3V/500mA for I/O, Default ON
` LDO2 : 1.2V/80mA for PLL, Default ON
` LDO3 : 1.2V/80mA for VDD Alive.
` LDO4 : 2.5V/50mA, Default OFF
` LDO5 : 3.3V/50mA, Default OFF
` Minimize the External Component Counts
Other
` Low Voltage Detector
2
` I C Compatible Interface
` Power ON Timing Control
RoHS Compliant and Halogen Free
Applications
Note :
`
Charger
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GPS and PND
PDA and Smart Phones
Handheld Devices
ments of IPC/JEDEC J-STD-020.
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Suitable for use in SnPb or Pb-free soldering processes.
DS9945-01 April 2011
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1
RT9945
Pin Configurations
ISETU
PWR_IN
PWR_IN
PWR_ID
VSYS
VSYS
HP_PWR
PWR_ON
PWR_HOLD
CLK
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
nCHG_S
ISETA
TS
TIMER
VOUT2
VIN3
VOUT3
VOUT1
VIN2
VOUT4
1
30
2
29
3
28
4
27
5
6
26
GND
25
7
24
8
23
41
9
22
21
10
DATA
BATT
BATT
FB1
PGND1
LX1
VIN1
LX2
PGND2
FB2
VOUT5
nPBSTAS
nRESET
nINT
nLBO
LBI
GND
S2
S1
PWR_EN
11 12 13 14 15 16 17 18 19 20
WQFN-40L 5x5
Functional Pin Description
Pin No.
Pin Name
1
nCHG_S
2
ISETA
Pin Function
This pin indicates the status of the battery charger. Open Drain Output and
Active Low.
PWR_IN Charge Current Setting Pin.
3
TS
Temperature Sense Pin.
4
TIMER
Charge Time Setting.
5
VOUT2
6
VIN3
7
VOUT3
1.2V/80mA LDO regulator.
This pin must be shorted to VSYS, VIN1 and VIN2. Connect a 4.7μF ceramic
capacitor from VIN3 to GND.
1.2V/80mA LDO Regulator with 25mV/Step Adjustable.
8
VOUT1
9
VIN2
10
VOUT4
11
VOUT5
12
nPBSTAS
13
nRESET
14
nINT
15
nLBO
16
LBI
17,
GND
41 (Exposed Pad)
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2
3.3V/500mA LDO Regulator.
Must be shorted to VSYS, VIN1 and VIN3. Connect a 10μF ceramic capacitor
from VIN2 to GND.
2
2.5V/50mA LDO Regulator. Default off, controlled by I C.
2
3.3V/50mA LDO Regulator. Default off, controlled by I C.
Push-Button Status Pin. This pin is used to inform the power good state to
processor. Open Drain Output and Active Low.
This pin provides a 200ms reset signal during power-up to initialize a processor.
Open Drain and Active Low.
This pin must be Active Low to inform processor the interrupt events happened,
Open Drain Output and Active Low.
Low-Battery indication. Open Drain Output and Active Low.
Low-Battery Detection. This pin is used to monitor the VSYS voltage and the
internal reference voltage is 1V.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
To be continued
DS9945-01 April 2011
RT9945
Pin No.
Pin Nam e
Pin Function
LDO1 & LDO2 Output Voltage Setting. Directly connect VSYS to pull high, GND
to pull low.
LDO1 & LDO2 Output Voltage Setting. Directly connect VSYS to pull high, GND
to pull low.
18
S2
19
S1
20
PWR_EN
Buck2 & LDO2 Enable Pin from Processor.
21
FB2
Voltage Feedback 2. FB2 regulates to 0.675V nominal.
22
PGND2
Buck 2’s Power Ground.
23
LX2
Inductor connection to the drains of the Internal N-MOSFET and P-MOSFET.
24
VIN1
This pin must be shorted to VSYS, VIN2, and VIN3. Connect a 10μF ceramic
capacitor from VIN1 to GND.
25
LX1
Inductor connection to the drains of the Internal N-MOSFET and P-MOSFET.
26
PGND1
Buck 1’s Power Ground.
27
FB1
Voltage Feedback 1. FB1 regulates to 0.6V nominal.
28,29
BATT
30
DATA
Main Battery Supply Input Terminal. This pin delivers charging current and
monitors battery voltage.
Data Input/ Output for Serial Interface.
31
CLK
Clock Input for Serial Interface.
32
PWR_HOLD
33
PWR_ON
34
HP_PWR
37
PWR_ID
Logic low signal from processor to turn-off the PMU.
Active High Power On/ Off Key Input. This pin has an Internal 2μA pull-down
current to GND. W hen the push button is closed, It Is shorted to SYS, not
Ground. This input is de-bounced with 320ms (typ).
Logic High Signals Connection of Hands Free Kit. This pin has an Internal 2μA
pull-down current to GND. This input is de-bounced with 320ms (typ).
Connect this pin to system with a minimum 22μF ceramic capacitor to GND.
This pin must be shorted to VIN1, VIN2, and VIN3
Power Source Input Detection Pin.
38,39
PWR_IN
Power Source Input. Connect a 4.7μF ceramic capacitor from this pin to GND.
ISETU
USB Charge Current Setting Pin.
35,36
40
VSYS
DS9945-01 April 2011
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3
RT9945
Typical Application Circuit
RT9945
LDO1 (S1 and S2 Control) 500mA
8 VOUT1
1µF
LDO2 (S1 and S2 Control) 80mA
5 VOUT2
1µF
7
LDO3 80mA
1µF
1µF
LDO5 (I2C Control) 50mA
11 VOUT5
1µF
PWR_IN
35, 36 VSYS
To VIN1, VIN2, VIN3
22µF
28, 29
+
200k
BATT
1µF x 2
100k
PGND1 26
LX2
23
VSYS
VSYS
4
510
TIMER
100k
VIN1 24
100k
VIN3
GND
4.7µF
16
LBI
nRESET 13
nINT
500mA
40 ISETU
18 S2
19 S1
20 PWR_EN
100mA
USB
Adapter
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4
32 PWR_HOLD
37
PWR_ID
VSYS
VSYS
VSYS
17, Exposed Pad (41)
100k
100k
14
39k
VBACK1
10µF
6
nPBSTAS 12
1 nCHG_S
100k
220pF
10µF
CTIMER
0.1µF
VBUCK2
1.35V/600mA
4.7µF
PGND2 22
NTC
RSET
2k
(750mA)
L2
2.2µH
FB2 21
VIN2 9
3 TS
2 ISETA
VBUCK1
1.8V/600mA
4.7µF
120pF
100k
38, 39
+5V (Adapter / USB)
L1
2.2µH
FB1 27
VOUT3
10 VOUT4
LDO4 (I2C Control) 50mA
LX1 25
nLBO 15
DATA 30
CLK 31
PWR_ON 33
100k
100k
4.7k
4.7k
VSYS
VBACK1
VSYS
VSYS
VSYS
VSYS
VSYS
HP_PWR 34
DS9945-01 April 2011
RT9945
Function Block Diagram
PWR_ID
PWR_IN
Control
Circuit
SW
VSYS
BATT
S2
S1
VIN1
LX1
Buck1
ISETU
ISETA
TS
TIMER
nCHG_S
Li-lon Linear Charger
Control
PGND1
FB1
UVLO
Thermal
Shutdown
nRESET
Reset
nPBSTAS
LX2
PWR_ON
HP_PWR
2µA
2µA
320ms
Debounce
Buck2
320ms
Debounce
ON/OFF
2
Control & I C
Interface
BUCK1 OK
PWR_HOLD
nLBO
VSYS
+
LDO1
VOUT1
LDO2
VOUT2
LDO3
VOUT3
LDO4
VOUT4
VIN2
VOUT5
LDO5
LBI
DS9945-01 April 2011
FB2
PWR_EN
VIN3
1V
-
nINT
DATA
CLK
PGND2
GND
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5
RT9945
Absolute Maximum Ratings
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(Note 1)
PWR_IN ----------------------------------------------------------------------------------------------------PWR_HOLD, PWR_ON, HP_PWR, DATA, CLK, nCHG_S, ISETA, TS, TIMER,
nPBSTAS, nRESET, nINT, nLBO, LBI, S2, PWR_EN, PWR_ID to GND -------------------FB2, FB1, LX2, LX1 -------------------------------------------------------------------------------------VOUT2, VOUT3 ------------------------------------------------------------------------------------------VOUT1, VOUT4, VOUT5 ------------------------------------------------------------------------------VIN1, VIN2, VIN3 ----------------------------------------------------------------------------------------BATT, SYS ------------------------------------------------------------------------------------------------ISETU ------------------------------------------------------------------------------------------------------PGND1, PGND2 -----------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WQFN-40L 5x5 ------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN-40L 5x5, θJA -------------------------------------------------------------------------------------WQFN-40L 5x5, θJC ------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------
Recommended Operating Conditions
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0V to 7V
−0.3V to VSYS + 0.3V
−0.3V to VIN1 + 0.3V
−0.3V to VIN3 + 0.3V
−0.3V to VIN2 + 0.3V
VSYS−0.3V to VSYS + 0.3V
0V to 5.5V
−0.3V to PWR_IN + 0.3V ≤ 6V
−0.3V to 0.3V
2.778W
36°C/W
7°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Junction Temperature Range --------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------- −40°C to 85°C
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DS9945-01 April 2011
RT9945
Electrical Characteristics
Electrical Characteristics (General)
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
3.3
--
5.5
V
System Operating Range
Input Supply Voltage
VIN
Without PWR_IN
Shutdown Supply Current
ISHDN
VBATT = 4.2V, VOUT1 to 5, LX1, LX2
to ground.
4
10
15
μA
VBATT = 3.7V, PWR_EN = L, Only
Buck1, LDO1, LDO3 Turn On
--
120
200
μA
VSYS Rising
--
3.2
--
V
VSYS Falling
--
2.5
--
V
Threshold
--
160
--
°C
Hystersis
--
10
--
°C
Sleep Mode Supply Current
System Voltage Lockout
Under Voltage Lockout
Thermal Shutdown
Logic and Control Inputs
Input Low Level
PWR_HOLD, PWR_ON, HP_PWR,
DATA, CLK, PWR_EN, PWR_ID
--
--
0.4
V
Input High Level
PWR_HOLD, PWR_ON, HP_PWR,
DATA, CLK, PWR_EN, PWR_ID
1.5
--
--
V
PWR_HOLD, DATA, CLK, PWR_EN
−1
--
1
μA
PWR_ON = 0.4V
--
2
--
μA
HP_PWR = 0.4V
--
2
--
μA
--
320
--
ms
--
65
--
mV
Input Current
PWR_ON Pull-down Current to
GND
HP_PWR Pull-down Current to
GND
PWR_ON, HP_PWR
De-bounce Filter
nINT, nPBSTAS, nRESET,
nLBO Pull Down Voltage
DS9945-01 April 2011
Source Current = 5mA
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7
RT9945
Electrical Characteristics (Buck Converter 1)
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Output Adjustable Range
Typ
0.6
FB Threshold Voltage
VFB1 Falling
FB1 Threshold Line Regulation
VIN = 2.7V to 5.5V
FB BIAS Current
ILIM
On-Resistance
Max
Unit
2.5
V
0.582
0.6
0.618
V
--
0.5
--
%/V
--
12
--
mV
Shutdown
--
0.1
--
μA
VFB = 0.5V
--
0.1
--
μA
1000
1500
2000
mA
P-MOSFET Switch, ILX = −40mA
--
0.3
--
Ω
N-MOSFET Switch, ILX = 40mA
--
0.38
--
Ω
--
30
--
mA
Min
Typ
Max
Unit
VREF
--
2.5
V
0.655
0.675
0.695
V
--
1.5
--
%/V
--
12
--
mV
1000
1500
2000
mA
P-MOSFET Switch, ILX = −40mA
--
0.4
--
Ω
N-MOSFET Switch, ILX = 40mA
--
0.4
--
Ω
--
30
--
mA
0.5
--
0.7
V
--
12.5
--
mV
FB1 Threshold Voltage
Hysteresis
Current Limit
Min
P-MOSFET Switch
Rectifier Off Current Threshold
Electrical Characteristics (Buck Converter 2)
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Output Adjustable Range
Default FB2 Threshold Voltage
VFB2 Falling
FB2 Threshold Line Regulation
VIN = 2.7V to 5.5V
FB2 Threshold Voltage
Hysteresis
Current Limit
On-Resistance
ILIM
P-MOSFET Switch
Rectifier Off Current Threshold
Programmable FB2 Voltage
Each Programmable FB Voltage
Step
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8
V FB2 Falling
DS9945-01 April 2011
RT9945
Electrical Characteristics (VOUT1 (LDO1) )
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
lLOAD = 200mA & V IN = 3.7V
Min
Typ
Max
Unit
3.201
3.3
3.399
V
--
--
500
mA
500
650
850
mA
Output Voltage
VOUT1
Output Current
IOUT
Current Limit
ILIM
V OUT1 = 0V
Dropout Voltage
VDROP
lLOAD = 200mA
--
150
--
mV
Line Regulation
V OUT1 + 0.4V ≤ V BATT = VIN1 ≤ 5.5V,
ILOAD = 200mA
--
2.4
--
mV
Load Regulation
V IN1 = 3.7V, 50μA < ILOAD < 200mA
--
25
--
mV
Power Supply Rejection.
ΔVOUT/ΔV IN
F = 1kHz (COUT = 1μF),
V OUT > 2.5V, ILOAD = 30mA
--
60
--
dB
Min
Typ
Max
Unit
1.164
1.2
1.236
V
--
--
80
mA
VOUT2 = 0V
--
400
--
mA
Line Regulation
VOUT2 + 0.4V ≤ VBATT = VIN1 ≤ 5.5V,
lLOAD = 80mA
--
2.4
--
mV
Load Regulation
VIN1 = 3.7V, 50μA < lLOAD < 80mA
--
25
--
mV
Power Supply Rejection.
ΔVOUT/ΔV IN
F = 1kHz (COUT = 1μF),
VOUT > 1.2V, lLOAD = 30mA
--
60
--
dB
Min
Typ
Max
Unit
1.164
1.2
1.236
V
--
--
80
mA
V OUT3 = 0V
--
400
--
mA
Line Regulation
V OUT3 + 0.4V ≤ VBATT = VIN1 ≤ 5.5V,
lLOAD = 80mA
--
2.4
--
mV
Load Regulation
50μA < lLOAD < 80mA
--
25
--
mV
Power Supply Rejection.
ΔVOUT/ΔV IN
F = 1kHz (COUT = 1μF),
V OUT > 1.2V, lLOAD = 30mA
--
60
--
dB
Note : All output capacitors are ceramic and X7R/X5R type.
Electrical Characteristics (VOUT2 (LDO2) )
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Output Voltage
VOUT2
Output Current
IOUT
Current Limit
ILIM
Conditions
lLOAD = 80mA & VIN = 3.7V
Note : All output capacitors are ceramic and X7R/X5R type.
Electrical Characteristics (VOUT3 (LDO3) )
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Output Voltage
VOUT3
Output Current
IOUT
Current Limit
ILIM
Conditions
lLOAD = 80mA & V IN = 3.7 V
Note : All output capacitors are ceramic and X7R/X5R type.
DS9945-01 April 2011
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9
RT9945
Electrical Characteristics (VOUT4 (LDO4) )
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
2.425
2.5
2.575
V
--
--
50
mA
Output Voltage
VOUT4
Output Current
IOUT
Current Limit
ILIM
V OUT4 = 0V
--
400
--
mA
Dropout Voltage
VDROP
lLOAD = 50mA
--
50
--
mV
V OUT4 + 0.4V ≤ VBATT = V IN1 ≤ 5.5V,
lLOAD = 50mA
--
2.4
--
mV
--
25
--
mV
--
60
--
dB
Min
Typ
Max
Unit
3.201
3.3
3.399
V
--
--
50
mA
Line Regulation
lLOAD = 50mA & VIN = 3.7 V
Load Regulation
50μA < lLOAD < 50mA
Power Supply Rejection.
ΔVOUT/ΔV IN
F = 1kHz (COUT = 1μF),
V OUT > 1.2V, lLOAD = 30mA
Note : All output capacitors are ceramic and X7R/X5R type.
Electrical Characteristics (VOUT5 (LDO5) )
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Output Voltage
VOUT5
Output Current
IOUT
Current Limit
ILIM
V OUT5 = 0V
--
400
--
mA
Dropout Voltage
VDROP
lLOAD = 50mA
--
50
--
mV
Line Regulation
V OUT5 + 0.4V ≤ VBATT = VIN1 ≤ 5.5V,
lLOAD = 50mA
--
2.4
--
mV
Load Regulation
50μA < lLOAD < 50mA
--
25
--
mV
Power Supply Rejection.
ΔVOUT/ΔV IN
F = 1kHz (COUT = 1μF),
V OUT > 1.2V, lLOAD = 30mA
--
60
--
dB
lLOAD = 50mA & V IN = 3.7 V
Note :All output capacitors are ceramic and X7R/X5R type.
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DS9945-01 April 2011
RT9945
Electrical Characteristics (Li-Ion Charger)
(VPWR_IN = 5V, VBATT = 4V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
4.5
--
5.5
V
--
--
100
μA
Input Voltage Range and Input Current
PWR_IN Input Operation
Voltage Range
PWR_ID Current
ISETU Pull High Current
ISETU = 0V
--
0.5
--
μA
PWR_IN Standby Current
VBATT = 4.2V
--
300
500
μA
PWR_IN UVP Current
VPWR_IN = 4V, VBATT = 3V
--
150
250
μA
--
3.7
--
V
ISETU = H
--
450
500
ISETU = L
--
--
100
PWR_ID = L
--
2300
--
IBATT = 60mA
4.158
4.2
4.242
V
4.8
5
5.2
V
--
350
--
mΩ
--
--
150
mΩ
VPWR_IN − VBATT
--
150
--
mV
VBATT = 3.5V
--
2.5
--
V
100
--
1200
mA
PWR_IN UVP Voltage
PWR_IN Current Limit
PWR_ID = H
mA
Voltage Regulation
BATT Regulation Voltage
System Regulation Voltage
PWR_IN Power FET RDS(ON)
System to Battery RDS(ON)
PWR_IN to SYS Switch Turn
On
Current Regulation
ISETA Set Voltage (Fast
Charge Phase)
Full Charge setting range
IAC = 1A
Timer
TIMER Pin Source Current
VTIMER = 2V
--
1
--
μA
Pre-charge Fault Time
CTIMER = 0.1μF
--
2460
--
s
Charge Fault Time
CTIMER = 0.1μF
--
19700
--
s
--
2.8
--
V
--
100
--
mV
Precharge
BATT Pre-Charge Threshold
BATT Pre-Charge Threshold
Hysteresis
Pre-Charge Current
VBATT = 2V
--
10
--
%
Recharge Threshold
BATT Re-Charge Falling
Threshold Hysteresis
VREG − VBATT
--
100
--
mV
ISETA Pin Voltage
--
250
--
mV
I/nCHG_S = 5mA
--
300
--
mV
Charge Termination Detection
Termination Current Ratio
(default)
Logic Input/Output
nCHG_S Pull Down Voltage
To be continued
DS9945-01 April 2011
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11
RT9945
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
--
125
--
°C
94
100
106
μA
2.45
2.5
2.55
V
0.485
0.5
0.515
V
Min
Typ
Max
Unit
Protection
Thermal Regulation
TS Pin Source Current
TS Pin Low Threshold
Voltage
TS Pin High Threshold
Voltage
V TS = 1.5V
Electrical Characteristics (RESET & Low Battery)
(VBATT = 3.7V, CSYS+ΣVINx = 47μF, CBATT = 4.7μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
nRESET Threshold
With respect to Buck2, Rising
--
87
--
%
nRESET Active Time-out
Period
LBI Feedback Voltage
(falling)
From Buck2 ≥ 87% until RESET =
High
--
200
--
ms
--
1
--
V
LBI Hysteresis
--
50
--
mV
LBI Leakage Current
−1
--
1
μA
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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12
DS9945-01 April 2011
RT9945
Typical Operating Characteristics
Buck2 Efficiency vs. Output Current
Buck1 Efficiency vs. Output Current
100
100
90
90
80
VBATT = 3.3V
VBATT = 3.7V
VBATT = 4.2V
70
60
Efficiency (%)
Efficiency (%)
80
50
40
30
20
70
VBATT = 3.3V
VBATT = 3.7V
VBATT = 4.2V
60
50
40
30
20
10
10
VBuck1 = 1.8V
0
0.001
0.01
0.1
VBuck2 = 1.35V
0
0.001
1
0.01
Output Current (A)
Buck2 Output Voltage vs. Output Current
1.38
VBuck1 = 1.8V
VBuck2 = 1.35V
1.37
Output Voltage (V)
1.81
Output Voltage (V)
1
Output Current (A)
Buck1 Output Voltage vs. Output Current
1.82
0.1
1.8
1.79
VBATT = 4V
VBATT = 3.6V
1.78
1.77
1.36
1.35
VBATT = 4V
VBATT = 3.6V
1.34
1.33
1.32
1.76
1.31
1.75
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.8
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Output Current (A)
Output Current (A)
VBuck1, VLDO1, VLDO2 Power On
VBuck2, VLDO2 Power On from PWR_EN
VBATT = 4V
VBATT = 4V
VBuck1
(2V/Div)
PWR_EN
(1V/Div)
VLDO1
(2V/Div)
VBuck2
(1V/Div)
VLDO3
(2V/Div)
VLDO2
(1V/Div)
Time (50μs/Div)
DS9945-01 April 2011
Time (50μs/Div)
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13
RT9945
Power On nReset
LDO4, LDO5 Power On
VBATT = 4V
VBATT = 4V
CLK
(5V/Div)
PWR_EN
(2V/Div)
DATA
(5V/Div)
LDO4
(2V/Div)
nRESET
(5V/Div)
LDO5
(2V/Div)
Time (50ms/Div)
Time (25μs/Div)
LDO4, LDO5 Power Off
Normal to Sleep Mode
VBATT = 4V
VBATT = 4V
CLK
(5V/Div)
PWR_EN
(1V/Div)
DATA
(5V/Div)
VBuck2
(1V/Div)
LDO4
(5V/Div)
VLDO2
(1V/Div)
LDO5
(5V/Div)
Time (25μs/Div)
Time (10ms/Div)
Buck1 Output Voltage Ripple
Buck2 Output Voltage Ripple
VBATT = 4V, IOUT = 500mA
VBATT = 4V, IOUT = 500mA
VLX1
(2V/Div)
VLX2
(2V/Div)
VBuck1
(20mV/Div)
VBuck2
(20mV/Div)
ILX1
(500mA/Div)
ILX2
(500mA/Div)
Time (500ns/Div)
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14
Time (500ns/Div)
DS9945-01 April 2011
RT9945
Buck1 Load Transient Response
Buck2 Load Transient Response
VBATT = 4V, IOUT = 0.1A to 0.6A
VBATT = 4V, IOUT = 0.1A to 0.6A
VBuck1
(50mV/Div)
VBuck2
(50mV/Div)
I Buck1
(200mA/Div)
I Buck2
(200mA/Div)
Time (250μs/Div)
Time (250μs/Div)
Buck Frequency vs. Input Voltage
LDO1 Load Transient Response
2.5
VBATT = 4V, IOUT = 50mA to 500mA
Buck1
VLDO1
(50mV/Div)
Frequency (MHz)
2.0
Buck2
1.5
1.0
0.5
IOUT = 200mA
0.0
I LDO1
(200mA/Div)
3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
Time (100μs/Div)
Input Voltage (V)
LDO1 Output Voltage vs. Output Current
3.36
LDO1 Dropout Voltage vs. Temperature
140
VBATT = 3.8V
120
Dropout Voltage (mV)
Output Voltage (V)
3.34
3.32
3.30
3.28
3.26
3.24
100
80
60
40
3.22
20
3.20
0
0
0.1
0.2
0.3
Output Current (A)
DS9945-01 April 2011
0.4
0.5
IOUT1 = 200mA
-40
-15
10
35
60
85
Temperature (°C)
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15
RT9945
PSRR vs. Frequency
0
-10
Charge Current vs. VBATT
1200
VBATT = 4V, IOUT1 = IOUT2 =
IOUT3 = IOUT4 = IOUT5 = 30mA
PWRIN = 5V
1000
Charge Current (mA)
-20
-30
PSRR (dB)
PWRID = L, RISETA = 1.5kΩ
-40
-50
LDO5
-60
-70
LDO1
-80
800
PWRIN = 4.5V
600
400
200
-90
-100
0
1k
1,000
100
10k
10,000
100k
100,000
1
1.5
2
2.5
3
3.5
4
4.5
Charge Current vs. RISETA
Charger Power Path at AC Mode
VPWRIN = 5V, VBATT = 4V, PWRID = L
1000
IBATT
(2A/Div)
I PWRIN
(2A/Div)
VBATT
(2V/Div)
V SYS
(2V/Div)
I SYS
(2A/Div)
V PWRIN
(2V/Div)
800
600
400
200
0
0
0.5
VBATT (V)
1200
Charge Current (mA)
0
Frequency (Hz)
2.5
5
7.5
10
12.5
5
IBATT
VBATT
IPWRIN
VSYS
VPWRIN
ISYS
VPWRIN = 5V, VBATT = 4V, PWRID = L, ISYS = 0 to 2.4A
Time (1ms/Div)
15
RISETA (kΩ)
(k⎠ )
PWRIN Insert Response
Charger Power Path at USB Mode
ISYS = 0 to 2.4A
VBATT
I PWRIN
(2A/Div)
VBATT
(2V/Div)
I SYS
(2A/Div)
V PWRIN
(2V/Div)
IBATT
(2A/Div)
V SYS
(2V/Div)
IPWRIN
ISYS
VPWRIN
IBATT
(2A/Div)
I PWRIN
(2A/Div)
IBATT
IPWRIN
VBATT
VSYS
VSYS
VBATT
(2V/Div)
IBATT
V SYS
(2V/Div)
V PWRIN
(2V/Div)
VPWRIN = 5V, VBATT = 4V, PWRID = H, USBID = H
Time (1ms/Div)
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16
VPWRIN
VPWRIN = 5V, VBATT = 3.8V, PWRID = L
Time (1ms/Div)
DS9945-01 April 2011
RT9945
PWRIN Remove Response
IBATT
(2A/Div)
I PWRIN
(2A/Div)
IBATT
IPWRIN
VBATT
VSYS
VBATT
(2V/Div)
V SYS
(2V/Div)
V PWRIN
(2V/Div)
VPWRIN
VPWRIN = 5V, VBATT = 3.8V, PWRID = L
Time (250ms/Div)
DS9945-01 April 2011
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17
RT9945
Application Information
line is stable low during the high period of the Acknowledge
clock pulse (set-up and hold times must also be met). A
master receiver must signal an end of data to the
transmitter by not generating an acknowledge signal on
the last byte that has been clocked out of the slave. In this
case the transmitter must leave DATA high to enable the
master to generate a stop condition.
I2C Start and Stop Conditions
Both DATA and CLK remain high when the bus is not busy.
A high-to-low transition of DATA, while CLK is high is defined
as the Start condition. A low-to-high transition of the data
line while CLK is high is defined as the Stop condition.
I2C Acknowledge
I2C System Configuration
The number of data bytes between the start and stop
conditions for the Transmitter and Receiver are unlimited.
Each 8-bit byte is followed by an Acknowledge Bit. The
Acknowledge Bit is a high level signal put on DATA by the
transmitter during which time the master generates an extra
acknowledge related clock pulse. A slave receiver which
is addressed must generate an Acknowledge after each
byte it receives. Also a master receiver must generate an
Acknowledge after each byte it receives that has been
clocked out of the slave transmitter.
A device on the I2C Bus which generates a “message” is
called a “Transmitter” and a device that receives the
message is a “Receiver”. The device that controls the
message is the “Master” and the devices that are
controlled by the “Master” are called “Slaves”.
I2C Write Command.
The RT9945 writing address set 9C hex and write command
and data to set internal register.
TYPE I : Send the address and one command by I2C (Figure
3).
The device that Acknowledges must pull down the DATA
line during the acknowledge clock pulse, so that the DATA
SCL
SDA
A6
A5
A0
W
A
0
Dx4
Dx0
A
01 or 10 or 11
Write command Acknowledge
from the master. from the slave.
START
Acknowledge STOP
from the slave.
START command from the master.
Figure 1. I2C Transmission Flow in the RT9945
VSYS
Processor
RT9945
SCL
SDA
SDO
Master
Slave
Figure 2. I2C Function Block in the RT9945
2
I C Address
START
A6
A5
A4
A3
W
A2
A1
A0
0
The 2nd Word
9
0
0
1
D14 D13 D12 D11 D10
0
1
0
D24 D23 D22 D21 D20
0
1
1
D34 D33 D32 D31 D30
STOP
2
Figure 3. I C One Command Flow in the RT9945
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18
DS9945-01 April 2011
RT9945
Table 1. Register Mapping Table (Underline is default)
Bit7 Bit6
0
D1
D2
D3
0
0
0
0
1
0
1
Bit5
Bit4
Bit3
0
0
0
LDO5
LDO4
1
0
1
0
1
Bit2
Bit1
Bit0
Select Group
0
Reserved
Reserved
Reserved
0
0
0
VPROG for LDO4
VPROG for LDO4
Charger
ON/OFF
Z41
Z40
1
OFF
ON
VPROG for
LDO5
OFF
ON
VPROG for
LDO5
Z51
Z50
VPROG for
Buck2
VPROG for
Buck 2
V4
V3
0
VPROG for Buck 2, VPROG for Buck 2
V2
V4
V3
V2
V1
V0
Buck 2 FB
Voltage (V)
0
0
0
0
0
0.5
0
0
0
0
1
0.5125
0
0
0
1
0
0.525
0
0
0
1
1
0.5375
0
0
1
0
0
0.55
0
0
1
0
1
0.5625
0
0
1
1
0
0.575
0
0
1
1
1
0.5875
0
1
0
0
0
0.6
0
1
0
0
1
0.6125
0
1
0
1
0
0.625
0
1
0
1
1
0.6375
0
1
1
0
0
0.65
0
1
1
0
1
0.6625
0
1
1
1
0
0.675 (Default)
0
1
1
1
1
0.6875
1
X[1]
X
X
X
0.7
1
OFF
ON
VPROG for
Buck 2
V1
V0
Z41
0
0
1
1
Z40
0
1
0
1
LDO4 Output Voltage (V)
1.8
2.5 (Default)
2.85
3.3
Z51
0
0
1
1
Z50
0
1
0
1
LDO5 Output Voltage (V)
1.2
1.5
3.0
3.3 (Default)
2
TYPE II : Send address and two commands by I C
(Figure 4).
Note 1 : “X” means don’t care
I2C Address
START
A6 A5 A4 A3 A2 A1 A0
W
0
9
The 2nd Word
0
0
0
x
x
G2 G1 G0
18 G2 : 0 = 3'b000
The 3rd Word
0
1 E15 E14 E13 E12 E11 E10
1
0 E25 E24 E23 E22 E21 E20
27
STOP
STOP
Figure 4. I2C Two Commands Flow in the RT9945
DS9945-01 April 2011
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19
RT9945
Group 0 (Bit2 = 0, Bit1 = 0, Bit0 = 0)
Bit7
Bit6
E1
0
1
E2
1
0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LDO3
LDO2
LDO1
Buck1
Buck2
PWR_EN
0
OFF
1
ON
PWR_IN IN
0
OFF
1
ON
0
OFF
PWR_IN OUT
0
1
0
None Mask None
1
ON
0
OFF
PWR_ID
1
ON
0
OFF
Reserved
1
0
1
Mask None Mask
1
ON
0
None
TIME OUT
CHG DONE
0
1
0
None Mask None
1
1
Mask
1
Mask
I2C Read Command.
The RT9945 reading address set 9D hex and read the
interrupt status from internal register (Figure 5).
2
I C Address
START
g
R
A5 A4 A3 A2 A1 A0
1
9
Read register
B7 B6 B5 B4 B3 B2 B1 B0
18
STOP
Figure 5. I2C Read Command of the RT9945
Table 2. The Default Status of Interrupt Registers for I2C Reading (No PWR_IN)
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Name
PWR_IN
PWR_OUT
PWR_ID
Reserved
Time Out
CHG_DONE
Default
0
1
0
1
0
0
Bit1
Bit0
Reserved
0
0
LDO1 & LDO2 Voltage Setting
Pin S1 and S2 are tri-stat input to set LDO1 and LDO2 voltage. Connect S1 and S2 to VSYS directly to pull high and to
GND to pull low. If S1 and S2 are connected to a voltage that is not equal to VSYS, then S1 and S2 will be floating. The
Voltage setting table is listed in Table 3.
Table 3. LDO1 & LDO2 Voltage Setting
S1
S2
LDO1 (V) LDO2 (V)
L
H
3.3
1.2
H
L
2.8
1.2
H
H
2.5
1.2
L
F
1.8
1.2
F
H
2.5
1.3
F
F
1.8
1.3
H
F
3.3
1.3
F
L
2.5
1.0
L
L
3.0
1.2
Power Sequence
If the PWR_IN and VSYS pin voltages are below the internal UVLO threshold, all IC blocks are disabled and the RT9945
is not operational. When an external power source or battery with voltage greater than the VULO voltage threshold is
applied to VSYS pins, the internal RT9945 references are powered up and biasing internal circuits. When all the main
internal supply rails are active, the RT9945 I2C registers are set to the power-up default values.
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DS9945-01 April 2011
RT9945
VSYS
CLK
DATA
nINT
VMEM VSYS
2
I C
Decoder
Interrupt
Controller
2
I C
Registers
and NonVolatile
Memory
Host
Processor
nPBSTAS
nRESET
PWR_HOLD
PWR_EN
HP_PWR
PWR_ON
Sequencing
& Operating
Mode
Setting
VSYS
System and
Battery
Charger
Control Logic
PWR_IN
BATT
VSYS
Figure 6. Power and Interface Module
If a power good fault is not present at the end of the power good check mode and then NORMAL mode starts. In this mode
of operation, the I2C registers define the RT9945 operation, and must be able to handle all issues regarding power on/off
the handheld device. The following pins and battery voltages determine the power on/off status of the handset :
PWR_ON
PWR_HOLD
Logic high on PWR_ON pin is the normal way of powering up a handset. The PWR_ON signal is held high for at least 320
ms; Buck1, 2 and LDO1, 3 are turned on; when Buck2 reaches 87% of its final value, a 200ms reset timer is started at
after which nRESET is asserted high, and then the handheld device processor is initialized and will assert PWR_HOLD
high to maintain power on. This wrap around constitutes the PWR_ON button can be released (return to low state) and the
power remains on. If, however, PWR_ON is released before the PWR_HOLD signal is asserted, then Buck1, 2 and LDO1,
3 will be turned off. All output could be turned off by the processor asserting PWR_HOLD low, if PWR_ON = Low.
The RT9945's default power output voltages for Samsung platform are listed in Table 4 as following :
Table 4. The RT9945 for Samsung Platform Power Terminology
Buck1
Buck 2
LDO1
LDO2
LDO3
Control Pin
PW R_ON PW R_EN PWR_ON PWR_EN PWR_ON
Default Output
1.8V
1.35V
3.3V
1.2V
1.2V
Voltage
LDO4
I C default Off
LDO5
I C, default Off
2.5V
3.3V
2
2
LDO1, 2 voltage setting by Pin S1 and S2
LDO2 and Buck2 can be turned on by PWR_EN pin.
The I2C will be activated if the Buck1 is enabled.
LDO 1, 2, 3, 4, 5 and Buck 1, 2 output voltages can be turned on and off by I2C.
LDO 4, 5 and Buck2 output voltages can be programmed by I2C.
Sleep Mode
The external host can set the RT9945 in sleep mode using the GPIO configuration. In the sleep mode, change the
PWR_EN signal to set different output on/off status :
1. Buck2 and LDO2 will be disabled when the PWR_EN is turned off to enter the sleep mode.
2. When the PWR_EN is turned on, the Buck2 and LDO2 are enabled and the reset signal from the RT9945 remains high.
DS9945-01 April 2011
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21
RT9945
Interrupt Mode
The RT9945 interruption controller monitors multiple system status parameters and signals to the host when one of the
monitored parameters toggled, as a result of system status change. If the external interrupt event happened, the internal
interrupt flag of the RT9945 will be triggered. The interrupt flag with no mask will set the INT to low state. The host
processor receives the active low signal and then try to read the interrupt register by I2C interface. The interrupt controller
setting and function in register are listed in the Table 5.
Power on
PWR_ON
Normal Mode
Sleep Mode
Power off
320ms
VDD_MEM
BUCK1
LDO1
VDD_IO
100µs
100µs
LDO3
VDD_alive
BUCK2 PG
PWR_EN
VDD_CORE
BUCK2
VDD_PLL
LDO2
LDO4
LDO5
PWR_HOLD
2
I C : LDO4/5_EN
200ms
nRESET
Figure 7. RT9945 POWER ON/OFF Timing Diagram
Table 5. Interrupt Register Table
Register
Name
Default
function
Bit7
PWR_IN
0
Bit6
PWR_OUT
1
If PWR_IN If PWR_IN =
= Hi, this bit Lo, this bit
will be set.
will be set.
INT
Event
Yes
Yes
Bit5
Bit4
PWR_ID Reserved
0
0
If PWR_IN = H
& PWR_ID = H
this bit will be
set
Yes
NO
Bit3
TIME_OUT
0
This bit will
be set if
charger
time out.
Yes
Bit2
Bit1
Bit0
CHG_DONE Reserved Reserved
0
0
0
This bit will
be set if
charge done.
Yes
NO
NO
If this internal interrupt event is set without mask, the interrupt controller will set nINT to low if any interrupt behavior
happened. Then processor will be acknowledged by nINT and then read register status by I2C interface. PMU will accept
this READ OK status and let the nINT return to high (Figure 8).
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DS9945-01 April 2011
RT9945
Interrupt Event
Interrupt Mask = 0
CLK
DATA
READ OK
nINT
Figure 8. Interrupt without Mask
If this internal interrupt register is set with mask, the interrupt controller will not set nINT to low even external real interrupt
event happened (Figure 9).
Interrupt Event
Interrupt Mask = 1
SET MASK = 0
CLK
DATA
READ OK
nINT
Figure 9. Interrupt with Mask
PWR_ON & HP_PWR & nPBSTAS
Connecting external signal such as head phone can start up the power sequence of power management circuit. When the
RT9945 detects a HP_PWR rising edge signal and generates a over 320ms pulse. All RT9945 output will be turned on
even the without recognizing PWR_ON signal. The handheld device processor is initialized and will assert PWR_HOLD to
high to maintain the RT9945 power remains on. This power on behavior is same as PWR_ON signal asserted. nPBSTAS
signal is an inverter of PWR_ON with 320ms de-bounced to inform SOC or uP that power on button has been pressed.
PWR_ON & HP_PWR & nPBSTAS timing control diagram in the Figure 10
PWR_ON
nPBSTAS
Buck1
LDO1
LDO3
nRESET
320ms
Buck2 power good
200ms
PWR_HOLD
Figure 10. PWR_ON & HP_PWR & nPBSTAS Timing Diagram
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23
RT9945
Buck Converters
The RT9945 step-down converters are optimized for high efficiency over a wide load range, small external component
size, low output ripple, and excellent transient response. The DC-DC converters also feature an optimized on-resistance
internal MOSFET switch and synchronous rectifier to maximize the efficiency and minimize the external components.
The RT9945 utilizes a proprietary hysteretic PWM control scheme that switches with nearly fixed frequency, allowing the
customer to trade some efficiency for smaller external component, as desired. If one buck converter is not used, please
make LX = open, FB = IN, and PGND = GND.
VSYS
CIN
Zero-Current ZC
Detection
Current Limit OC
Logic
+
Buffer
+
-
Reference
VREF
L
LX
R1
VOUT
CFF
R2
PGND
COUT
FB
Figure 11. Step-down Converter Block Diagram
Setting the Output Voltage
Select an output voltage between 0.6V and 2.5V by connecting FB to a resistive voltage divider between LX and GND.
Choose R2 for a reasonable bias current in the resistive divider. A wide range of resistor values is acceptable, but a good
starting point is to choose R2 as 100kΩ. Then, R1 is given by :
(
)
VOUT = R1 + 1 × VFB1
R2
Where VFB1 is the feedback reference voltage (0.6V typ.)
Below table is the default value of resistor and CFF for different output voltages.
VBuck (V)
R1 (k)
R2 (k)
CFF (pF)
1.2
100
100
220
1.8
200
100
120
2.5
316
100
120
Inductor Selection
The RT9945 step-down converters operate with inductors of 1μH to 4.7μH. Low inductance values are physically smaller
but require faster switching, which results in some efficiency loss. The inductor's DC current rating only needs to match
the maximum load current of the application because the RT9945 step-down converters feature zero current overshoot
during startup and load transients. The recommended inductor is 2.2μH. For optimum voltage positioning load transients,
choose an inductor with DC series resistance in the 50mΩ to 150mΩ range. For higher efficiency at heavy loads (above
200mA) or minimal load regulation (but some transient overshoot), the resistance should be kept below 100mΩ. For light
load applications up to 200mA, much higher resistance is acceptable with very little impact on performance.
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DS9945-01 April 2011
RT9945
Output Capacitor Selection
The output capacitor, COUT, is required to keep the output voltage ripple small and to ensure the regulation loop stability.
COUT must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their characteristics of small size, low ESR, and small temperature coefficients. Due to the unique
feedback network, the output capacitance can be very low. For most applications, a 4.7μF capacitor is sufficient. For
optimum load-transient performance and very low output ripple, the output capacitor value in μF’s should be equal or
larger than the inductor value in μH's.
Feedforward Capacitor Selection
The feedforward capacitor, CFF, sets the feedback loop response, controls the switching frequency, and is critical in
obtaining the best efficiency possible. Choose a small ceramic X7R capacitor with value given by :
CFF = L × 10
R1
Select the closest standard value to CFF as possible.
Charger
The RT9945 has an integrated charger with power path integrated MOSFETs. This topology, shown in the simplified block
diagram (Figure 12), enables the goal of using an external input power to run the system and charge the battery. The
power path has single inputs that can be used to select either an external AC_DC adapter or USB port by PWR_ID pin and
different charging current by limitation. The RT9945 connect the end equipment main power rail and charge the battery
pack by the BATT pin.
USB/AC
Adapter
PWR_IN
System
Power Bus
Q1
LDO
VSYS
CC/CV
Dynamic
Battery
Supplement
Q2
Battery
BATT
+
Power Path
Control,
nCHG_S System power
and Current
PWR_ID limit selection
Current
Scaling and
Charger
Suspend
Li
NTC
TS
ISETA
RSET
Figure 12. Charger Block Diagram and Required External Components
The RT9945 charger uses current, voltage, and thermal control loops to charge and protect a single Li+ battery cell. One
enable input PWR_ID pin is supplied to set charging current limits. During pre-charge and fast-charge phases, the charger
output status is pulled low. As the battery voltage approaches 4.2V, the charging current is reduced. When the charging
current drops below 10% of charging current setting and the battery voltage equals 4.2V, the nCHG_S output pin goes
high impedance, signaling a full battery and set the internal I2C register bit CHG DONE. If the charger done is not masked,
the interrupt flag will be trigged. At any time during charging, if the RT9945 internal I2C register bit, Charger ON/OFF, is
clear. Then the charger enters suspend mode, charging stops, and nCHG_S goes high impedance.
DS9945-01 April 2011
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25
RT9945
BATTERY CHARGE MANAGEMENT FUNCTION
The RT9945 supports charging of single-cell Li-Ion battery packs. The charge process is executed in three phases: precharge (or preconditioning), constant current and constant voltage. A typical charge profile and flow chart are shown in
Figure 13 & 14.
Precharge
Phase
Fast Charge
Phase
Constant
Voltage Phase
&
Standby Phase
Recharge
Phase
4.2V
Programmed
Charge
Current
4.1V
Recharge
Threshold
1/10 Programmed
Charge Current
2.8V
Precharge
Threshold
Charge
Complete
Figure 13. Typical Charge Profile
UVLO > VIN < OVP
2
& I C = ON &VIN >
BATT
YES
BATT < 4.1V
0.5V < TS < 2.5V
NO
YES
BATT>2.8V
YES
Fast-CHG State
ICHG_fast = 1000mA
@RISET = 1.5kΩ
NO
Power Off State
PFET = OFF
NO
Any State
if VIN < UVLO or
VIN > OVP or
2
I C = OFF or
VIN < BATT
Pre-CHG State
ICHG_pre = 0.1 x
ICHG_fast
Check Thermal NO
Temp.<125°C
Decrease
ICHG_fast
Temp.<125°C
YES
Charge Done State
ICHG = 0A
YES
ICHG<0.1*ICHG_fast
NO
Figure 14. Charge Flow Chat
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DS9945-01 April 2011
RT9945
Power-Path Management
The power path and charge management block operate independently of the other RT9945 circuits. Internal circuits
check battery parameters (pack temperature, battery voltage and charge current) and system parameters, setting the
power path MOSFETs operating modes automatically. The RT9945 has integrated comparators that monitor the battery
voltage, Power input pin voltage and the SYS pin voltage. The data generated by those comparators is used by the power
path control logic to define which of the integrated power path switches is active.
A typical auto power path management profile is shown in Figure 15 & 16.
PWR_IN
5V
SYS 4.65V
4.2V
BATT 4.0V
0V
3A
2A
IBATT
1A
ISYS
0
IPWR_IN
-1A
-2A
-3A
T1
T2
T3
T4
T5
T6
T7
T8
Figure 15. Typical Power Path Management Profile
AC supply SYS
& BATT
SYS > BATT
(T1,T2,T6,T7)
YES
BATT supply
SYS
SYS < BATT
(T8)
ACOK?
NO
ACOK?
NO
YES
AC Current Limit
NO
YES
AC supply SYS &
BATT
Reduce charge
current
SYS = 4.2V > BATT
(T3,T5)
NO
ACOK?
NO
YES
AC Current Limit
YES
SYS Load >
AC Current
Limit
NO
YES
AC & BATT
supply SYS
SYS < BATT
(T4)
NO
Figure 16. Power Path Management Flow Chart
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27
RT9945
The RT9945 powers the system while independently charging the battery. This feature reduces the charge and discharge
cycles on the battery, allows for proper charge termination, and allows the system to run with an absent or defective
battery pack. This feature gives the system priority on input power, allowing the system to power up with a deeply
discharged battery pack. This feature works as follows:
Case 1: AC Mode (PWR_ID = LOW)
In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (Figure 17). The
output SYS is regulated at 5V. If the system load exceeds the capacity of the supply, the output voltage drops down to
the battery's voltage.
When in AC mode, the battery is charged through the switch Q2 based on the charge rate set on the ISETA input pin. This
feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting, or removal
of the input supply. If the voltage on the VSYS pin drops to a preset value (4.2V) due to a limited amount of input current,
then the battery charging current is reduced until the VSYS stops dropping. If the system continues increasing load to
exceed the AC adapter capacity, the battery will start to discharge to VSYS.
Adapter PWR_IN
From adapter
V+
LDO
V+
VSYS
GND
Q1
PWR_ID
ID
GND
Power Path
Control,
System power
and Current
limit selection
Figure 17. RT9945 Powered by AC Adapter
Case 2: USB Mode (PWR_ID = High)
In this case, the system load is powered from a USB port through the internal switch Q1 (Figure 18). Note that in this
case, Q1 regulates the total current to the 450mA level as selected on the input. The output, SYS, is regulated to 5V. The
system's power management is responsible for keeping its system load below the USB current. Otherwise, the output
drops (VSYS) to the battery voltage; therefore, the system should have a low-power mode for USB power application.
USB
USB port
from PC or
Notebook
VBUS
Q1
LDO
VBUS
D+
D-
GND
PWR_IN
VSYS
ID
GND
PWR_ID
Power Path
Control,
System power
and Current
limit selection
Figure 18. RT9945 Powered by USB port
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DS9945-01 April 2011
RT9945
Table 6. PWR_IN Input Current and Charger Current-Limit Selection
PWR_ID
PWR_IN Current Limit
Expected Input Type
Charger Current Limit
Hi
450mA
USB
450mA
Lo
2.3A
AC adapter
(2.5V/Rset)*600
Charge-Current Selection
When powered from a USB port, the input current is available to 0.5A. For AC-Adapter input applications (PWR_ID = Low)
requiring a different current requirement, set the charging current with an external resistor (RSET) from ISETA to GND.
Calculate charge current as follows :
Charge Current = 2.5/ RSET(kΩ) x 600 (mA)
The RT9945 offers ISETA pin to determine the AC charge rate from 100mA to 1A.
Charge-Status Output
nCHG_S is an open-drain output that indicates charger status and can be used with an external LED. nCHG_S goes low
during charging. When VBAT equals 4.2V and the charging current drops below 10% of the setting charge current,
nCHG_S goes high impedance and the RT9945 internal I2C register bit CHG DONE will be set. Connect a pull-up resistor
between nCHG_S and VSYS to indicate charge status.
Soft-Start
To prevent input transients, the change rate of the charge current is limited when the charger is turned on or changes its
current compliance. It takes approximately 1ms for the charger to go from 0mA to the maximum fast-charge current.
VBATT
+
A
ITS
NTC
Temperature
Sense
TS
Battery
0.1µF to 10µF
VTS = RTS × 100μA
Figure 19. Connection of Battery Temperature Monitor
VBATT
+
A
ITS
Temperature
Sense
R × (RT1 + RNTC )
VTS = ITS × T2
RT1 + RT2 + RNTC
TS
RT1
NTC
Battery
0.1µF to 10µF
RT2
Figure 20. Connection of Battery Temperature Monitor
DS9945-01 April 2011
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29
RT9945
Temperature Monitoring
The RT9945 monitors the battery temperature by measuring the voltage between the TS and GND pins. The RT9945 has
an internal current source to provide the bias for most common 10kΩ negative-temperature thermistor (NTC) with the
battery.
The RT9945 compares the voltage on the TS pin against the internal VTS thresholds to determine if charging is allowed.
When the temperature outside the VTS thresholds is detected, the device immediately stops the charger. Charging is
resumed when the VTS is recovered to the operation range. However, the user may modify thresholds by adding external
resistors to change biasing voltage.
Timer
As a safety mechanism, the charger has a user programmable timer that monitors the pre-charge and fast charge time.
This timer (charge safety timer) is started at the beginning of the pre-charge and fast charge period. The safety charge
timeout value is set by the value of an
external capacitor connected to the TIMR pin (CTIMR), if pin TIMR is short to GND, the charge safety timer is disabled.
As CTIMR = 0.1μF, TFAULT is CTIMR (F) x 1.97 x 1011 secs = 19700 secs and TPRECH = TFAULT /8
As timer fault, re-plug-in power or I2C ON/OFF charger again can release the fault condition.
SYS Output
The RT9945 contains a SYS output which can be regulated up to 5V. Bypass SYS to GND with a 22μF or larger ceramic
capacitor to improve the transient droops. When charging a battery, the load on SYS is serviced first and the remaining
available current goes to charge the battery.
Battery PRE-CHARGE
During a charge cycle, if the battery voltage is below the VPRECH threshold and the RT9945 applies a pre-charge mode to
the battery. This feature revives deeply discharged cells and protects battery life. The RT9945 internally determines the
pre-charge rate as 10% of the fast charge current.
Thermal Regulation
The RT9945 features a thermal limit that reduces the charge current when the die temperature exceeds +125°C. As the
temperature increases, the RT9945 features a junction temperature regulation loop. If the power dissipation of the IC
results in a junction temperature greater than the thermal regulation threshold (125°C), the RT9945 throttles back on the
charge current in order to maintain a junction temperature around the thermal regulation threshold (125°C). The RT9945
monitors the junction temperature, TJ, of the die and disconnects the battery from the input if TJ exceeds 125°C. This
operation continues until junction temperature falls below the thermal regulation threshold (125°C) by the hysteresis
level. This feature prevents the maximum power dissipation from exceeding typical design conditions.
Capacitor Selection
Connect a ceramic capacitor from PWR_IN to GND as close to the IC as possible for proper stability. For most applications,
connect a 4.7μF ceramic capacitor from IN to GND as close to the IC as possible.
Linear Regulators
The RT9945 offers five Integrated Linear Regulators, designed to be stable over the operating load range with the use of
external ceramic capacitors.
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DS9945-01 April 2011
RT9945
All the LDO have an ON/OFF control which can be set by I2C commands and have integrated switches that discharge
each output to ground when the LDO is turned off. The LDO 1, 3 will be turn on in the first time of PWR_ON button be
pressed and LDO2 will be turned on when PWR_EN = 1. LDO 4, 5 need to be turned on/off by I2C command. The LDO4,5
also support four voltage setting by I2C control. LDO1 and LDO2 voltages are set by S1 and S2 pin, see Table 3.
Low-Battery Detector
nLBO is an open-drain output that typically connects to the BATT FAULT input of the processor to indicate the battery has
been removed or discharged. nLBO is typically pulled up to VSYS. LBI monitors the input voltage (usually connect to
VSYS) and triggers the nLBO output (Figure 21). nLBO is high impedance when the voltage from LBI exceeds the battery
rising threshold VLBITH = 1.05V (typ.). nLBO is low when the voltage from LBI falls below the low-battery falling threshold
VLBITH = 1V (typ.) (Figure 22). Connecting LBI to two-resistor voltage divider to detect the external resistor embedded in
a battery pack and is also used as a pack ID function.
When system first power up or back from deep sleep mode , LBI will check the VSYS voltage. If VSYS voltage is lower
than setting voltage, system will not power up or wake up.
If the low-battery-detector feature is not required, connect nLBO to ground and connect LBI to SYS.
nLBO
+
VSYS
LBI
SYS
1V
-
LBI
Figure 21. LBI and nLBO Application Circuit
1V
1.05V
nLBO
Figure 22. Typical LBI Rising and Falling Threshold
Voltage
Thermal Considerations
For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation
depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference
between junction to ambient. The maximum power dissipation can be calculated by following formula :
PD(MAX) = ( TJ(MAX) - TA ) / θJA
Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the
junction to ambient thermal resistance.
For recommended operating conditions specification of RT9945, where TJ(MAX) is the maximum junction temperature of
the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout
dependent. For WQFN-40L 5x5 packages, the thermal resistance θJA is 36°C/W on the standard JEDEC 51-7 four layers
thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula :
PD(MAX) = ( 125°C - 25°C) / (36°C/W) = 2.778W for
WQFN-40L 5x5 packages
The maximum power dissipation depends on operating ambient temperature for fixed TJ (MAX) and thermal resistance θJA.
For RT9945 packages, the Figure 23 of derating curves allows the designer to see the effect of rising ambient temperature
on the maximum power allowed.
DS9945-01 April 2011
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31
Maximum Power Dissipation (W)
RT9945
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Four Layers PCB
WQFN-40L 5x5
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 23. Derating Curves for RT9945 Packages
PCB Layout Guide Considerations
For the best performance of the RT9945, the following PCB Layout guidelines must be strictly followed.
` Place the input and output capacitors as close as possible to the input and output pins.
` Keep the main power traces as possible as wide and short.
` To minimize EMI, the switching area connected to LX inductor should be smallest possible.
` Place the feedback components as close as possible to the FB pin and keep these components away from the noisy
devices. Also, the feed forward capacitor CFF trace is sensitive to the magnetic field that the inductor generates. Please
keep the CFF trace away from the inductor and use a via and run the trace between ground layers.
` Connect the GND and Exposed Pad to a strong ground plane for maximum thermal dissipation and noise protection.
GND
GND
CPWR_IN
ISETU
PWR_IN
PWR_IN
PWR_ID
VSYS
VSYS
HP_PWR
PWR_ON
PWR_HOLD
CLK
VSYS
R1
R14
VSYS
1
30
2
29
3
28
4
27
5
6
Place input and output
capacitors (connected to the
ground) as close as possible
to the IC.
25
24
7
8
23
41
9
22
21
10
DATA
BATT
BATT
FB1
PGND1
LX1
VIN1
LX2
PGND2
FB2
VOUT5
nPBSTAS
nRESET
nINT
nLBO
LBI
GND
S2
S1
PWR_EN
C5
R9
R6 R7
VSYS
R4 R5
VSYS
R8
VSYS
GND
CBATT
Buck1
CFF1
R11
R10
L1
CIN1
L2
R13
CBuck1
R12
GND
CBuck2
CFF2
11 12 13 14 15 16 17 18 19 20
C4
high-current path should be
made as short and wide as
possible.
GND
26
GND
Keep the voltage feedback
network very close to the IC,
but away from Inductor & LX.
R13
40 39 38 37 36 35 34 33 32 31
nCHG_S
R2
ISETA
R3
TS
GND C6
TIMER
VOUT2
C2
GND
VIN3
C3
CIN3 VOUT3
VOUT1
C1
VIN2
CIN2
VOUT4
GND
CSYS
Buck2
Connect the inductors, output
capacitors, and feedback resistors
as close to the IC as possible and
keep the traces short, direct, and
wide.
Figure 24. PCB Layout Guide
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DS9945-01 April 2011
RT9945
Outline Dimension
D
SEE DETAIL A
D2
L
1
E2
E
e
A
Dimensions In Millimeters
2
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
4.950
5.050
0.195
0.199
D2
3.250
3.500
0.128
0.138
E
4.950
5.050
0.195
0.199
E2
3.250
3.500
0.128
0.138
e
L
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
A1
Symbol
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
b
A3
1
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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