Ordering number : ENA1885 CMOS IC LC749402PT Silicon gate LCD Picture Quality Improvement IC Overview LC749402PT is a picture quality improvement IC that processes the output signals to the LCD panel for high picture quality display. This IC performs various picture quality adjustments to provide the ideal correction for the display panel. It can support up to WVGA/SVGA panels. * Features (1) Digital input/output • Digital YCbCr/YPbPr 24bit (4:4:4) or 16bit (4:2:2) or 8bit (ITU-R BT.656) signal input • Digital RGB 24bit signal input • Digital RGB 18bit/24bit signal output • Digital YCbCr 16bit (4:2:2)/24bit (4:4:4) signal output (2) Image quality correction • Y image quality correction: luminance adjustment, contour correction, CDEX (Color Depth Expander), dynamic-γ, black/white stretch • C image quality correction: color exciter, flesh tone correction, hue, color gain • RGB image quality correction: brightness, contrast, white balance, black balance, γ correction (3) Panel interface • Built-in panel driver timing controller • Panel protection timing signal generation • Backlight control PWM (video adaptive low power consumption processing) *: The LC749402PT video input should satisfy the following conditions: 40MHz or less operating frequency, 896 dots or less horizontal size, 768 lines or less vertical size. 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D0810HKIM 20101117-S00004 No.A1885-1/10 LC749402PT LSI Specifications • Supply voltage Core: 1.2V I/O: 1.8V/2.85V/3.3V • Maximum operating frequency: 40MHz • Package: TQFP100 Principal Applications • LCD display equipment CDEX (Color Depth Expander) Original CDEX Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS_OSC = 0V Parameter Symbol Maximum supply voltage (I/O) DVDD_IO Maximum supply voltage (core) DVDD_CORE AVDD_OSC Conditions Ratings Unit -0.3 to +3.96 V -0.3 to +1.8 V Digital input voltage VI -0.3 to DVDD_IO+0.3 V Digital output voltage VO -0.3 to DVDD_IO+0.3 V Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Allowable Operating Ranges at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V Ratings Parameter Symbol Conditions unit min Supply voltage (I/O) DVDD_IO Supply voltage (core) DVDD_CORE AVDD_OSC Input voltage range VIN typ max 2.6 2.85 3.6 V 1.7 1.8 1.9 V 1.1 1.2 1.3 V DVDD_IO V 0 No.A1885-2/10 LC749402PT DC Characteristics at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V, DVDD_IO = 1.7V to 1.9V or 2.6V to 3.6V, DVDD_CORE = 1.1V to 1.3V Parameter Symbol Ratings Conditions min Input high-level voltage VIH Input low-level voltage VIL Input high-level current IIH Input low-level current IIL Output high-level voltage VOH typ CMOS level inputs 0.7DVDD_IO CMOS level schmitt inputs 0.7DVDD_IO unit max V V CMOS level inputs 0.3DVDD_IO CMOS level schmitt inputs 0.3DVDD_IO V 10 μA 100 μA VI=DVDD_IO VI=DVDD_IO, with pull-down resistance VI=DVSS CMOS voltage: 2.6V to 3.6V V -10 μA DVDD_IO-0.4 V DVDD_IO-0.45 V Pin D: IOH=-2mA Pin F: IOH=-2mA (when set to 2mA) IOH=-4mA (when set to 4mA) Pin G: IOH=-4mA (when set to 4mA) IOH=-8mA (when set to 8mA) Pin H: IOH=-4mA CMOS voltage: 1.7V to 1.9V Pin D: IOH=-1mA Pin F: IOH=-1mA (when set to 2mA) IOH=-2mA (when set to 4mA) Pin G: IOH=-2mA (when set to 4mA) IOH=-4mA (when set to 8mA) Pin H: IOH=-2mA Output low-level voltage VOL CMOS Output leak current IOZ At output of high-impedance Pull-down resistor RDN DVDD_IO=2.85V DVDD_CORE=1.2V IDDOP 0.4 V 10 μA Typical conditions: Ta=25°C Dynamic supply current -10 98 kΩ 18 mA 57 mA 20 μA Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=10MHz 10 steps Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=40MHz 10 steps Static supply current *1 IDDST Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V Outputs open VI=DVSS or DVDD_IO *1: There is a input terminal which builds in pull down resistance. Please note that there is no guarantee about static consumption current depending on circuit composition. No.A1885-3/10 LC749402PT Package Dimensions unit:mm (typ) 3274 75 0.5 16.0 14.0 51 50 100 26 14.0 16.0 76 1 25 0.2 0.5 0.125 1.2max 0.1 (1.0) (1.0) 80 85 75 5 70 10 65 LC749402PT 15 60 20 55 DGOUT3 DGOUT2 DGOUT1 DVDD_IO DGOUT0 DROUT7 DROUT6 DVSS DROUT5 DROUT4 DROUT3 DVDD_CORE DROUT2 DROUT1 DROUT0 PDWN DVSS DCKO DVDD_IO DHSO/SP2 DVSO/FLM2 DDEO DVSS DEXR POL 50 45 40 35 30 25 DCBIN2 DCBIN3 DCBIN4 DCBIN5 DVDD_CORE DCBIN6 DCBIN7 DDEI DVSI DHSI DVSS OSDBL SCS_I2SEL DCKI SIOSEL XTAL1 DVDD_IO GRST FLM OE DVSS CPV STRB SP DVDD_CORE AVDD_OSC RC_BIAS AVSS_OSC DVSS DCRIN0 DCRIN1 DCRIN2 DCRIN3 DCRIN4 DVDD_CORE DCRIN5 DCRIN6 DCRIN7 DYGIN0 DYGIN1 DVDD_IO DYGIN2 DYGIN3 DYGIN4 DYGIN5 DYGIN6 DVSS DYGIN7 DCBIN0 DCBIN1 90 95 100 Pin Assignment DVDD_IO STXD SRXD_SDA SCK_SCL DVSS TEST INTO XRST DVDD_CORE PWM DBOUT7 DBOUT6 DBOUT5 DVSS DBOUT4 DBOUT3 DBOUT2 DVDD_IO DBOUT1 DBOUT0 DGOUT7 DVSS DGOUT6 DGOUT5 DGOUT4 SANYO : TQFP100(14X14) Top view No.A1885-4/10 PDWN INTO SIOSEL Oscillator STXD SCS_I2SEL XRST SRXD_SDA I²C/SIO TEST BL Control PWM DDEI DCKI SCK_SCL DVSI Panel Protection TCON LTI Dynamic γ W/BL stretch Horizontal Contour OSD Mix Bypass Dither RGB γ Brightness/Contrast White/Black Balance Color Space Convert Color Exciter Color Gain FTI HUE CTI Color Depth Expander DYGIN[7:0] XTALI DCRIN[7:0] Color Space Convert DCBIN[7:0] Timing Controller LC749402PT Block Diagram LC749402PT DYGOUT[7:0] DCBOUT[7:0] Delay DHSI DCROUT[7:0] DHSO DVSO DDEO DCKO GRST FLM OE CPV STRB SP DEXR OSDBL POL PWM MPU No.A1885-5/10 LC749402PT Pin Functions Pin No. Pin symbol In/output format Connecting I/O Format destination Remarks 1 AVDD_OSC P - Core Voltage Analog 2 RC_BIAS I J Resistor Analog 3 AVSS_OSC P - GND Analog 4 DVSS P - GND Digital 5 DCRIN0 I C CMOS Digital R/Cr video input. (LSB Connect to GND when not used.) 6 DCRIN1 I C CMOS Digital R/Cr video input. (Connect to GND when not used.) 7 DCRIN2 I C CMOS Digital R/Cr video input (Connect to GND when not used.) 8 DCRIN3 I C CMOS Digital R/Cr video input (Connect to GND when not used.) 9 DCRIN4 I C CMOS Digital R/Cr video input (Connect to GND when not used.) 10 DVDD_CORE P - Core Voltage Digital 11 DCRIN5 I C CMOS Digital R/Cr video input (Connect to GND when not used.) 12 DCRIN6 I C CMOS Digital R/Cr video input (Connect to GND when not used.) 13 DCRIN7 I C CMOS Digital R/Cr video input (MSB Connect to GND when not used.) 14 DYGIN0 I C CMOS Digital G/Y/656 video input (LSB Connect to GND when not used.) 15 DYGIN1 I C CMOS Digital G/Y/656 video input (Connect to GND when not used.) 16 DVDD_IO P - IO voltage Digital 17 DYGIN2 I C CMOS Digital G/Y/656 video input (Connect to GND when not used.) 18 DYGIN3 I C CMOS Digital G/Y/656 video input (Connect to GND when not used.) 19 DYGIN4 I C CMOS Digital G/Y/656 video input (Connect to GND when not used.) 20 DYGIN5 I C CMOS Digital G/Y/656 video input (Connect to GND when not used.) 21 DYGIN6 I C CMOS Digital G/Y/656 video input (Connect to GND when not used.) 22 DVSS P - GND Digital 23 DYGIN7 I C CMOS Digital G/Y/656 video input (MSB Connect to GND when not used.) 24 DCBIN0 I C CMOS Digital B/Cb/C video (LSB Connect to GND when not used.) 25 DCBIN1 I C CMOS Digital B/Cb/C video input (Connect to GND when not used.) 26 DCBIN2 I C CMOS Digital B/Cb/C video input (Connect to GND when not used.) 27 DCBIN3 I C CMOS Digital B/Cb/C video input (Connect to GND when not used.) 28 DCBIN4 I C CMOS Digital B/Cb/C video input (Connect to GND when not used.) 29 DCBIN5 I C CMOS Digital B/Cb/C video input (Connect to GND when not used.) 30 DVDD_CORE P - Core Voltage Digital 31 DCBIN6 I C CMOS Digital B/Cb/C video input (Connect to GND when not used.) 32 DCBIN7 I C CMOS Digital B/Cb/C video input (MSB Connect to GND when not used.) 33 DDEI I C CMOS Digital Data enable signal. (Connect to GND when not used.) 34 DVSI I C CMOS Digital Vertical sync signal 35 DHSI I C CMOS Digital Horizontal sync signal. 36 DVSS P - GND Digital 37 OSDBL I C CMOS Digital 38 SCS_I2SEL I A CMOS Digital Bias resistor connection (Connect to ground through 20kΩ resistor) Data enable signal for external OSD. (Connect to GND when not used.) SIO chip enable / I2C slave select 39 DCKI I C CMOS Digital Video clock. 40 SIOSEL I C CMOS Digital ”L”: I2C slave, ”H”: 4 wire SIO 41 XTAL1 I C CMOS Digital 42 DVDD_IO P - IO voltage Digital 43 GRST O F CMOS Digital Gate driver reset signal. 44 FLM O F CMOS Digital Start pulse signal for gate driver 45 OE O F CMOS Digital Output enable signal for gate driver. 46 DVSS P - GND Digital 47 CPV O F CMOS Digital Gate driver clock signal. 48 STRB O F CMOS Digital Data strobe signal for source driver. 49 SP O F CMOS Digital Start pulse signal for sourse driver. Extarnal clock input for panel protection. (Connect to GND when not used.) Continued on next page. No.A1885-6/10 LC749402PT Continued from preceding page. Pin No. Pin symbol In/output format Connecting I/O destination Format Remarks 50 DVDD_CORE P - Core Voltage Digital 51 POL O F CMOS Digital 52 DEXR O F CMOS Digital 53 DVSS P - GND Digital 54 DDEO O F CMOS Digital Data enable signal 55 DVSO / FLM2 O F CMOS Digital Vertical sync signal / Start pulse signal for gate driver 56 DHSO / SP2 O F CMOS Digital Horizontal sync signal / Start pulse signal for sourse driver 57 DVDD_IO P - IO voltage Digital 58 DCKO O G CMOS Digital 59 DVSS P - GND Digital 60 PDWN I A CMOS Digital “H” power down control (Connect to GND when not used.) 61 DROUT0 O F CMOS Digital R/Cr video output (LSB when 8-bit output is selected) 62 DROUT1 O F CMOS Digital R/Cr video output 63 DROUT2 O F CMOS Digital R/Cr video output (LSB when 6-bit output is selected) 64 DVDD_CORE P - Core Voltage Digital 65 DROUT3 O F CMOS Digital R/Cr video output 66 DROUT4 O F CMOS Digital R/Cr video output 67 DROUT5 O F CMOS Digital R/Cr video output Voltage polarity selection signal for the source driver. Reversed video signal output for DTR. Low output when the DTR is OFF. Video clock output 68 DVSS P - GND Digital 69 DROUT6 O F CMOS Digital R/Cr video output 70 DROUT7 O F CMOS Digital R/Cr video output (MSB) 71 DGOUT0 O F CMOS Digital G/Y video output (LSB when 8-bit output is selected) 72 DVDD_IO P - IO voltage Digital 73 DGOUT1 O F CMOS Digital G/Y video output 74 DGOUT2 O F CMOS Digital G/Y video output (LSB when 6-bit output is selected) 75 DGOUT3 O F CMOS Digital G/Y video output 76 DGOUT4 O F CMOS Digital G/Y video output 77 DGOUT5 O F CMOS Digital G/Y video output 78 DGOUT6 O F CMOS Digital G/Y video output 79 DVSS P - GND Digital 80 DGOUT7 O F CMOS Digital G/Y video output (MSB) 81 DBOUT0 O F CMOS Digital B/Cb/C video output (LSB when 8-bit output is selected) 82 DBOUT1 O F CMOS Digital B/Cb/C video output 83 DVDD_IO P - IO voltage Digital 84 DBOUT2 O F CMOS Digital B/Cb/C video output (LSB when 6-bit output is selected) 85 DBOUT3 O F CMOS Digital B/Cb/C video output 86 DBOUT4 O F CMOS Digital B/Cb/C video output 87 DVSS P - GND Digital 88 DBOUT5 O F CMOS Digital B/Cb/C video output 89 DBOUT6 O F CMOS Digital B/Cb/C video output 90 DBOUT7 O F CMOS Digital B/Cb/C video output (MSB) 91 PWM O D CMOS Digital Pulse width modulation waveform output 92 DVDD_CORE P - Core Voltage Digital 93 XRST I A CMOS Digital System reset (“L” reset) 94 INTO O D CMOS Digital Interrupt 95 TEST I B CMOS Digital Test setting (Connect to GND normally) 96 DVSS P - GND Digital 97 SCK_SCL I C CMOS Digital Bus clock (shared with SIO/I2C) 98 SRXD_SDA I/O H CMOS Digital SIO data input / I2C data input/output 99 STXD O D CMOS Digital SIO data 100 DVDD_IO P - IO voltage Digital No.A1885-7/10 LC749402PT Pin Type In/Output form Function Schmitt trigger Equivalent circuit Application Terminal XRST, PDWN, SCS_I2SEL CMOS input A CMOS input with built-in TEST pull-down resistor B CMOS input SCK_SCL, SIOSEL, DVSI, DHSI, DDEI, OSDBL, DYGIN7, DYGIN6, DYGIN5, DYGIN4, DYGIN3, DYGIN2, DYGIN1, DYGIN0, C DCBIN7, DCBIN6, DCBIN5, DCBIN4, DCBIN3, DCBIN2, DCBIN1, DCBIN0, DCRIN7, DCRIN6, DCRIN5, DCRIN4, DCRIN3, DCRIN2, DCRIN1, DCRIN0 2mA 3-STATE drive STXD, PWM, INTO CMOS output D 2mA/4mA switching DBOUT7, DBOUT6, DBOUT5, DBOUT4, 3-STATE drive DBOUT3, DBOUT2, DBOUT1, DBOUT0, CMOS output DROUT7, DROUT6, DROUT5, DROUT4, DROUT3, DROUT2, DROUT1, DROUT0 F DGOUT7, DGOUT6, DGOUT5, DGOUT4, DGOUT3, DGOUT2, DGOUT1, DGOUT0, DHSO/SP2, DVSO/FLM2, DDEO FLM, DEXR, POL, GRST, CPV, SP, OE, STRB 4mA/8mA switching DCKO 3-STATE drive CMOS output G 4mA 3-STATE drive SRXD_SDA CMOS input/output H Analog input/output RC_BIAS J No.A1885-8/10 LC749402PT I/O Timing (1) Input data timing tCK tHI DVDD_IO/2 DCKI tSU tLI tHD DVDD_IO/2 Input data Pin name Parameter Symbol Clock cycle DCKI min tCK typ 50 (DVDD_IO=2.6 to 3.6V) DCBIN*, DVSI, DHSI, DDEI, OSDBL unit ns Duty Input data setup time DCRIN*, DYGIN*, max 25 Input data setup time (DVDD_IO=1.7 to 1.9V) Input data hold time (DVDD_IO=2.6 to 3.6V) Input data hold time (DVDD_IO=1.7 to 1.9V) % tSU 3 ns tSU 3 ns tHD 2 ns tHD 2 ns *: The recommended duty cycle of input clock is 50% (2) Output data timing tHO tCK DVDD_IO/2 DCKO tAC tLO DVDD_IO/2 Output data Pin name DCKO Parameter Clock cycle Symbol tCK min typ max unit 25 Duty ns 50 % Output data delay time (DVDD_IO=2.6 to 3.6V) Pin F: when set to 4mA tAC -3 3 ns tAC -3 6 ns tAC -5 4 ns tAC -6 9 ns Pin G: when set to 8mA Output data delay time DROUT*, DGOUT*, DBOUT*, DVSO, DHSO, DDEO, DEXR, POL, SP, STRB, CPV, OE, FLM, GRST (DVDD_IO=2.6 to 3.6V) Pin F: when set to 2mA Pin G: when set to 4mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 4mA Pin G: when set to 8mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 2mA Pin G: when set to 4mA * When DCKO is set to the forward rotation output. Output load capacity: 5pF No.A1885-9/10 LC749402PT SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2010. Specifications and information herein are subject to change without notice. PS No.A1885-10/10