Ordering number : ENA1618 CMOS IC LC749402BG Silicon gate LCD Picture Quality Improvement IC Overview LC749402BG is a picture quality improvement IC that processes the output signals to the LCD panel for high picture quality display. This IC performs various picture quality adjustments to provide the ideal correction for the display panel. It can support up to WVGA/SVGA panels. * Features (1) Digital input/output • Digital YCbCr/YPbPr 24bit (4:4:4) or 16bit (4:2:2) or 8bit(ITU-R BT.656) signal input • Digital RGB 24bit signal input • Digital RGB 18bit/24bit signal output • Digital YCbCr16bit (4:2:2)/24bit (4:4:4) signal output (2) Image quality correction • Y image quality correction: luminance adjustment, contour correction, CDEX (Color Depth Expander), dynamic-γ, black/white stretch • C image quality correction: color exciter, flesh tone correction, hue, color gain • RGB image quality correction: brightness, contrast, white balance, black balance, γ correction (3) Panel interface • Built-in panel driver timing controller • Panel protection timing signal generation • Backlight control PWM (video adaptive low power consumption processing) *: The LC749402BG video input should satisfy the following conditions: 40MHz or less operating frequency, 896 dots or less horizontal size, 768 lines or less vertical size. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 12710HKIM 20091026-S00005 No.A1618-1/11 LC749402BG LSI Specifications • Supply voltage Core: 1.2V I/O: 1.8V/2.85V/3.3V • Maximum operating frequency: 40MHz • Package: FBGA96 Principal Applications • LCD display equipment CDEX (Color Depth Expander) Original CDEX Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS_OSC = 0V Parameter Symbol Maximum supply voltage (I/O) DVDD_IO Maximum supply voltage (core) DVDD_CORE Conditions Ratings Unit -0.3 to +3.96 V -0.3 to +1.8 V V AVDD_OSC Digital input voltage VI -0.3 to DVDD_IO+0.3 Digital output voltage VO -0.3 to DVDD_IO+0.3 V Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Allowable Operating Ranges at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V Ratings Parameter Symbol Conditions unit min Supply voltage (I/O) DVDD_IO Supply voltage (I/O) DVDD_CORE AVDD_OSC Input voltage range VIN typ max 2.6 2.85 3.6 V 1.7 1.8 1.9 V 1.0 1.2 1.3 V DVDD_IO V 0 No.A1618-2/11 LC749402BG DC Characteristics at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V, DVDD_IO = 1.7V to 1.9V or 2.6V to 3.6V, DVDD_CORE = 1.0V to 1.3V Parameter Symbol Ratings Conditions min Input high-level voltage VIH Input low-level voltage VIL Input high-level current IIH Input low-level current IIL Output high-level voltage VOH typ CMOS level inputs 0.7DVDD_IO CMOS level Schmitt inputs 0.7DVDD_IO unit max V V CMOS level inputs 0.3DVDD_IO CMOS level Schmitt inputs 0.3DVDD_IO V 10 μA 100 μA VI=DVDD_IO VI=DVDD_IO, with pull-down resistance VI=DVSS CMOS voltage: 2.6V to 3.6V V -10 μA DVDD_IO-0.4 V DVDD_IO-0.45 V Pin D: IOH=-2mA Pin F: IOH=-2mA (when set to 2mA) IOH=-4mA (when set to 4mA) Pin G: IOH=-4mA (when set to 4mA) IOH=-8mA (when set to 8mA) Pin H: IOH=-4mA CMOS voltage: 1.7V to 1.9V Pin D: IOH=-1mA Pin F: IOH=-1mA (when set to 2mA) IOH=-2mA (when set to 4mA) Pin G: IOH=-2mA (when set to 4mA) IOH=-4mA (when set to 8mA) Pin H: IOH=-2mA Output low-level voltage VOL CMOS Output leak current IOZ At output of high-impedance Pull-down resistor RDN DVDD_IO=2.85V IDDOP 0.4 V 10 μA Typical conditions: Ta=25°C Dynamic supply current -10 98 kΩ 18 mA 57 mA 20 μA DVDD_CORE=1.2V Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=10MHz 10 steps Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=40MHz 10 steps Static supply current *1 IDDST Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V Outputs open VI=DVSS or DVDD_IO *1: There is a input terminal which builds in pull down resistance. Please note that there is no guarantee about static consumption current depending on circuit composition. No.A1618-3/11 LC749402BG Package Dimensions FBGA96 unit:mm (typ) 3387 TOP VIEW BOTTOM VIEW SIDE VIEW 6.0 0.75 0.5 6.0 0.75 1 2 3 4 5 6 7 8 9 10 0.5 K J H GF E D C B A 1.05 MAX 0.1 SIDE VIEW 0.29 SANYO : ISB96(6.0X6.0) Pin Assignment LC749402BG 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K Top view No.A1618-4/11 PDWN INTO SIOSEL Oscillator STXD SCS_I2SEL XRST SCK_SCL I²C/SIO TEST BLCON PWM DDEI DCKI SRXD_SDA DVSI Panel protection TCON LTI Dynamic γ W/BL stretch Horizontal contour OSD Mix delay DHSI Bypass Dither RGB γ Brightness/contrast White/black balance Color Space Convert Color Exciter Color Gain FTI HUE CTI Color Depth Expander DYGIN[7:0] XTALI DCRIN[7:0] Color Space Convert DCBIN[7:0] Timing controller LC749402BG Block Diagram LC749402BG DYGOUT[7:0] DCBOUT[7:0] DCROUT[7:0] DHSO DVSO DDEO DCKO GRST FLM OE CPV STRB SP DEXR OSDBL POL PWM MPU No.A1618-5/11 LC749402BG Pin Functions Pin No. A1 Pin symbol AVDD_OSC In/output format Connecting I/O Format destination P - Core voltage Remarks Analog Connect this pin to B2 without fail. A2 STXD O D CMOS Digital SIO data A3 SCK_SCL I C CMOS Digital Bus clock (common to SIO and I2C) A4 DBOUT7 O F CMOS Digital B/Cb/C video (MSB) A5 DBOUT4 O F CMOS Digital B/Cb/C video A6 DBOUT1 O F CMOS Digital B/Cb/C video A7 DGOUT6 O F CMOS Digital G/Y video A8 DGOUT4 O F CMOS Digital G/Y video A9 DGOUT3 O F CMOS Digital G/Y video A10 DVDD_IO P - IO voltage Digital Connect this pin to B9 without fail B1 RC_BIAS I J resistor Analog B2 AVDD_OSC P - Core voltage Analog B3 SRXD_SDA I/O H CMOS Digital SIO data input/I2C data I/O B4 PWM O D CMOS Digital Pulse width modulation waveform B5 DBOUT5 O F CMOS Digital B/Cb/C video B6 DBOUT2 O F CMOS Digital B/Cb/C video (6-bit output mode, LSB) B7 DGOUT7 O F CMOS Digital G/Y video (MSB) B8 DGOUT5 O F CMOS Digital G/Y video B9 DVDD_IO P - IO voltage Digital B10 DGOUT2 O F CMOS Digital G/Y video (6-bit output mode, LSB) C1 DCRIN0 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. C2 DCRIN1 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. C3 AVSS_OSC P - GND Analog C4 INTO O D CMOS Digital Interrupt C5 DBOUT6 O F CMOS Digital B/Cb/C video C6 DBOUT3 O F CMOS Digital B/Cb/C video C7 DBOUT0 O F CMOS Digital B/Cb/C video (8-bit output mode, LSB) C8 DVDD_IO P - IO voltage Digital C9 DGOUT1 O F CMOS Digital C10 DGOUT0 O F CMOS Digital G/Y video (8-bit output mode, LSB) D1 DCRIN2 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. D2 DCRIN3 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. D3 DCRIN4 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. D4 TEST I B CMOS Digital Test (Normally, connect this pin to GND) D5 XRST I A CMOS Digital System reset (“L” reset) D6 DVDD_IO P - IO voltage Digital D7 DVDD_IO P - IO voltage Digital D8 DROUT7 O F CMOS Digital R/Cr video (MSB) Bias resistor connection (Connect this pin to GND with a 20kΩ) G/Y video D9 DROUT6 O F CMOS Digital R/Cr video D10 DROUT5 O F CMOS Digital R/Cr video Continued on next page. No.A1618-6/11 LC749402BG Continued from preceding page. Pin No. Pin symbol In/output format Connecting I/O Format destination Remarks E1 DCRIN5 I C CMOS Digital E2 DCRIN6 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. R/Cr video (MSB). E3 DCRIN7 I C CMOS Digital E4 DVSS P - GND Digital E7 PDWN I A CMOS Digital E8 DROUT4 O F CMOS Digital R/Cr video E9 DROUT3 O F CMOS Digital R/Cr video E10 DROUT2 O F CMOS Digital Connect this pin to GND when not to be used. “H” power down. Connect this pin to GND when not to be used. R/Cr video (6-bit output mode, LSB) G/Y/656 video (LSB). F1 DYGIN0 I C CMOS Digital F2 DYGIN1 I C CMOS Digital F3 DYGIN2 I C CMOS Digital F4 DVSS P - GND Digital F7 DVDD_CORE P - Core voltage Digital F8 DROUT1 O F CMOS Digital F9 DROUT0 O F CMOS Digital R/Cr video (8-bit output mode, LSB) F10 DCKO O G CMOS Digital Video clock G1 DYGIN3 I C CMOS Digital G2 DYGIN4 I C CMOS Digital G3 DYGIN5 I C CMOS Digital G4 DVSS P - GND Digital G5 SCS_I2SEL I A CMOS Digital SIO chip enable/I2C slave address switching G6 SIOSEL I C CMOS Digital “L”: I2C slave, ”H”: 4-wire SIO G7 DVDD_CORE P - Core voltage Digital G8 DHSO/SP2 O F CMOS Digital G9 DVSO/FLM2 O F CMOS Digital G10 DDEO O F CMOS Digital H1 DYGIN6 I C CMOS Digital H2 DYGIN7 I C CMOS Digital H3 DVSS P - GND H4 DCBIN6 I C CMOS Digital H5 DVSI I C CMOS Digital H6 OSDBL I C CMOS Digital H7 FLM O F CMOS Digital H8 DVDD_CORE P - Core voltage Digital H9 DEXR O F CMOS Digital H10 POL O F CMOS Digital Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. R/Cr video G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. Horizontal synchronizing signal/start pulse signal for source driver Vertical synchronizing signal/start pulse signal for gate driver Data enable signal G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video (MSB). Connect this pin to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. Vertical synchronizing signal Data enable signal for external OSD. Connect this pin to GND when not to be used. Start pulse signal for gate driver Reversed video signal output for DTR. Low output when the DTR is OFF. Voltage polarity selection signal for source driver Continued on next page. No.A1618-7/11 LC749402BG Continued from preceding page. Pin No. Pin symbol In/output format Connecting I/O Format destination Remarks J1 DCBIN0 I C CMOS Digital J2 DVSS P - GND Digital J3 DCBIN3 I C CMOS Digital J4 DCBIN5 I C CMOS Digital J5 DDEI I C CMOS Digital B/Cb/C video (LSB). Connect to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. Data enable signal, Connect this pin to GND in the internal generation mode J6 DHSI I C CMOS Digital Horizontal synchronizing signal J7 GRST O F CMOS Digital Reset signal for gate driver J8 CPV O F CMOS Digital Clock signal for gate driver J9 DVDD_CORE P - Core voltage Digital J10 SP O F CMOS Digital Start pulse signal for source driver K1 DVSS P - GND Analog Connect this pin to J2 without fail K2 DCBIN1 I C CMOS Digital K3 DCBIN2 I C CMOS Digital K4 DCBIN4 I C CMOS Digital K5 DCBIN7 I C CMOS Digital K6 DCKI I C CMOS Digital B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video (MSB). Connect this pin to GND when not to be used. Video clock Panel protection, PWM generation clock. K7 XTAL1 I C CMOS Digital K8 OE O F CMOS Digital Output enable signal for gate driver K9 STRB O F CMOS Digital Data strobe signal for source driver K10 DVDD_CORE P - Core voltage Digital Connect this pin to J9 without fail Connect this pin to GND when not to be used. No.A1618-8/11 LC749402BG Pin Type In/Output form Function Schmitt trigger Equivalent circuit Application Terminal XRST, PDWN, SCS_I2SEL CMOS input A CMOS input with built-in TEST pull-down resistor B CMOS input SCK_SCL, SIOSEL, DVSI, DHSI, DDEI, OSDBL, DYGIN7, DYGIN6, DYGIN5, DYGIN4, DYGIN3, DYGIN2, DYGIN1, DYGIN0, C DCBIN7, DCBIN6, DCBIN5, DCBIN4, DCBIN3, DCBIN2, DCBIN1, DCBIN0, DCRIN7, DCRIN6, DCRIN5, DCRIN4, DCRIN3, DCRIN2, DCRIN1, DCRIN0 2mA 3-STATE drive STXD, PWM, INTO CMOS output D 2mA/4mA switching DBOUT7, DBOUT6, DBOUT5, DBOUT4, 3-STATE drive DBOUT3, DBOUT2, DBOUT1, DBOUT0, CMOS output DROUT7, DROUT6, DROUT5, DROUT4, DROUT3, DROUT2, DROUT1, DROUT0 F DGOUT7, DGOUT6, DGOUT5, DGOUT4, DGOUT3, DGOUT2, DGOUT1, DGOUT0, DHSO/SP2, DVSO/FLM2, DDEO FLM, DEXR, POL, GRST, CPV, SP, OE, STRB 4mA/8mA switching DCKO 3-STATE drive CMOS output G 4mA 3-STATE drive SRXD_SDA CMOS input/output H Analog input/output RC_BIAS J No.A1618-9/11 LC749402BG I/O Timing (1) Input data timing tHI tCK DVDD_IO/2 DCKI tSU tLI tHD DVDD_IO/2 Input data Pin name Parameter Symbol Clock cycle DCKI min tCK typ 50 Input data setup time (DVDD_IO=2.6 to 3.6V) DCBIN*, DVSI, DHSI, DDEI, OSDBL unit ns Duty DCRIN*, DYGIN*, max 25 Input data setup time (DVDD_IO=1.7 to 1.9V) Input data hold time (DVDD_IO=2.6 to 3.6V) Input data hold time (DVDD_IO=1.7 to 1.9V) % tSU 3 ns tSU 3 ns tHD 2 ns tHD 2 ns *: The recommended duty cycle of input clock is 50% (2) Output data timing tHO tCK DVDD_IO/2 DCKO tAC tLO DVDD_IO/2 Output data Pin name DCKO Parameter Clock cycle Symbol tCK min typ max unit 25 Duty ns 50 % Output data delay time (DVDD_IO=2.6 to 3.6V) Pin F: when set to 4mA tAC -3 3 ns tAC -3 6 ns tAC -5 4 ns tAC -6 9 ns Pin G: when set to 8mA Output data delay time (DVDD_IO=2.6 to 3.6V) DROUT*, DGOUT*, DBOUT*, DVSO, DHSO, DDEO, DEXR, POL, SP, STRB, CPV, OE, FLM, GRST Pin F: when set to 2mA Pin G: when set to 4mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 4mA Pin G: when set to 8mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 2mA Pin G: when set to 4mA * When DCKO is set to the forward rotation output. Output load capacity: 5pF No.A1618-10/11 LC749402BG SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2010. Specifications and information herein are subject to change without notice. PS No.A1618-11/11