SYNC-POWER SPP3052_11

SPP3052
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP3052 is the P-Channel logic enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage application, such as
DC/DC converter and Desktop computer power
management.
The package is universally preferred for commercial
industrial surface mount applications
APPLICATIONS
z Power Management in Desktop Computer
z DC/DC Converter
z LCD Display inverter
FEATURES
‹
-30V/- 25A,RDS(ON)=50mΩ@VGS=-10V
‹
-30V/- 16A,RDS(ON)=85mΩ@VGS=- 5V
‹
Super high density cell design for extremely low
RDS (ON)
‹
Exceptional on-resistance and maximum DC
current capability
‹
TO-252-2L package design
PIN CONFIGURATION ( TO-252-2L )
PART MARKING
2011/09/22 Ver.4
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SPP3052
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
Symbol
Description
1
G
Gate
2
S
3
D
Source
Drain
ORDERING INFORMATION
Part Number
Package
Part
Marking
SPP3052T252RG
TO-252-2L
SPP3052
SPP3052T252RGB
TO-252-2L
SPP3052
※ Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※ SPP3052T252RG : Tape Reel ; Pb – Free
※ SPP3052T252RGB : Tape Reel ; Pb – Free ; Halogen - Free
ABSOULTE MAXIMUM RATINGS
(TA=25℃ Unless otherwise noted)
Parameter
Symbol
Typical
Unit
Drain-Source Voltage
VDSS
-30
V
Gate –Source Voltage
VGSS
±20
V
Continuous Drain Current(TJ=150℃)
TA=25℃
TA=70℃
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
TA=25℃
TA=70℃
Avalanche Energy with Single Pulse
( Tj=25℃, L = 0.14mH , IAS = 43A , VDD = 20V. )
ID
-25
-18
A
IDM
-100
A
IS
-15
A
PD
40
20
W
EAS
129
mJ
TJ
-55/150
℃
Storage Temperature Range
TSTG
-55/150
℃
Thermal Resistance-Junction to Ambient
RθJA
105
℃/W
Operating Junction Temperature
2011/09/22 Ver.4
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SPP3052
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(TA=25℃ Unless otherwise noted)
Parameter
Symbol
Conditions
Min.
Typ
Max.
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
V(BR)DSS VGS=0V,ID=-250uA
VGS(th) VDS=VGS,ID=-250uA
Gate Leakage Current
IGSS
Forward Transconductance
gfs
VDS=0V,VGS=±20V
VDS=-21V,VGS=0V
VDS=-21V,VGS=0V
TJ=55℃
VGS=-10V,ID=-25A
VGS=- 5V,ID=-16A
VDS=-10V,ID=-8A
Zero Gate Voltage Drain Current
IDSS
Diode Forward Voltage
VSD
IS=-16A,VGS =0V
Drain-Source On-Resistance
RDS(on)
-30
-1.0
-3.0
±100
-2
-5
0.040
0.068
8
0.050
0.085
-0.8
-1.2
16
24
V
nA
uA
Ω
S
V
Dynamic
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-On Time
Turn-Off Time
2011/09/22 Ver.4
VDS=-15V,VGS=-10V
ID= -3.5A
4.5
VDS=-15V,VGS=0V
f=1MHz
td(on)
tr
td(off)
tf
nC
2.3
VDD=-15V,RL=15Ω
ID≡-1.0A,VGEN=-10V
RG=6Ω
680
pF
120
75
14
25
15
26
42
70
30
50
ns
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SPP3052
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2011/09/22 Ver.4
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SPP3052
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2011/09/22 Ver.4
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SPP3052
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2011/09/22 Ver.4
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SPP3052
P-Channel Enhancement Mode MOSFET
TO-252-2L PACKAGE OUTLINE
2011/09/22 Ver.4
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SPP3052
P-Channel Enhancement Mode MOSFET
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2011/09/22 Ver.4
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