54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks General Description The ’F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Commercial Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Features Y Guaranteed 4000V minimum ESD protection Package Number Military 74F193PC 54F193DM (Note 2) 74F193SC (Note 1) Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F193FM (Note 2) W16A 16-Lead Cerpack 54F193LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F193SJ (Note 1) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9497–1 IEEE/IEC TL/F/9497 – 2 TL/F/9497 – 3 TL/F/9497–4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9497 RRD-B30M75/Printed in U. S. A. 54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks November 1994 Unit Loading/Fan Out 54F/74F Pin Names CPU CPD MR PL P0 – P3 Q0 – Q3 TCD TCU Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output (Active LOW) Terminal Count Up (Carry) Output (Active LOW) 1.0/3.0 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3 20 mA/b1.8 mA 20 mA/b1.8 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA b 1 mA/20 mA b 1 mA/20 mA Functional Description If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. The ’F193 is a 4-bit binary synchronous up/down (reversible) counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH, as indicated in the Function Table. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state 15, the next HIGH-toLOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. TCU e Q0 # Q1 # Q2 # Q3 # CPU Function Table MR PL CPU CPD Mode H L L L L X L H H H X X H L H X X H H L Reset (Asyn.) Preset (Asyn.) No Change Count Up Count Down H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition State Diagram TCD e Q0 # Q1 # Q2 # Q3 # CPD The ’F193 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data input (P0 – P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both clock inputs, and latch each Q output in the LOW state. TL/F/9497 – 5 2 Logic Diagram TL/F/9497 – 6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA 0.5 0.5 V Min IOL e 20 mA IOL e 20 mA 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.8 mA Max VIN e 0.5V (MR, PL, Pn) VIN e 0.5V (CPu, CPD) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICC Power Supply Current 55 mA Max 2.5 2.5 2.7 4.75 b 60 38 4 Recognized as a LOW Signal AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Typ fmax Maximum Count Frequency 100 125 tPLH tPHL Propagation Delay CPU or CPD to TCU or TCD 4.0 3.5 7.0 6.0 9.0 8.0 4.0 3.5 10.5 9.5 4.0 3.5 10.0 9.0 tPLH tPHL Propagation Delay CPU or CPD to Qn 4.0 5.5 6.5 9.5 8.5 12.5 3.5 5.5 10.0 14.0 4.0 5.5 9.5 13.5 ns tPLH tPHL Propagation Delay Pn to Qn 3.0 6.0 4.5 11.0 7.0 14.5 3.0 6.0 8.5 16.5 3.0 6.0 8.0 15.5 ns tPLH tPHL Propagation Delay PL to Qn 5.0 5.5 8.5 10.0 11.0 13.0 5.0 5.5 13.5 15.0 5.0 5.5 12.0 14.0 ns tPHL Propagation Delay MR to Qn 5.5 11.0 14.5 5.0 16.0 5.5 15.5 tPLH Propagation Delay MR to TCU 6.0 10.5 13.5 5.0 15.0 6.0 14.5 tPHL Propagation Delay MR to TCD 6.0 11.5 14.5 6.0 16.0 6.0 15.5 tPLH tPHL Propagation Delay PL to TCU or TCD 7.0 7.0 12.0 11.5 15.5 14.5 7.0 6.0 18.5 17.5 7.0 7.0 16.5 15.5 ns tPLH tPHL Propagation Delay Pn to TCU or TCD 7.0 6.5 11.5 11.0 14.5 14.0 6.0 5.0 16.5 16.5 7.0 6.5 15.5 15.0 ns 75 Min Units Max 90 MHz ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Pn to PL 4.5 4.5 6.0 6.0 5.0 5.0 th(H) th(L) Hold Time, HIGH or LOW Pn to PL 2.0 2.0 2.0 2.0 2.0 2.0 tw(L) PL Pulse Width, LOW 6.0 7.5 6.0 ns tw(L) CPU or CPD Pulse Width, LOW 5.0 7.0 5.0 ns tw(L) CPU or CPD Pulse Width, LOW (Change of Direction) 10.0 12.0 10.0 ns tw(H) MR Pulse Width, HIGH 6.0 6.0 6.0 ns trec Recovery Time PL to CPU or CPD 6.0 8.0 6.0 ns trec Recovery Time MR to CPU or CPD 4.0 4.5 4.0 ns 5 ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 193 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code Plastic DIP Pe Ceramic DIP De Flatpak Fe Le Leadless Chip Carrier (LCC) Se Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 6 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 16-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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