54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock General Description Features The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting. The preset feature allows the ’F191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. Commercial Y Y Y Y High-SpeedÐ125 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Package Number Military 74F191PC 54F191DM (Note 2) Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line 74F191SC (Note 1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC 74F191SJ (Note 1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F191FM (Note 2) W16A 16-Lead Cerpack 54F191LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9495–1 IEEE/IEC TL/F/9495 – 2 TL/F/9495 – 3 TL/F/9495–4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9495 RRD-B30M75/Printed in U. S. A. 54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock November 1994 Unit Loading/Fan Out 54F/74F Pin Names CE CP P0 – P3 PL U/D Q0 – Q3 RC TC Description Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Asynchronous Parallel Load Input (Active LOW) Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output (Active LOW) Terminal Count Output (Active HIGH) U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3 20 mA/b1.8 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA b 1 mA/20 mA b 1 mA/20 mA Functional Description A method of causing state changes to occur simultaneously in all stages is shown in Figure 2 . All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figures 1 and 2 doesn’t apply, because the TC output of a given stage is not affected by its own CE. The ’F191 is a synchronous up/down 4-bit binary counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the countdown mode or reaches 15 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figures 1 and 2. In Figure 1 , each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. Mode Select Table Inputs Mode PL CE U/D CP H H L H L L X H L H X X L L X X Count Up Count Down Preset (Asyn.) No Change (Hold) RC Truth Table Inputs TC* CP RC L H X H X L ß X X ß H H *TC is generated internally H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition ß e LOW Pulse 2 Output CE Logic Diagram TL/F/9495 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. TL/F/9495 – 6 FIGURE 1. n-Stage Counter Using Ripple Clock TL/F/9495 – 7 FIGURE 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow TL/F/9495 – 8 FIGURE 3. Synchronous n-Stage Counter with Gated Carry/Borrow 3 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA 0.5 0.5 V Min IOL e 20 mA IOL e 20 mA 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA, All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.8 mA Max VIN e 0.5V (except CE) VIN e 0.5V (CE) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICC Power Supply Current 55 mA Max 2.5 2.5 2.7 4.75 b 60 38 4 Recognized as a LOW Signal AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Typ fmax Maximum Count Frequency 100 125 tPLH tPHL Propagation Delay CP to Qn 3.0 5.0 5.5 8.5 7.5 11.0 3.0 5.0 9.5 13.5 3.0 5.0 8.5 12.0 tPLH tPHL Propagation Delay CP to TC 6.0 5.0 10.0 8.5 13.0 11.0 6.0 5.0 16.5 13.5 6.0 5.0 14.0 12.0 tPLH tPHL Propagation Delay CP to RC 3.0 3.0 5.5 5.0 7.5 7.0 3.0 3.0 9.5 9.0 3.0 3.0 8.5 8.0 tPLH tPHL Propagation Delay CE to RC 3.0 3.0 5.0 5.5 7.0 7.0 3.0 3.0 9.0 9.0 3.0 3.0 8.0 8.0 tPLH tPHL Propagation Delay U/D to RC 7.0 5.5 11.0 9.0 18.0 12.0 7.0 5.5 22.0 14.0 7.0 5.5 20.0 13.0 tPLH tPHL Propagation Delay U/D to TC 4.0 4.0 7.0 6.5 10.0 10.0 4.0 4.0 13.5 12.5 4.0 4.0 11.0 11.0 tPLH tPHL Propagation Delay Pn to Qn 3.0 6.0 4.5 10.0 7.0 13.0 3.0 6.0 9.0 16.0 3.0 6.0 8.0 14.0 ns tPLH tPHL Propagation Delay PL to Qn 5.0 5.5 8.5 9.0 11.0 12.0 5.0 5.5 13.0 14.5 5.0 5.5 12.0 13.0 ns tPLH tPHL Propagation Delay Pn to TC 5.0 6.5 14.0 13.0 5.0 6.0 15.0 14.0 ns tPLH tPHL Propagation Delay Pn to RC 6.5 6.0 19.0 14.0 6.5 6.0 20.0 15.0 ns tPLH tPHL Propagation Delay PL to TC 8.0 6.0 16.5 13.5 8.0 6.0 17.5 14.5 ns tPLH tPHL Propagation Delay PL to RC 10.0 9.0 20.0 15.5 10.0 9.0 21.0 16.0 ns 75 5 Min Units Max 90 MHz ns ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Pn to PL 4.5 4.5 6.0 6.0 5.0 5.0 th(H) th(L) Hold Time, HIGH or LOW Pn to PL 2.0 2.0 2.0 2.0 2.0 2.0 ts(L) Setup Time LOW CE to CP 10.0 10.5 10.0 th(L) Hold Time LOW CE to CP 0 0 0 ts(H) ts(L) Setup Time, HIGH or LOW U/D to CP 12.0 12.0 12.0 12.0 12.0 12.0 th(H) th(L) Hold Time, HIGH or LOW U/D to CP 0 0 0 0 0 0 tw(L) PL Pulse Width LOW 6.0 8.5 6.0 ns tw(L) CP Pulse Width LOW 5.0 7.0 5.0 ns trec Recovery Time PL to CP 6.0 7.5 6.0 ns ns ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 191 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations X e Devices shipped in 13× reels QB e Military grade with environmental and burn-in processing shipped in tubes Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 6 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 16-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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