54F/74F283 4-Bit Binary Full Adder with Fast Carry General Description Features The ’F283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words (A0 –A3, B0 – B3) and a Carry input (C0). It generates the binary Sum outputs (S0 – S3) and the Carry output (C4) from the most significant bit. The ’F283 will operate with either active HIGH or active LOW operands (positive or negative logic). Y Commercial Guaranteed 4000V minimum ESD protection Package Number Military Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line 74F283SC (Note 1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC 74F283SJ (Note 1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F283FM (Note 2) W16A 16-Lead Cerpack 54F283LL (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F283PC 54F283DM (Note 2) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9513–1 IEEE/IEC TL/F/9513 – 2 TL/F/9513 – 3 TL/F/9513–4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9513 RRD-B30M105/Printed in U. S. A. 54F/74F283 4-Bit Binary Full Adder with Fast Carry November 1994 Unit Loading/Fan Out 54F/74F Pin Names A 0 – A3 B 0 – B3 C0 S0 – S3 C4 Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL A Operand Inputs B Operand Inputs Carry Input Sum Outputs Carry Output 1.0/2.0 1.0/2.0 1.0/1.0 50/33.3 50/33.3 20 mA/b1.2 mA 20 mA/b1.2 mA 20 mA/b0.6 mA b 1 mA/20 mA b 1 mA/20 mA Functional Description other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the ’F283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1 –I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs I1 –I5 are true, the output M5 is true. The ’F283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (S0 – S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. 20 (A0 a B0 a C0) a 21 (A1 a B1) a 22 (A2 a B2) a 23 (A3 a B3) e S0 a 2S1 a 4S2 a 8S3 a 16C4 Where ( a ) e plus Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the ’F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure 1 . Note that if C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic. Due to pin limitations, the intermediate carries of the ’F283 are not brought out for use as inputs or outputs. However, C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4 Logic Levels L L H L H H L L H H H L L H Active HIGH Active LOW 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1 0 1 1 0 Active HIGH: 0 a 10 a 9 e 3 a 16 Active LOW: 1 a 5 a 6 e 12 a 0 FIGURE 1. Active HIGH versus Active LOW Interpretation 2 Functional Description (Continued) TL/F/9513 – 5 FIGURE 2. 3-Bit Adder TL/F/9513 – 6 FIGURE 3. 2-Bit and 1-Bit Adders TL/F/9513 – 7 FIGURE 4. 5-Input Encoder TL/F/9513 – 8 FIGURE 5. 5-Input Majority Gate 3 TL/F/9513 – 9 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 4 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA 0.5 0.5 V Min IOL e 20 mA IOL e 20 mA 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.2 mA Max VIN e 0.5V (CO) VIN e 0.5V (An, Bn) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICCH Power Supply Current 36 55 mA Max VO e HIGH ICCL Power Supply Current 36 55 mA Max VO e LOW 74F 2.5 2.5 2.7 4.75 74F b 60 5 Recognized as a LOW Signal AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Units Min Typ Max Min Max Min Max tPLH tPHL Propagation Delay C0 to Sn 3.5 3.0 7.0 7.0 9.5 9.5 3.5 3.0 14.0 14.0 3.5 3.0 11.0 11.0 ns tPLH tPHL Propagation Delay An or Bn to Sn 3.0 3.0 7.0 7.0 9.5 9.5 3.0 3.0 17.0 14.0 3.0 3.0 13.0 11.5 ns tPLH tPHL Propagation Delay C0 to C4 3.0 3.0 5.7 5.4 7.5 7.0 3.0 2.5 10.5 10.0 3.0 3.0 8.5 8.0 ns tPLH tPHL Propagation Delay An or Bn to C4 3.0 2.5 5.7 5.3 7.5 7.0 3.0 2.5 10.5 10.0 3.0 2.5 8.5 8.0 ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 283 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 6 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 16-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 9 54F/74F283 4-Bit Binary Full Adder with Fast Carry Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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