National Semiconductor Application Note 2011 James Patterson September 23, 2010 EFFICIENCY WITH 9 SERIES LEDS AT 700mA Introduction This evaluation board showcases the LM3423 NFET controller used with a boost current regulator. It is designed to drive 9 to 12 LEDs at a maximum average LED current of 700mA from a DC input voltage of 10 to 26V. The evaluation board showcases most features of the LM3423 including PWM dimming, overvoltage protection and input under-voltage lockout. It also has a connector footprint (J7) which can mate with an external LED load board allowing for the LEDs to be mounted close to the driver. Alternatively, the LED+ and LED- banana jacks can be used to connect the LED load. The boost circuit can be easily redesigned for different specifications by changing only a few components (see the Alternate Designs section found at the end of this application note). Note that design modifications can change the system efficiency. See the LM3423 datasheet for a comprehensive explanation of the device and application information. 30107801 Schematic © 2010 National Semiconductor Corporation 301078 www.national.com AN-2011 30107802 LM3423 Boost 2 Layer Evaluation Board LM3423 Boost 2 Layer Evaluation Board AN-2011 Pin Descriptions LM3423 LM3421 Name Description Function 1 1 VIN Input Voltage Bypass with 100 nF capacitor to AGND as close to the device as possible in the circuit board layout. 2 2 EN Enable Connect to AGND for zero current shutdown or apply > 2.4V to enable device. 3 3 COMP Compensation Connect a capacitor to AGND to set the compensation. 4 4 CSH Current Sense High Connect a resistor to AGND to set the signal current. For analog dimming, connect a controlled current source or a potentiometer to AGND as detailed in the Analog Dimming section. 5 5 RCT Resistor Capacitor Timing External RC network sets the predictive “off-time” and thus the switching frequency. 6 6 AGND Analog Ground Connect to PGND through the DAP copper pad to provide ground return for CSH, COMP, RCT, and TIMR. Over-Voltage Protection Connect to a resistor divider from VO to program output over-voltage lockout (OVLO). Turn-off threshold is 1.24V and hysteresis for turn-on is provided by 23 µA current source. 7 7 OVP 8 8 nDIM Dimming Input / Under-Voltage Protection Connect a PWM signal for dimming as detailed in the PWM Dimming section and/or a resistor divider from VIN to program input under-voltage lockout (UVLO). Turn-on threshold is 1.24V and hysteresis for turn-off is provided by 23 µA current source. 9 - FLT Fault Flag Connect to pull-up resistor from VIN and N-channel MosFET open drain output is high when a fault condition is latched by the timer. 10 - TIMR Fault Timer 11 - LRDY LED Ready Flag Connect to pull-up resistor from VIN and N-channel MosFET open drain output pulls down when the LED current is not in regulation. 12 - DPOL Dim Polarity Connect to AGND if dimming with a series P-channel MosFET or leave open when dimming with series Nchannel MosFET. 13 9 DDRV Dim Gate Drive Output 14 10 PGND Power Ground 15 11 GATE Main Gate Drive Output 16 12 VCC Internal Regulator Output Bypass with 2.2 µF–3.3 µF ceramic capacitor to PGND. 17 13 IS Main Switch Current Sense Connect to the drain of the main N-channel MosFET switch for RDS-ON sensing or to a sense resistor installed in the source of the same device. 18 14 RPD Resistor Pull Down 19 15 HSP LED Current Sense Positive Connect through a series resistor to the positive side of the LED current sense resistor. 20 16 HSN LED Current Sense Negative Connect through a series resistor to the negative side of the LED current sense resistor. DAP (21) DAP (17) DAP Thermal PAD on bottom of IC Star ground, connecting AGND and PGND. www.national.com Connect a capacitor to AGND to set the time delay before a sensed fault condition is latched. 2 Connect to the gate of the dimming MosFET. Connect to AGND through the DAP copper pad to provide ground return for GATE and DDRV. Connect to the gate of the main switching MosFET. Connect the low side of all external resistor dividers (VIN UVLO, OVP) to implement “zero-current” shutdown. AN-2011 Bill of Materials Qty Part ID Part Value Manufacturer Part Number 2 C1, C12 0.1 µF X7R 10% 50V TDK C1608X5R1H104K 2 C2, C8 1.0 µF X7R 10% 50V MURATA GRM21BR71H105KA12L KA01L 1 C3 100 µF 20% 50V PANASONIC EEV-FK1H101GP 1 C4 0.1 µF X7R 10% 100V TDK C2012X7R2A104M 1 C5 DNP 4 C6 10 µF X7R 10% 50V (4 TDK installed for a total of 40 µF) C5750X7R1H106 1 C7 1000 pF X5R 5% 100V MURATA C2012X5R2E102K 1 C9 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA01L 1 C10 10 nF X7R 10% 50V PANASONIC ECJ2VB1H103 KA12L 1 C11 47 pF COG/NPO 5% 50V PANASONIC ECJ2VG1H470 KA01L 1 D1 Schottky 100V 7A VISHAY 6CWQ10FNPBF 4 J1, J2, J4, J5 banana jack KEYSTONE 575-8 1 J3 1x2 male header (with shunt SAMTEC tab) TSW-102-07-T-S 1 J6 BNC connector AMPHENOL 112536 1 J7 DNP 1 L1 22 µH 20% 6.3A COILCRAFT DO5040H 2 Q1, Q2 NMOS 100V 40A VISHAY SUD40N10-25 1 Q3 NMOS 60V 260 mA ON-SEMI 2N7002ET1G 2 R1, R11 12.4 kΩ 1% VISHAY CRCW080512k4FKEA 1 R2 0Ω 1% VISHAY CRCW08050000Z0EA 2 R3, R20 10Ω 1% VISHAY CRCW080510R0FKEA 1 R4 5.76 kΩ 1% VISHAY CRCW08055k76FKEA 1 R5 14.0 kΩ 1% VISHAY CRCW080514k0FKEA 2 R7, R8 1.40 kΩ 1% VISHAY CRCW08051k40FKEA 1 R6 0.06Ω 1% 1W VISHAY WSL2512R0600FEA 1 R9 0.2Ω 1% 1W PANASONIC ERJ12RSFR20U 1 R10 35.7 kΩ 1% VISHAY CRCW080535k7FKEA 1 R12 10.0 kΩ 1% VISHAY CRCW080510k0FKEA 3 R13, R14, R15 100 kΩ 1% VISHAY CRCW0805100kFKEA 2 R16, R21 DNP 1 R17 432 kΩ 1% VISHAY CRCW0805432kFKEA 5 TP1, TP4, TP5, TP7, TP10 turret KEYSTONE 1502-2 1 U1 Buck-boost controller NSC LM3423MH 3 www.national.com AN-2011 PCB Layout 30107803 Top Layer 30107804 Bottom Layer www.national.com 4 AN-2011 3. AVERAGE LED CURRENT Solve for R9: Design Procedure Refer to LM3429 datasheet for design considerations. SPECIFICATIONS N=9 VLED = 3.5V rLED = 325 mΩ VIN = 24V VIN-MIN = 10V; VIN-MAX = 26V fSW = 700 kHz VSNS = 150 mV ILED = 700mA Assume R1 = 12.4 kΩ and solve for R8: The closest standard resistor for R9 is 0.2Ω and the closest for R8 (and R7) is actually 1.4 kΩ therefore ILED is: ΔiL-PP = 350 mA ΔiLED-PP = 25 mA ΔvIN-PP = 100 mV ILIM = 4A VTURN-ON = 10V; VHYS = 3V VTURN-OFF = 44V; VHYSO = 10V The chosen components from step 3 are: 1. OPERATING POINT Solve for VO and rD: 4. INDUCTOR RIPPLE CURRENT Solve for L1: Solve for D, D', DMAX, and DMIN: The closest standard inductor is 22 µH therefore the actual ΔiL-PP is: Determine minimum allowable RMS current rating: 2. SWITCHING FREQUENCY Assume C7 = 1 nF and solve for R10: The closest standard resistor is actually 35.7 kΩ therefore the fSW is: The chosen component from step 4 is: The chosen components from step 2 are: 5 www.national.com AN-2011 TU0 is approximated: 5. OUTPUT CAPACITANCE Solve for CO: To ensure stability, calculate ωP2: A total value of 40 µF (using 4 10 µF ceramic capacitors) is chosen to improve PWM dimming response therefore the actual ΔiLED-PP is: Solve for C8: To attenuate switching noise, calculate ωP3: Determine minimum allowable RMS current rating: Assume R20 = 10Ω and solve for C12: The chosen components from step 5 are: 6. PEAK CURRENT LIMIT Solve for R6: Since PWM dimming can be evaluated with this board, a much larger compensation capacitor C8 = 1.0 µF is chosen and a smaller high frequency capacitor C12 = 0.1 µF is chosen. The chosen components from step 7 are: The closest standard resistor is 0.06 Ω therefore ILIM is: The chosen component from step 6 is: 8. INPUT CAPACITANCE Solve for the minimum CIN: 7. LOOP COMPENSATION ωP1 is approximated: To minimize power supply interaction a much larger capacitance of 100 µF is used, therefore the actual ΔvIN-PP is much lower. Determine minimum allowable RMS current rating: ωZ1 is approximated: The chosen components from step 8 are: www.national.com 6 AN-2011 Solve for R4: 9. NFET Determine minimum Q1 voltage rating and current rating: The closest standard resistor is 5.76 kΩ making VHYS: A 100V NFET is chosen with a current rating of 40A due to the low RDS-ON = 50 mΩ. Determine IT-RMS and PT: The chosen components from step 11 are: The chosen component from step 9 is: 10. DIODE Determine minimum D1 voltage rating and current rating: 12. OUTPUT OVLO Solve for R17: A 100V diode is chosen with a current rating of 12A and VD = 600 mV. Determine PD: The closest standard resistor is 432 kΩ therefore VHYSO is: The chosen component from step 10 is: Solve for R11: 11. INPUT UVLO Since PWM dimming will be evaluated a three resistor network will be used. Assume R13 = 100 kΩ and solve for R5: The closest standard resistor is 12.4 kΩ making VTURN-OFF: The closest standard resistor is 14 kΩ therefore VTURN-ON is: The chosen components from step 12 are: 7 www.national.com AN-2011 13. PWM DIMMING The LM3423 Boost Evaluation board is configured to demonstrate PWM dimming of the LEDs. For best operation, use a PWM signal that has greater than 3V amplitude at a frequency between 120Hz and 25kHz. Apply the PWM signal to the BNC connector (J6) and the inverted signal (seen by the nDIM pin) can be monitored at TP5. The output DDRV signal is connected directly to the series dimming FET (Q2) to open and close the LED load. Achievable contrast ratios are dependant on the dimming frequency and operating point. The minimum pulse width is limited by the internal delays of the LM3423 and the slew time of the LED current from zero to its nominal value. This can be several microseconds in duration. Using the evaluation board (24V input, 31.5V output), at 25kHz dimming frequency the best case contrast ratio is approximately 20:1, but at 200Hz the same system is more like 2500:1 ratio. In general, contrast ratios much above 4000:1 are not possible for any operating point using the LM3423 boost evaluation board. 13. FAULT AND LED CURRENT MONITORING The LM3423 has a fault detection flag in the form of an opendrain NFET at the FLT pin. Using the external pull-up resistor (R14) to VIN, the fault status can be monitored at the FLT pin (high = fault). The fault timer interval is set with the capacitor (C10) from TIMR to GND (10nF yields roughly 1ms). If a fault is detected that exceeds the programmed timer interval, such as an output over-voltage condition, the FLT pin transitions from high to low and internally GATE and DDRV are latched off. To reset the device once the fault is removed, either the input power must be cycled or the EN pin must be toggled. This can be tested directly with the evaluation board by opening the LED load. An OVP fault will occur which disables GATE and DDRV. Then if the LEDs are reconnected, the EN pin jumper (J3) can be removed and reinserted to restart normal operation of the LM3423. The LED status flag (LRDY) can be seen by monitoring TP4. LRDY is also an open-drain NFET connection which has an external pull-up resistor (R15) to VIN. If the LED current is in regulation the voltage at TP4 will be high, but when it falls out of regulation the NFET turns on and pulls TP4 low. The LM3423 datasheet lists all of the conditions that affect LRDY, FLT, and TIMR. Typical Waveforms TA = +25°C, VIN = 24V and VO = 31.5V. 30107861 30107862 1kHz 50% PWM DIMMING TP5 dim voltage (VDIM) LED current (ILED) www.national.com 1kHz 50% PWM DIMMING (Rising Edge) TP5 dim voltage (VDIM) LED current (ILED) 8 Alternate designs with the LM3423 evaluation board are possible with very few changes to the existing hardware. The evaluation board FETs and diodes are already rated higher than necessary for design flexibility. The input UVLO, output OVP, input and output capacitance can remain the same for Specification / Component Design 1 Design 2 Design 3 Design 4 VIN 10V 15V 20V 25V VO 14V 21V 28V 35V fSW 600kHz 700kHz 500kHz 700kHz ILED 2A 500mA 2.5A 1.25A R9 0.05Ω 0.2Ω 0.04Ω 0.08Ω R10 41.2 kΩ 35.7 kΩ 49.9 kΩ 35.7 kΩ L1 22µH 68µH 15µH 33µH 9 www.national.com AN-2011 the designs shown below. These alternate designs can be evaluated by changing only R9, R10, and L1. The table below gives the main specifications for four different designs and the corresponding values for R9, R10, and L1. PWM dimming can be evaluated with any of these designs. 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