ADS5275 SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 8-Channel, 10-Bit, 40MSPS ADC with Serial LVDS Interface P LL IN1 P IN1 N S/H IN2 P IN2 N S/H IN3 P IN3 N S/H The ADS5275 is a high-performance, 40MSPS, 8-channel, parallel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. In LVDS, an integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 6. This high-frequency LVDS clock is used in the data serialization and transmission process and is converted to an LVDS signal for transmission in parallel with the data. Providing this additional LVDS clock allows for easy delay matching. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. The bit following the rising edge of the ADC clock output is the first bit of the word. IN4 N S/H IN5 P IN5 N S/H IN6 P IN6 N S/H IN7 P IN7 N S/H IN8 P IN8 N S/H 10−Bit ADC Se rializer 10−Bit ADC Se rializer 10−Bit ADC Se rializer 10−Bit ADC Se rializer 10−Bit ADC Se rializer 10−Bit ADC Se rializer 10−Bit ADC Se rializer 10−Bit ADC Se rializer INT/E XT OUT1 N OUT2 P OUT2 N OUT3 P OUT3 N OUT4 P OUT4 N OUT5 P OUT5 N OUT6 P OUT6 N OUT7 P OUT7 N OUT8 P OUT8 N R egisters Reference OUT1 P Control Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2004, Texas Instruments Incorporated PRODUCT PREVIEW A DCLK N IN4 P DESCRIPTION A DCLK P 1X ADCLK ADCLK PD Portable Ultrasound Systems Tape Drives Test Equipment LCLK N RE SE T • • • LCLK P 6X ADCLK S DAT A APPLICATIONS The ADS5275 is available in a PowerPAD TQFP-80 package and are specified over a -40°C to +85°C operating range. CS • • • Maximum Sample Rate: 40MSPS 10-Bit Resolution No Missing Codes Power Dissipation: 768mW CMOS Technology Simultaneous Sample-and-Hold 60.5dB SNR at 10MHz IF Serialized LVDS Outputs Meet or Exceed Requirements of ANSI TIA/EIA-644-A Standard Internal and External References 3.3V Digital/Analog Supply TQFP-80 PowerPAD™ Package SCLK • • • • • • • • The ADS5275 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. RE F T VC M RE F B FEATURES ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR ADS5275 HTQFP-80 PFP (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING -40°C to +85°C ADS5275IPFP ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5275IPFP Tray, 96 ADS5275IPFPT Tape and Reel, 250 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ABSOLUTE MAXIMUM RATINGS (1) PRODUCT PREVIEW Supply Voltage Range, AVDD -0.3V to +3.8V Supply Voltage Range, LVDD -0.3V to +3.8V Voltage Between AVSS and LVSS -0.3V to +0.3V Voltage Between AVDD and LVDD -0.3V to +0.3V Voltage Applied to External REF Pins -0.3V to +2.4V All LVDS Data and Clock Outputs -0.3V to +2.4V Analog Input Pins -0.3V to +2.7V Peak Total Input Current (all inputs) -30mA Operating Free-Air Temperature Range, TA -40°C to +85°C Lead Temperature, 1.6mm (1/16" from case for 10s) (1) 220°C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. RELATED PRODUCTS 2 MODEL RESOLUTION (BITS) SAMPLE RATE (MSPS) CHANNELS ADS5270 12 40 8 ADS5271 12 50 8 ADS5272 12 65 8 ADS5273 12 70 8 ADS5276 10 50 8 ADS5277 10 65 8 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 RECOMMENDED OPERATING CONDITIONS ADS5275 MIN TYP MAX UNITS Analog Supply Voltage, AVDD 3.0 3.3 3.6 V Output Driver Supply Voltage, LVDD 3.0 3.3 3.6 V SUPPLIES AND REFERENCES CLOCK INPUT AND OUTPUTS ADCLK Input Sample Rate (low-voltage TTL), 1/tC 40 MSPS Low-Level Voltage Clock Input 20 1 V High-Level Voltage Clock Input 2 V ADCLKP and ADCLKN Outputs (LVDS) 20 40 MHz LCLKP and LCLKN Outputs (LVDS) (1) 120 240 MHz Operating Free-Air Temperature, TA -40 +85 °C Thermal Characteristics: θJA 21 °C/W θJC 68 °C/W 6 × ADCLK. PRODUCT PREVIEW (1) REFERENCE SELECTION MODE 2.0VPP Internal Reference External Reference INT/EXT DESCRIPTION 1 Default with internal pull-up. 0 Internal reference is powered down. Common mode of external reference should be within 50mV of VCM. VCM is derived from the internal bandgap voltage. 3 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5275 PARAMETER TEST CONDITIONS MIN fIN = 5MHz -0.9 fIN = 5MHz -2.0 -0.75 TYP MAX UNITS ±0.5 +0.9 LSB ±0.6 +2.0 LSB ±0.2 +0.75 DC ACCURACY No Missing Codes DNL Differential Nonlinearity INL Integral Nonlinearity Offset Assured Error (1) Offset Temperature Coefficient Fixed Attenuation in Channel (2) Variable Attenuation in Channel (3) Gain Error (4) REFT - REFB -2.5 Gain Temperature Coefficient (5) %FS 14 ppm/°C 1 %FS ±2.0 %FS ±1.0 +2.5 %FS 44 ppm/°C POWER SUPPLY ICC Total Supply Current PRODUCT PREVIEW VIN = FS, FIN = 5MHz 275 mA I(AVDD) Analog Supply Current VIN = FS, FIN = 5MHz 221 mA I(LVDD) Digital Output Driver Supply Current VIN = FS, FIN = 5MHz, LVDS into 100Ω Load 54 mA Power Dissipation Power-Down 904 Clock Running 950 90 mW mW REFERENCE VOLTAGES VREFT Reference Top (internal) 1.95 2.0 2.05 V VREFB Reference Bottom (internal) 0.95 1.0 1.05 V VCM Common-Mode Voltage 1.45 1.5 1.55 V VCM Output Current (6) ±50mV Change in Voltage VREFT Reference Top (external) ±2.0 mA 1.875 V VREFB Reference Bottom (external) 1.125 External Reference Input Current (7) 2.0 V mA ANALOG INPUT Differential Input Capacitance 70 Analog Input Common-Mode Range Differential Input Voltage Range Voltage Overhead Recovery Time Input Bandwidth 1.5 pF VCM ± 0.05 V 2.02 VPP Differential Input Signal at 4VPP Recovery to Within 1% of Code 4.0 CLK Cycles -3dBFS 300 MHz DIGITAL DATA OUTPUTS Data Bit Rate 240 480 MBPS SERIAL INTERFACE (1) (2) (3) (4) (5) (6) (7) 4 Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale. Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are changed from -VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT - REFB). Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation. The reference voltages are trimmed at production so that (VREFT - VREFB) is within ± 25mV of the ideal value of 1V. It does not include fixed attenuation. The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with temperature. VCM provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The VCM output current specified is the additional drive of the VCM buffer if loaded externally. Average current drawn from the reference pins in the external reference mode. ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5275 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 20 MHz V SCLK Serial Clock Input Frequency VIN LOW Input Low Voltage 0 0.6 VIN HIGH Input High Voltage 2.1 VDD V Input Current ±10 µA Input Pin Capacitance 5.0 pF AC CHARACTERISCTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted. ADS5275 PARAMETER CONDITIONS MIN TYP MAX UNITS fIN = 1MHz SFDR Spurious-Free Dynamic Range HD2 2nd-Order Harmonic Distortion HD3 3rd-Order Harmonic Distortion 80 dBc 80 dBc fIN = 10MHz 80 dBc fIN = 20MHz 80 dBc fIN = 1MHz 85 dBc 85 dBc fIN = 10MHz 85 dBc fIN = 20MHz 85 dBc fIN = 1MHz 80 dBc fIN = 5MHz fIN = 5MHz fIN = 5MHz TBD TBD 80 dBc fIN = 10MHz TBD 80 dBc fIN = 20MHz 80 dBc 60.5 dBFS 60.5 dBFS fIN = 10MHz 60.5 dBFS fIN = 20MHz 60.5 dBFS 60 dBFS 60 dBFS 60 dBFS fIN = 20MHz 60 dBFS fIN = 10MHz 9.7 Bits Signal Applied to 7 Channels; Measurement Taken on the Channel with No Input Signal -85 dBc fIN = 1MHz SNR Signal-to-Noise Ratio fIN = 5MHz TBD fIN = 1MHz SINAD Signal-to-Noise and Distortion ENOB Effective Number of Bits Crosstalk fIN = 5MHz fIN = 10MHz TBD PRODUCT PREVIEW DYNAMIC CHARACTERISTICS 5 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 LVDS DIGITAL DATA AND CLOCK OUTPUTS Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 9pF. All LVDS specifications are functionally tested, but not parametrically tested. PARAMETER CONDITIONS MIN TYP MAX UNITS 1340 1475 mV DC SPECIFICATIONS VOH Output Voltage High, OUTP or OUTN VOL Output Voltage Low, OUTP or OUTN |VOD| Output Differential Voltage VOS Output Offset Voltage RO Output Impedance, Single-Ended ∆RO Mismatch Between OUTP and OUTN CO Output Capacitance |∆VOD| Change in |VOD| Between 0 and 1 RLOAD = 100Ω± 1%; See LVDS Timing Diagram, Page 7 RLOAD = 100Ω± 1% 925 1038 RLOAD = 100Ω± 1% 325 350 375 mV RLOAD = 100Ω± 1%; See LVDS Timing Diagram, Page 7 1.125 1.250 1.275 V VCM = 1.0V and 1.4V Ω TBD VCM = 1.0V and 1.4V VCM = 1.0V and 1.4V mV 3 4 TBD % 5 pF RLOAD = 100Ω± 1% 25 mV ∆VOS Change Between 0 and 1 RLOAD = 100Ω± 1% 25 mV ISOUT Output Short-Circuit Current Drivers Shorted to Ground 40 mA Drivers Shorted Together 12 mA VCC = 0V 10 mA 55 % Any Differential Pair on Package (1) 50 ps Any Two Signals on Package (3) 100 ps ISOUTNP Output Current PRODUCT PREVIEW |IXN|, |IXP| Power-Off Output Leakage DRIVER AC SPECIFICATIONS Clock Clock Signal Duty Cycle tSKEW1 |tpHLP - tpLHN| or |tpHLN - tpHLP|, Differential Skew tSKEW2 |tpDIFF[X] - tpDIFF[Y]|, Channel-to-Channel Skew (2) tRISE/tFALL VOD Rise Time or VOD Fall Time (1) (2) (3) 6 6 × ADCLK 45 50 ZLOAD = 100Ω, CI = 9pF, IO = 2.5mA 400 ZLOAD = 100Ω, CI = 9pF, IO = 3.5mA 250 ps ZLOAD = 100Ω, CI = 9pF, IO = 4.5mA 200 ps ZLOAD = 100Ω, CI = 9pF, IO = 6.0mA 150 ps Skew measurements are made at the 50% point of the transistion. Where x is any one of the parallel channels and y is any other channel. Skew measurements made at 0V differential (that is, the crossing of single-ended signals). ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 SWITCHING CHARACTERISTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56kΩ, internal voltage reference, and 2VPP differential input,unless otherwise noted. ADS5275 PARAMETER CONDITIONS MIN TYP MAX UNITS 50 ns SWITCHING SPECIFICATIONS tSAMPLE 25 tD(A) Aperature Delay Aperature Jitter (uncertainty) tD(pipeline) Latency tPROP Propagation Delay 120 ps 1 ps 6.5 Cycles 5 ns SERIAL INTERFACE TIMING Data is shifted in MSB first. PRODUCT PREVIEW Outputs change on next rising clock edge after CS goes high. ADCLK Start Sequence CS t1 Data latched on each rising edge of SCLK. t2 SCLK t3 MSB SDATA D6 D5 D4 D3 D2 D1 D0 t4 t5 PARAMETER DESCRIPTION MIN t1 Serial CLK Period 50 TYP MAX UNIT ns t2 Serial CLK High Time 13 ns t3 Serial CLK Low Time 13 ns t4 Minimum Data Setup Time 5 ns t5 Minimum Data Hold Time 5 ns 7 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 SERIAL INTERFACE TIMING ADDRESS DATA D7 D6 D5 D4 0 0 0 0 0 0 0 0 PRODUCT PREVIEW 0 0 0 D3 D2 DESCRIPTION D1 0. LVDS BUFFERS 0 0 Normal ADC Output 0 1 Deskew Pattern 1 0 Sync Pattern 1 1 Custom Pattern 0 0 Output Current in LVDS = 3.5mA 0 1 Output Current in LVDS = 2.5mA 1 0 Output Current in LVDS = 4.5mA 1 1 1 1 Output Current in LVDS = 6.0mA D3 D2 D1 D0 0 X X 1 0 0 X X LSB Mode 0 1 X X MSB Mode 2X LVDS Clock Output Current 2. POWER-DOWN ADC CHANNELS D3 D2 D1 D0 X X X X D3 D2 D1 D0 X X X X D3 D2 D1 D0 X 1 Power-Down Channels 1 to 4; D3 is for Channel 4 and D0 for Channel 1 3. POWER-DOWN ADC CHANNELS Power-Down Channels 5 to 8; D3 is for Channel 8 and D0 for Channel 5 CUSTOM PATTERN (registers 4-6) 0 1 0 0 MSB X X 0 1 0 1 X X X X 0 1 1 0 X X X LSB Bits for Custom Pattern TEST PATTERNS (1) Deskew 101010101010 Sync 000000111111 Custom Any 10-bit pattern that is defined in the custom pattern registers 4 to 6. (1) 8 Patterns Get Reversed in MSB First Mode of LVDS 1. LSB/MSB MODE 0 1 REMARKS D0 Default is LSB first. If MSB is selected, the above patterns will be reversed. Example: 1010 Powers Down Channels 4 and 2 and Keeps Channels 1 and 3 Alive ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 LVDS TIMING DIAGRAM (PER ADC CHANNEL) Sample n Sample n+6 Input 1 fS ADCLK tSAMPLE 2 LCLKP 6X ADCLK LCLKN OUTP SERIAL DATA 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 0 0 OUTN PRODUCT PREVIEW Sample n data ADCLKP 1X ADCLK ADCLKN tPROP 6.5 Clock Cycles RESET TIMING t1 +AVDD Power Supply t1 > TBD t2 > 100ns 0V +AVDD RESET 0V t2 POWER-DOWN TIMING Device Fully Powers Down 10µs PDN 1µs Device Fully Powers Up 9 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 PIN CONFIGURATION ISET AVDD AVSS AVSS 73 VCM 74 REFB AVSS 75 REFT AVSS 76 AVSS AVDD 77 INT/EXT CS 78 AVDD SDA 79 AVSS SCLK 80 ADCLK AVSS HTQFP AVSS Top View 72 71 70 69 68 67 66 65 64 63 62 61 AVDD 1 60 AVDD IN1P 2 59 IN8N IN1N 3 58 IN8P AVSS 4 57 AVSS IN2P 5 56 IN7N IN2N 6 55 IN7P AVDD 7 54 AVDD AVSS 8 53 AVSS IN3P 9 52 IN6N PRODUCT PREVIEW IN3N 10 51 IN6P ADS5275 AVSS 11 50 AVSS IN4P 12 49 IN5N IN4N 13 48 IN5P AVDD 14 47 AVDD LVSS 15 46 LVSS 45 RESET PD 16 10 LVSS 17 44 LVSS LVSS 18 43 LVSS 33 34 35 36 37 38 39 40 OUT8N OUT3N 32 OUT8P OUT3P 31 OUT7N LVSS 30 OUT7P LVDD 29 LVSS 28 LVDD 27 OUT6N 26 OUT6P 25 OUT5N 24 OUT5P 23 OUT4P 22 OUT4N 21 OUT2N 41 ADCLKP OUT2P LCLKN 20 OUT1N 42 ADCLKN OUT1P LCLKP 19 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 PIN DESCRIPTIONS PIN # NUMBER OF PINS I/O DESCRIPTION AVDD 1, 7, 14, 47, 54, 60, 63, 70, 75 9 I Analog Power Supply AVSS 4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80 14 I Analog Ground LVDD 25, 35 2 I LVDS Power Supply LVSS 15, 17, 18, 26, 36, 43, 44, 46 8 I LVDS Ground IN1P 2 1 I Channel 1 Differential Analog Input High IN1N 3 1 I Channel 1 Differential Analog Input Low IN2P 5 1 I Channel 2 Differential Analog Input High IN2N 6 1 I Channel 2 Differential Analog Input Low IN3P 9 1 I Channel 3 Differential Analog Input High IN3N 10 1 I Channel 3 Differential Analog Input Low IN4P 12 1 I Channel 4 Differential Analog Input High IN4N 13 1 I Channel 4 Differential Analog Input Low IN5P 48 1 I Channel 5 Differential Analog Input High IN5N 49 1 I Channel 5 Differential Analog Input Low IN6P 51 1 I Channel 6 Differential Analog Input High IN6N 52 1 I Channel 6 Differential Analog Input Low IN7P 55 1 I Channel 7 Differential Analog Input High IN7N 56 1 I Channel 7 Differential Analog Input Low IN8P 58 1 I Channel 8 Differential Analog Input High IN8N 59 1 I Channel 8 Differential Analog Input Low REFT 67 1 I/O Reference Top Voltage (1Ω resistor in series with a 0.1µF capacitor to ground) REFB 66 1 I/O Reference Bottom Voltage (1Ω resistor in series with a 0.1µF capacitor to ground) VCM 65 1 O Common-Mode Output Voltage INT/EXT 69 1 I Internal/External Reference Select; 0 = External, 1 = Internal PD 16 1 I Power-Down; 0 = Normal, 1 = Power-Down LCLKP 19 1 O Positive LVDS Clock LCLKN 20 1 O Negative LVDS Clock ADCLK 71 1 I Data Converter Clock Input OUT1P 21 1 O Channel 1 Positive LVDS Data Output OUT1N 22 1 O Channel 1 Negative LVDS Data Output OUT2P 23 1 O Channel 2 Positive LVDS Data Output OUT2N 24 1 O Channel 2 Negative LVDS Data Output OUT3P 27 1 O Channel 3 Positive LVDS Data Output OUT3N 28 1 O Channel 3 Negative LVDS Data Output OUT4P 29 1 O Channel 4 Positive LVDS Data Output OUT4N 30 1 O Channel 4 Negative LVDS Data Output OUT5P 31 1 O Channel 5 Positive LVDS Data Output OUT5N 32 1 O Channel 5 Negative LVDS Data Output OUT6P 33 1 O Channel 6 Positive LVDS Data Output OUT6N 34 1 O Channel 6 Negative LVDS Data Output OUT7P 37 1 O Channel 7 Positive LVDS Data Output OUT7N 38 1 O Channel 7 Negative LVDS Data Output OUT8P 39 1 O Channel 8 Positive LVDS Data Output OUT8N 40 1 O Channel 8 Negative LVDS Data Output ADCLKP 41 1 O Positive LVDS ADC Clock Output 11 PRODUCT PREVIEW NAME ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 PIN DESCRIPTIONS (continued) NAME PIN # NUMBER OF PINS I/O DESCRIPTION ADCLKN 42 1 O I/O Bias Current Setting Resistor of 56kΩ to Ground Negative LVDS ADC Clock Output ISET 64 1 RESET 45 1 I Reset to Default; 0 = Reset, 1 = Normal CS 76 1 I Chip Select; 0 = Select, 1 = No Select SDA 77 1 I Serial Data input SCLK 78 1 I Serial Data Clock PRODUCT PREVIEW 12 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. SPECTRAL PERFORMANCE 0 fIN = 10MHz SNR = 60.5dBFS SFDR = 85dBc SINAD = 60dBFS −40 −60 −80 −100 −120 0 5 10 15 20 Frequency (MHz) Figure 1. PRODUCT PREVIEW Amplitude (dB) −20 13 ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 THEORY OF OPERATION OVERVIEW PRODUCT PREVIEW The ADS5275 is an 8-channel, high-speed, CMOS ADC. It consists of a high-performance sample-and-hold circuit at the input, followed by a 10-bit ADC. The 10 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the ADS5275 run off a single clock referred to as ADCLK. The sampling clocks for each of the eight channels are generated from the input clock using a carefully matched clock buffer tree. The 12X clock required for the serializer is generated internally from ADCLK using a phase lock loop (PLL). A 6X and a 1X clock are also output in LVDS format along with the data to enable easy data capture. The ADS5275 operates from internally generated reference voltages that are trimmed to ensure matching across multiple devices on a board. This feature eliminates the need for external routing of reference lines and also improves matching of the gain across devices. The nominal values of REFT and REFB are 2V and 1V, respectively. This implies that a differential input of -1V corresponds to the zero code of the ADC, and a differential input of +1V corresponds to the full-scale code (4095 LSB). VCM (common-mode voltage of REFT and REFB) is also made available externally through a pin, and is nominally 1.5V. The ADC employs a pipelined converter architecture consisting of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 10-bit level. The pipeline architecture results in a data latency of 6.5 clock cycles. The output of the ADC goes to a serializer that operates from a 12X clock generated by the PLL. The 10 data bits from each channel are serialized and output LSB first. In addition to serializing the data, the serializer also generates a 1X clock and a 6X clock. These clocks are generated in the same way the serialized data is generated, so these clocks maintain perfect synchronization with the data. The data and clock outputs of the serializer are buffered externally using LVDS buffers. Using LVDS buffers to transmit data externally has multiple advantages, such as reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the analog circuit inside the ADS5275. The ADS5275 operates from two sets of supplies and grounds. The analog supply/ground set is denoted as AVDD/AVSS, while the digital set is denoted by LVDD/LVSS. 14 DRIVING THE ANALOG INPUTS The analog input biasing is shown in Figure 2. The recommended method to drive the inputs is through AC coupling. AC coupling removes the worry of setting the common-mode of the driving circuit, since the inputs are biased internally using two 600Ω resistors. The sampling capacitor used to sample the inputs is 4pF. The choice of the external AC coupling capacitor is dictated by the attenuation at the lowest desired input frequency of operation. The attenuation resulting from using a 10nF AC coupling capacitor is 0.04%. ADS5275 IN+ 600Ω Input Circuitry 600Ω IN− CM Buffer 1 Internal Voltage Reference VCM CM Buffer 2 Figure 2. Analog Input Bias Circuitry If the input is DC-coupled, then the output common-mode voltage of the circuit driving the ADS5275 should match the VCM (which is provided as an output pin) to within ±50mV. It is recommended that the output common-mode of the driving circuit be derived from VCM provided by the device. The sampling circuit consists of a low-pass RC filter at the input to filter out noise components that might be getting differentially coupled on the input pins. The inputs are sampled on two 4pF capacitors. The sampling on the capacitors is done with respect to an internally generated common-mode voltage (INCM). The switches connecting the sampling capacitors to the INCM are opened out first (before the switches connecting them to the analog inputs). This ensures that the charge injection arising out of the switches opening is independent of the input signal amplitude to a first-order of approximation. SP refers to a sampling clock whose falling edge comes an instant before the SAMPLE clock. The falling edge of SP determines the sampling instant. ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 15Ω IN+ 1.5pF Sample 4pF SP (defines sampling instant) 1.7pF SP 4pF 15Ω IN− 1.5pF Sample SP INCM Figure 3. Input Circuitry INPUT OVER-VOLTAGE RECOVERY The differential full-scale input peak-to-peak voltage supported by the ADS5275 is 2V. For a nominal value of VCM (1.5V), INP and INN can swing from 1V to 2V. The ADS5275 is specially designed to handle an over-voltage differential peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP and INN). If the input common-mode is less than 300mV from VCM during overload, recovery from an over-voltage input condition is expected to be within 4 clock cycles. All of the amplifiers in the SHA and ADC are specially designed for excellent recovery from an overload signal. REFERENCE CIRCUIT DESIGN The digital beam-forming algorithm relies heavily on gain matching across all receiver channels. A typical system would have about 10 octal ADCs on the board. In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the ADCs to be the same. Matching references within the eight channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures the reference voltages are well-matched across different chips. All bias currents required for the internal operation of the device are set using an external resistor to ground at pin ISET. Using a 56kΩ resistor on ISET generates an internal reference current of 20µA. This current is mirrored internally to generate the bias current for the internal blocks. Using a larger external resistor at ISET reduces the reference bias current Buffering the internal bandgap voltage also generates a voltage called VCM, which is set to the midlevel of REFT and REFB, and is accessible on a pin. The internal buffer driving VCM has a drive of ±4mA. It is meant as a reference voltage to derive the input common-mode in case the input is directly coupled. The device also supports the use of external reference voltages. This involves forcing REFT and REFB externally. In this mode, the internal reference buffer is tri-stated. Since the switching current for the eight ADCs come from the externally-forced references, it is possible for the performance to be slightly less than when the internal references are used. It should be noted that in this mode, VCM and ISET continue to be generated from the internal bandgap voltage, as in the internal reference mode. It is therefore important to ensure that the common-mode voltage of the externally-forced reference voltages matches to within 50mV of VCM. CLOCKING The eight channels on the chip run off a single ADCLK input. To ensure that the aperture delay and jitter are same for all the channels, a clock tree network is used to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point all the way to the sample-and-hold. This ensures that the performance and timing for all the channels are identical. The use of the clock tree for matching introduces an aperture delay, which is defined as the delay between the rising edge of ADCLK and the actual instant of sampling. The aperture delays for all the channels are matched, and vary between 2.5ns to 4.5ns across devices. Another critical specification is the aperture jitter that is defined as the uncertainty of the sampling instant. The gates in the clock path are designed to give an rms jitter of about 1ps. The input ADCLK should ideally have a 50% duty cycle. However, while routing ADCLK to different components on board, the duty cycle of the ADCLK reaching the ADS5275 could deviate from 50%. A smaller (or larger) duty cycle eats into the time available for sample or hold phases of each circuit, and is therefore not optimal. For this reason, the internal PLL is used to generate an internal clock that has 50% duty cycle. The use of the PLL automatically dictates the lower frequency of operation to be about 20MHz. 15 PRODUCT PREVIEW INCM (internally generated voltage) and thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56k so that the internal bias margins for the various blocks are proper. ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 LVDS BUFFERS The LVDS buffer has two current sources, as shown in Figure 4. OUTP and OUTN are loaded externally by a resistive load that is ideally about 100Ω. Depending on the data being 0 or 1, the currents are directed in one or the other direction through the resistor. The LVDS buffer has four current settings. The default current setting is 3.5mA, and gives a differential drop of about ±350mV across the 100Ω resistor. High External Termination Resistor Low PRODUCT PREVIEW OUTP OUTN Low High Figure 4. LVDS Buffer The LVDS buffer gets data from a serializer that takes the output data from each channel and serializes it into a single data stream. For a clock frequency of 40MHz, the data rate output by the serializer is 480MBPS. The data comes out LSB first, with a register programmability to revert to MSB first. The serializer also gives out a 1X clock and a 6X clock. The 6X clock (denoted as LCLKP/LCLKN) is meant to synchronize the capture of the LVDS data. The deskew mode can be enabled as well, using a register setting. This mode gives out a data stream of alternate 0s and 1s and can be used to determine the relative delay between the 6X clock and the output data for optimum capture. A 1X clock is also generated by the serializer and transmitted by the LVDS buffer. The 1X clock (referred to as ADCLKP/ADCLKN) is used to determine the start of the 10-bit data frame. The sync mode (enabled through a register setting) gives out a data of six 0s 16 followed by six 1s. Using this mode, the 1X clock can be used to determine the start of the data frame. In addition to the deskew mode pattern and the sync pattern, a custom pattern can be defined by the user and output from the LVDS buffer. NOISE COUPLING ISSUES High-speed mixed signals are sensitive to various types of noise coupling. One of the main sources of noise is the switching noise from the serializer and the output buffers. Maximum care is taken to isolate these noise sources from the sensitive analog blocks. As a starting point, the analog and digital domains of the chip are clearly demarcated. AVDD and AVSS are used to denote the supplies for the analog sections, while LVDD and LVSS are used to denote the digital supplies. Care is taken to ensure that there is minimal interaction between the supply sets within the device. The extent of noise coupled and transmitted from the digital to the analog sections depends on the following: 1. The effective inductances of each of the supply/ground sets. 2. The isolation between the digital and analog supply/ground sets. Smaller effective inductance of the supply/ground pins leads to better suppression of the noise. For this reason, multiple pins are used to drive each supply/ground. It is also critical to ensure that the impedances of the supply and ground lines on board are kept to the minimum possible values. Use of ground planes in the board as well as large decoupling capacitors between the supply and ground lines are necessary to get the best possible SNR from the device. It is recommended that the isolation be maintained onboard by using separate supplies to drive AVDD and LVDD, as well as separate ground planes for AVSS and LVSS. The use of LVDS buffers reduces the injected noise considerably, compared to CMOS buffers. The current in the LVDS buffer is independent of the direction of switching. Also, the low output swing as well as the differential nature of the LVDS buffer results in low-noise coupling. ADS5275 www.ti.com SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004 POWER-DOWN MODE SUPPLY SEQUENCE The device has a power-down pin, PD. Pulling PD high causes the devices to enter the power-down mode. In this mode, the reference and clock circuitry as well as all the channels are powered down. Device power consumption drops to less than 100mW in this mode. Individual channels can also be selectively powered down by programming registers. The following supply sequence is recommended for powering up the device: 1. AVDD is powered up. 2. LVDD is powered up. PRODUCT PREVIEW The ADS5275 also has an internal circuit that monitors the state of stopped clocks. If ADCLK is stopped (or if it runs at a speed < 3MHz), this monitoring circuit generates a logic signal that puts the device in a power-down state. As a result, the power consumption of the device goes to less than 100mW when ADCLK is stopped. This circuit can also be disabled using register options. After the supplies have stabilized, it is required to give the device an active RESET pulse. This results in all internal registers getting reset to their default value of 0 (inactive). Without RESET, it is possible that some registers might be in their non-default state on power-up. This could cause the device to malfunction. 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS5275IPFP PREVIEW HTQFP PFP 80 96 ADS5275IPFPT PREVIEW HTQFP PFP 80 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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