ADS5273 SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 8-Channel, 12-Bit, 70MSPS ADC with Serialized LVDS Interface The ADS5273 provides an internal reference, or can optionally be driven with an external reference. Best performance can be achieved through the internal reference mode. FEATURES Maximum Sample Rate: 70MSPS 12-Bit Resolution No Missing Codes The device is available in a PowerPAD TQFP-80 package and is specified over a −40°C to +85°C operating range. Power Dissipation: 1.1W CMOS Technology Simultaneous Sample-and-Hold LCLKP 6X ADCLK 70.5dB SNR at 10MHz IF PLL ADCLKP 1X ADCLK ADCLK IN3P IN3N IN4P IN4N DESCRIPTION IN5P The ADS5273 is a high-performance, 70MSPS, 8-channel parallel analog-to-digital converter (ADC). An internal reference is provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS outputs reduce the number of interface lines and package size. In LVDS (low-voltage differential signaling), an integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 6. This high-frequency LVDS clock is used in the data serialization and transmission process and is converted to an LVDS signal for transmission in parallel with the data. Providing this additional LVDS clock allows for easy delay matching. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. The bit following the rising edge of the ADC clock output is the first bit of the word. IN5N IN6P IN6N IN7P IN7N IN8P IN8N S/H 12−Bit ADC Serializer S/H 12−Bit ADC Serializer S/H 12−Bit ADC Serializer S/H 12−Bit ADC Serializer S/H 12−Bit ADC Serializer S/H 12−Bit ADC Serializer 12−Bit ADC Serializer S/H INT/EXT OUT1N OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N OUT5P OUT5N OUT6P OUT6N OUT7P OUT7N OUT8P OUT8N Registers Reference OUT1P Control PD D Portable Ultrasound Systems D Tape Drives D Test Equipment Serializer RESET APPLICATIONS 12−Bit ADC SDATA IN2P IN2N S/H CS IN1P IN1N SCLK D Internal and External References D 3.3V Digital/Analog Supply D TQFP-80 PowerPAD Package ADCLKN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. ! Copyright 2004, Texas Instruments Incorporated www.ti.com PRODUCT PREVIEW LCLKN Serialized LVDS Outputs Meet or Exceed the Requirements of ANSI TIA/EIA-644-A Standard REFT VCM REFB D D D D D D D D "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage Range, AVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V Supply Voltage Range, LVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V Voltage Between AVSS and LVSS . . . . . . . . . . . . . . −0.3V to 0.3V Voltage Between AVDD and LVDD . . . . . . . . . . . . . . −0.3V to 0.3V Voltages Applied to External REF Pins . . . . . . . . . . −0.3V to 2.4V All LVDS Data and Clock Outputs . . . . . . . . . . . . . . −0.3V to 2.4V ADCLK Peak Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD Peak Total Input Current (all inputs) . . . . . . . . . . . . . . . . . . . −30mA Operating Free-Air Temperature Range, TA . . . . . . −40°C to 85°C Lead Temperature 1.6mm (1/16″ from case for 10s) . . . . . . 235°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PRODUCT PREVIEW ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5273 HTQFP-80 PFP −40°C to +85°C ADS5273IPFP ADS5273IPFP Tray, 96 ADS5273IPFPT Tape and Reel, 250 ″ ″ ″ ″ ″ (1) For the most current specification and package information, refer to our web site at www.ti.com. RECOMMENDED OPERATING CONDITIONS ADS5273 SUPPLIES AND REFERENCES Analog Supply Voltage, AVDD Output Driver Supply Voltage, LVDD CLOCK INPUT AND OUTPUTS ADCLK Input Sample Rate (low-voltage TTL), 1/tC Low Voltage Level Clock High Voltage Level Clock ADCLKP and ADCLKN Outputs (LVDS) LCLKP and LCLKN Outputs (LVDS)(1) Operating Free-Air Temperature, TA (1) 6 × ADCLK. MIN TYP MAX UNIT 3.0 3.0 3.3 3.3 3.6 3.6 V V 70 1 2 70 420 +85 MSPS V V MHz MHz °C 20 35 210 −40 REFERENCE SELECTION MODE INT/EXT DESCRIPTION 2.0VPP Internal Reference 1 Default with internal pull-up. External Reference 0 Internal reference is powered down. Common mode of external reference should be within 50mV of VCM. VCM is derived from the internal bandgap voltage. 2 "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 ELECTRICAL CHARACTERISTICS TMIN = −40°C, and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −0.5dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5273 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DC ACCURACY No Missing Codes Assured DNL Differential Nonlinearity INL Integral Nonlinearity Midscale Offset Error(1) TBD 0.5 TBD LSB TBD 1 TBD LSB TBD Offset Temperature Coefficient Fixed Gain Error(2) TBD TBD TBD 1.0 mV ppm/°C TBD %FS TBD ∆%/°C VIN = FS, FIN = 10MHz VIN = FS, FIN = 10MHz VIN = FS, FIN = 10MHz, LVDS Into 100Ω Load 333 mA 289 mA 44 mA VIN = FS, FIN = 10MHz 1.1 W VREFT Reference Top (internal) VREFN Reference Bottom (internal) 2.0 V 1.0 V VCM Common-Mode Voltage VCM Output Current 1.5 V TBD mA Gain Temperature Coefficient ICC Total Supply Current I(AVDD) Analog Supply Current I(LVDD) Digital Output Driver Supply Current Power Dissipation PRODUCT PREVIEW POWER SUPPLY REFERENCE VOLTAGES VREFT Reference Top (external) VREFB Reference Bottom (external) Reference Input Resistance(3) 1.875 V 1.125 V TBD ANALOG INPUT DC Differential Input Resistance 1.2 Differential Input Capacitance 7 Differential Input Voltage Range Input Bandwidth pF VCM ± 0.05 2.0 Analog Input Common-Mode Range Voltage Overload Recovery Time kΩ 1.5 Differential Input Signal at 4VPP Recovery to Within 1% of Code 4 −3dBFS 300 V VPP CLK Cycles MHz DIGITAL DATA OUTPUTS Data Bit Rate 420 840 MBPS SERIAL INTERFACE SCLK Serial Clock Input Frequency VIN LOW Input Low Voltage VIN HIGH Input High Voltage Input Current Input Pin Capacitance 0 2.1 20 0.6 VDD MHz V V µA pF TBD 5 (1) Offset Error is the measured deviation of the midscale transition from the ideal midscale transition. (2) Gain Error is the difference between the nominal and actual offset point on the transfer function after the offset error has been corrected to zero. The gain point is the mid-step value when the digital output is full-scale. (3) Average switching current drawn from external reference. DC component of current is internally generated even in external reference mode. 3 "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 AC CHARACTERISTICS TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −0.5dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted. ADS5273 PARAMETER CONDITIONS MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Spurious-Free Dynamic Range fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 20MHz 2nd-Order Harmonic Distortion fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 20MHz 3rd-Order Harmonic Distortion fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 20MHz Signal-to-Noise Ratio fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 20MHz SINAD Signal-to-Noise and Distortion fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 20MHz ENOB Effective Number of Bits SFDR HD2 HD3 PRODUCT PREVIEW SNR Crosstalk TBD TBD TBD TBD TBD fIN = 10MHz Signal Applied to 7 Channels; Measurement Taken on the Channel with No Input Signal 85 85 85 80 dBc dBc dBc dBc 90 87 80 76 dBc dBc dBc dBc 87 84 77 73 dBc dBc dBc dBc 70.5 70.5 70.5 70.5 dBFS dBFS dBFS dBFS 70 70 70 70 dBFS dBFS dBFS dBFS 11.3 Bits −85 dBc LVDS DIGITAL DATA AND CLOCK OUTPUTS Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 9pF. All LVDS specifications are characterized but not tested. PARAMETER CONDITIONS MIN TYP MAX UNITS RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 7 RLOAD = 100Ω ± 1% 925 1340 1038 1475 mV 325 350 375 1.125 1.250 1.275 DC SPECIFICATIONS VOH VOL VOD Output Voltage High, OUTP or OUTN Output Voltage Low, OUTP or OUTN Output Differential Voltage VOS RO Output Offset Voltage ∆RO CO Mismatch Between OUTP and OUTN Output Impedance, Single-Ended VCM = 1.0V and 1.4V VCM = 1.0V and 1.4V mV TBD % 5 pF ∆VOD Change in VOD Between 0 and 1 25 mV ∆VOS ISOUTP, ISOUTN Change Between 0 and 1 RLOAD = 100Ω ± 1% 25 mV Output Short-Circuit Current Drivers Shorted to Ground 40 mA Output Current Drivers Shorted Together 12 mA VCC = 0V 10 mA 55 % Any Differential Pair on Package(1) 50 ps Any Two Signals on Package(2) 100 ps Power-Off Output Leakage 4 V Ω TBD 3 mV VCM = 1.0V and 1.4V RLOAD = 100Ω ± 1% ISOUTNP IXN, IXP Output Capacitance RLOAD = 100Ω ± 1% RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 7 DRIVER AC SPECIFICATIONS Clock Clock Signal Duty Cycle tSKEW1 tpHLP − tpLHN or tpHLN − tpLHP, Differential Skew tSKEW2 tpDIFF[X] − tpDIFF[Y], Channel-to-Channel Skew(3) tRISE/tFALL VOD Rise Time or VOD Fall Time 6 × ADCLK 50 ZLOAD = 100Ω, CI = 9pF, IO = 2.5mA ZLOAD = 100Ω, CI = 9pF, IO = 3.5mA 400 250 ps ZLOAD = 100Ω, CI = 9pF, IO = 4.5mA 200 ps ZLOAD = 100Ω, CI = 9pF, IO = 6mA 150 ps (1) Skew measurements are made at the 50% point of the transition. (2) Skew measurements made at 0V differential (that is, the crossing of single-ended signals). (3) Where x is any one of the parallel channels and y is any other channel. 4 45 "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 SWITCHING CHARACTERISTICS TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −0.5dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted. PARAMETER CONDITIONS MIN SWITCHING SPECIFICATIONS tSAMPLE tD(A) Aperture Delay Aperture Jitter (uncertainty) tD(pipeline) Latency tPROP Propagation Delay TYP MAX UNITS 50 ns ps ps cycles ns 14.3 120 1 6.5 5 SERIAL INTERFACE TIMING Data is shifted in MSB first. Outputs change on next rising clock edge after CS goes high. PRODUCT PREVIEW ADCLK Start Sequence CS t1 Data latched on each rising edge of SCLK. t2 SCLK t3 MSB SDATA D6 D5 D4 D3 D2 D1 D0 t4 t5 PARAMETER DESCRIPTION MIN t1 t2 t3 t4 t5 Serial CLK Period Serial CLK High Time Serial CLK Low Time Data Setup Time Data Hold Time 50 13 13 5 5 TYP MAX UNIT ns ns ns ns ns 5 "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 SERIAL INTERFACE TIMING ADDRESS D6 D5 D4 0 0 0 0 0 0 PRODUCT PREVIEW DATA D7 0 0 0 0 0 1 1 D3 D2 0 0 1 1 0 1 0 1 DESCRIPTION D1 0 0 1 1 0 1 0 1 1 0. LVDS BUFFERS Normal ADC Output Deskew Pattern Sync Pattern Custom Pattern Output Current in LVDS = 3.5mA Output Current in LVDS = 2.5mA Output Current in LVDS = 4.5mA Output Current in LVDS = 6.0mA 1 1 1 0 0 1 D2 X 0 1 D1 X X X D0 1 X X D3 D2 D1 D0 X X X X D3 D2 D1 D0 X X X X D3 MSB X X D2 X X X D1 X X X D0 X X LSB 0 2X LVDS Clock Input Current LSB Mode MSB Mode 2. POWER-DOWN ADC CHANNELS 1 0 1 0 Power-Down Channels 1 to 4; D3 is for Channel 4 and D0 for Channel 1 3. POWER-DOWN ADC CHANNELS Power-Down Channels 5 to 8; D3 is for Channel 8 and D0 for Channel 5 Bits for Custom Pattern TEST PATTERNS(1) Deskew 101010101010 Sync 000000111111 Custom Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. (1) Default is LSB first. If MSB is selected the above patterns will be reversed. 6 Patterns Get Reversed in MSB First Mode of LVDS 1. LSB/MSB MODE D3 0 0 0 CUSTOM PATTERN (registers 4-6) 0 0 0 REMARKS D0 Example: 1010 Powers Down Channels 4 and 2 and Keeps Channels 1 and 3 Alive "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 LVDS TIMING DIAGRAM (PER ADC CHANNEL) Sample n Sample n+6 Input 1 fS ADCLK tSAMPLE 2 LCLKP 6X ADCLK LCLKN OUTP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 SERIAL DATA OUTN PRODUCT PREVIEW Sample n data ADCLKP 1X ADCLK ADCLKN tPROP 6.5 Clock Cycles RESET TIMING t1 +AVDD Power Supply t1 > TBD t2 > 100ns 0V +AVDD RESET 0V t2 POWER-DOWN TIMING Device Fully Powers Down 10µs PDN 1µs Device Fully Powers Up 7 "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 PIN CONFIGURATION PRODUCT PREVIEW AVSS SCLK SDA CS AVDD AVSS AVSS AVSS ADCLK AVDD INT/EXT AVSS REFT REFB VCM ISET AVDD AVSS AVSS TQFP AVSS Top View 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVDD 1 60 AVDD IN1P 2 59 IN8N IN1N 3 58 IN8P AVSS 4 57 AVSS IN2P 5 56 IN7N IN2N 6 55 IN7P AVDD 7 54 AVDD AVSS 8 53 AVSS IN3P 9 52 IN6N IN3N 10 51 IN6P ADS5273 AVSS 11 50 AVSS IN4P 12 49 IN5N IN4N 13 48 IN5P AVDD 14 47 AVDD LVSS 15 46 LVSS PD 16 8 45 RESET LVSS 17 44 LVSS LVSS 18 43 LVSS 33 34 35 36 37 38 39 40 OUT8N OUT3N 32 OUT8P OUT3P 31 OUT7N LVSS 30 OUT7P LVDD 29 LVSS 28 LVDD 27 OUT6N 26 OUT6P 25 OUT5N 24 OUT5P 23 OUT4N 22 OUT4P 21 OUT2N 41 ADCLKP OUT2P LCLKN 20 OUT1N 42 ADCLKN OUT1P LCLKP 19 "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 NAME PIN # NUMBER OF PINS I/O DESCRIPTION AVDD AVSS LVDD LVSS IN1P IN1N IN2P IN2N IN3P IN3N IN4P IN4N IN5P IN5N IN6P IN6N IN7P IN7N IN8P IN8N REFT REFB VCM INT/EXT PD LCLKP LCLKN ADCLK OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N OUT5P OUT5N OUT6P OUT6N OUT7P OUT7N OUT8P OUT8N ADCLKP ADCLKN ISET RESET CS SDA SCLK 1, 7, 14, 47, 54, 60, 63, 70, 75 4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80 25, 35 15, 17, 18, 26, 36, 43, 44, 46 2 3 5 6 9 10 12 13 48 49 51 52 55 56 58 59 67 66 65 69 16 19 20 71 21 22 23 24 27 28 29 30 31 32 33 34 37 38 39 40 41 42 64 45 76 77 78 8 14 2 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I I I I I I I I I I I I I I I I I I I I I/O I/O O I I O O I O O O O O O O O O O O O O O O O O O I/O I I I I Analog Power Supply Analog Ground LVDS Power Supply LVDS Ground Channel 1 Differential Analog Input High Channel 1 Differential Analog Input Low Channel 2 Differential Analog Input High Channel 2 Differential Analog Input Low Channel 3 Differential Analog Input High Channel 3 Differential Analog Input Low Channel 4 Differential Analog Input High Channel 4 Differential Analog Input Low Channel 5 Differential Analog Input High Channel 5 Differential Analog Input Low Channel 6 Differential Analog Input High Channel 6 Differential Analog Input Low Channel 7 Differential Analog Input High Channel 7 Differential Analog Input Low Channel 8 Differential Analog Input High Channel 8 Differential Analog Input Low Reference Top Voltage Reference Bottom Voltage Common-Mode Output Voltage Internal/External Reference Select; 0 = External, 1 = Internal Power-Down; 0 = Normal, 1 = Power-Down Positive LVDS Clock Negative LVDS Clock Data Converter Clock Input Channel 1 Positive LVDS Data Output Channel 1 Negative LVDS Data Output Channel 2 Positive LVDS Data Output Channel 2 Negative LVDS Data Output Channel 3 Positive LVDS Data Output Channel 3 Negative LVDS Data Output Channel 4 Positive LVDS Data Output Channel 4 Negative LVDS Data Output Channel 5 Positive LVDS Data Output Channel 5 Negative LVDS Data Output Channel 6 Positive LVDS Data Output Channel 6 Negative LVDS Data Output Channel 7 Positive LVDS Data Output Channel 7 Negative LVDS Data Output Channel 8 Positive LVDS Data Output Channel 8 Negative LVDS Data Output Positive LVDS ADC Clock Output Negative LVDS ADC Clock Output Bias Current Setting Resistor Reset to Default; 0 = Reset, 1 = Normal Chip Select; 0 = Select, 1 = No Select Serial Data Input Serial Data Clock 9 PRODUCT PREVIEW PIN DESCRIPTIONS "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS TMIN = −40°C, and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −0.5dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5273 Spectral Performance 0 fIN = 10MHz SNR = 70.5dBFS SFDR = 88dBc SINAD = 70dBFS Amplitude (dB) −20 −40 −60 −80 −100 −120 PRODUCT PREVIEW 0 5 10 15 20 Frequency (MHz) 10 25 30 35 "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 THEORY OF OPERATION DRIVING THE ANALOG INPUTS OVERVIEW The analog input biasing is shown in Figure 1. The recommended method to drive the inputs is through AC coupling. AC coupling removes the worry of setting the common-mode of the driving circuit, since the inputs are biased internally using two 600Ω resistors. The sampling capacitor used to sample the inputs is 4pF. The choice of the external AC coupling capacitor is dictated by the attenuation at the lowest desired input frequency of operation factor. The attenuation resulting from using a 10nF AC coupling capacitor is 0.04%. The ADC employs a pipelined converter architecture consisting of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The pipeline architecture results in a data latency of 6.5 clock cycles. The output of the ADC goes to a serializer that operates from a 12X clock generated by the PLL. The 12 data bits from each channel are serialized and sent LSB first. In addition to serializing the data, the serializer also generates a 1X clock and a 6X clock. These clocks are generated in the same way the serialized data is generated, so these clocks maintain perfect synchronization with the data. The data and clock outputs of the serializer are buffered externally using LVDS buffers. Using LVDS buffers to transmit data externally has multiple advantages, such as a reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the analog circuit inside the ADS5273. The ADS5273 operates from two sets of supplies and grounds. The analog supply/ground set is denoted as AVDD/AVSS, while the digital set is denoted by LVDD/LVSS. ADS5273 IN+ 600Ω Input Circuitry 600Ω IN− CM Buffer 1 Internal Voltage Reference VCM CM Buffer 2 Figure 1. Analog Input Bias Circuitry If the input is DC coupled, then the output common-mode voltage of the circuit driving the ADS5273 should match the VCM (which is provided as an output pin) to within ±50mV. It is recommended that the output common-mode of the driving circuit be derived from VCM provided by the device. INPUT OVER-VOLTAGE RECOVERY The differential full-scale input peak-to-peak supported by the ADS5273 is 2V. For a nominal value of VCM (1.5V), INP and INN can swing from 1V to 2V. The ADS5273 is specially designed to handle an over-voltage differential peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP and INN). If the input common-mode is not considerably off from VCM during overload (less than 300mV), recovery from an over-voltage input condition is expected to be within 4 clock cycles. All of the amplifiers in the SHA and ADC are especially designed for excellent recovery from an overload signal. 11 PRODUCT PREVIEW The ADS5273 is an 8-channel, high-speed, CMOS ADC, consisting of a high-performance sample-and-hold circuit at the input, followed by a 12-bit ADC. The 12 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the ADS5273 operate from a single clock referred to as ADCLK. The sampling clock for each of the eight channels is generated from the input clock using a carefully matched clock buffer tree. The 12X clock required for the serializer is generated internally from ADCLK using a phase lock loop (PLL). A 6X and a 1X clock are also output in LVDS format along with the data to enable easy data capture. The ADS5273 operates from an internally generated reference voltage that is trimmed to ensure matching across multiple devices on a board. This feature eliminates the need for external routing of reference lines and also improves matching of the gain across devices. The nominal values of REFP and REFN are 2V and 1V, respectively. These values imply that a differential input of −1V corresponds to the zero code of the ADC, and a differential input of +1V corresponds to the full-scale code (4095 LSB). VCM (common-mode voltage of REFP and REFN) is also made available externally through a pin, and is nominally 1.5V. "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 REFERENCE CIRCUIT DESIGN PRODUCT PREVIEW The digital beam-forming algorithm relies heavily on gain matching across all receiver channels. A typical system would have about 12 octal ADCs on the board. In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the ADCs to be the same. Matching references within the eight channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures the reference voltages are well matched across different chips. All bias currents required for the internal operation of the device are set using an external resistor to ground at pin ISET. Using a 56kΩ resistor on ISET generates an internal reference current of 20µA. This current is mirrored internally to generate the bias current for the internal blocks. Using a larger external resistor at ISET reduces the reference bias current and thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56k so that the internal bias margins for the various blocks are proper. Buffering the internal bandgap voltage also generates a voltage called VCM, which is set to the midlevel of REFT and REFB, and is accessible on a pin. The internal buffer driving VCM has a drive of ±4mA. It is meant as a reference voltage to derive the input common-mode in case the input is directly coupled. The device also supports the use of external reference voltages. This involves forcing REFT and REFB externally. In this mode, the internal reference buffer is tri-stated. Since the switching current for the eight ADCs come from the externally forced references, it is possible for the performance to be slightly less than when the internal references are used. It should be noted that in this mode, VCM and ISET continue to be generated from the internal bandgap voltage, as in the internal reference mode. It is therefore important to ensure that the common-mode voltage of the externally forced reference voltages matches to within 50mV of VCM. CLOCKING The eight channels on the chip run off a single ADCLK input. To ensure that the aperture delay and jitter are same for all the channels, a clock tree network is used to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point all the way to the sample-and-hold. This ensures that the performance and timing for all the channels are identical. The use of the clock tree for matching introduces an aperture delay, which is defined as the delay between the rising edge of ADCLK and the actual instant of sampling. The aperture delays for all the channels are matched, and vary between 2.5ns to 4.5ns. 12 Another critical specification is the aperture jitter that is defined as the uncertainty of the sampling instant. The gates in the clock path are designed so as to give an rms jitter of about 1ps. The input ADCLK should ideally have a 50% duty cycle. However, while routing ADCLK to different components on board, the duty cycle of the ADCLK reaching the ADS5273 could deviate from 50%. A smaller (or larger) duty cycle eats into the time available for sample or hold phases of each circuit, and is therefore not optimal. For this reason, the internal PLL is used to generate an internal clock that has 50% duty cycle. The use of the PLL automatically dictates the lower frequency of operation to be about 20MHz. LVDS BUFFERS The LVDS buffer has two current sources, as shown in Figure 2. OUTP and OUTN are loaded externally by a resistive load that is ideally about 100Ω. Depending on the data being 0 or 1, the currents are directed in one or the other direction through the resistor. The LVDS buffer has four current settings. The default current setting is 3.5mA, and gives a differential drop of about ±350mV across the 100Ω resistor. High External Termination Resistor Low OUTP OUTN Low High Figure 2. LVDS Buffer The LVDS buffer gets data from a serializer that takes the output data from each channel and serializes it into a single data stream. For a clock frequency of 40MHz, the data rate output by the serializer is 480 MBPS. The data comes out LSB first, with a register programmability to revert to MSB first. The serializer also gives out a 1X clock and a 6X clock. The 6X clock (denoted as LCLKP/ LCLKN) is meant to synchronize the capture of the LVDS data. The deskew mode can be enabled as well, using a register setting. This mode gives out a data stream of alternate 0s and 1s and can be used determine the relative delay "#$%&' www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 between the 6X clock and the output data for optimum capture. A 1X clock is also generated by the serializer and transmitted by the LVDS buffer. The 1X clock (referred to as ADCLKP/ADCLK N) is used to determine the start of the 12-bit data frame. The sync mode (enabled through a register setting) gives out a data of six 0s followed by six 1s. Using this mode, the 1X clock can be used to determine the start of the data frame. In addition to the deskew mode pattern and the sync pattern, a custom pattern can be defined by the user and output from the LVDS buffer. It is recommended that the isolation be maintained on board by using separate supplies to drive AVDD and LVDD, as well as separate ground planes for AVSS and LVSS. NOISE COUPLING ISSUES POWER-DOWN MODE 1. The effective inductances supply/ground sets. of each of the 2. The isolation between the digital and analog supply/ground sets. Smaller effective inductance of the supply/ground pins leads to better suppression of the noise. For this reason, multiple pins are used to drive each supply/ground. It is also critical to ensure that the impedances of the supply and ground lines on board are kept to the minimum possible values. Use of ground planes in the board as well as large decoupling capacitors between the supply and ground lines are necessary to get the best possible SNR from the device. The ADS52763 has a power-down pin, PD. Pulling PD high causes the devices to enter the power-down mode. In this mode, the reference and clock circuitry as well as all the channels are powered down. Device power consumption drops to less than 100mW in this mode. Individual channels can also be selectively powered down by programming registers. The ADS5273 also has an internal circuit that monitors the state of stopped clocks. If ADCLK is stopped (or if it runs at a speed < 3MHz), this monitoring circuit generates a logic signal that puts the device in a power-down state. As a result, the power consumption of the device goes to less than 100mW when ADCLK is stopped. This circuit can also be disabled using register options. SUPPLY SEQUENCE The following supply sequence is recommended for powering up the device: 1. AVDD is powered up. 2. LVDD is powered up. After the supplies have stabilized, the device must receive an active RESET pulse. This results in all internal registers getting reset to their default value of 0 (inactive). Without RESET, it is possible that some registers might be in their non-default state on power-up. This could cause the device to malfunction. 13 PRODUCT PREVIEW High-speed mixed signals are sensitive to various types of noise coupling. One of the main sources of noise is the switching noise from the serializer and the output buffers. Maximum care is taken to isolate these noise sources from the sensitive analog blocks. As a starting point, the analog and digital domains of the chip are clearly demarcated. AVDD and AVSS are used to denote the supplies for the analog sections, while LVDD and LVSS are used to denote the digital supplies. Care is taken to ensure that there is minimal interaction between the supply sets within the device. The extent of noise coupled and transmitted from the digital to the analog sections depends on the following: The use of LVDS buffers reduces the injected noise considerably, compared to CMOS buffers. The current in the LVDS buffer is independent of the direction of switching. Also, the low output swing as well as the differential nature of the LVDS buffer results in low-noise coupling. PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5273IPFP PREVIEW HTQFP PFP 80 ADS5273IPFPT PREVIEW HTQFP PFP 80 96 Lead/Ball Finish MSL Peak Temp (3) None Call TI Call TI None Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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