WM8944B Mono Low-Power CODEC with Video Buffer DESCRIPTION FEATURES The WM8944B is a highly integrated low power hi-fi CODEC designed for portable devices such as digital still cameras. Up to 2 analogue inputs may be connected; a stereo digital microphone interface is also provided. Flexible output mixing options support single-ended and differential configurations, with outputs derived from the digital audio paths or from analogue bypass paths. Mono line output and mono BTL headphone/speaker drive is supported. Flexible digital mixing and powerful DSP functions are available. Programmable filters and other processes may be applied to the ADC and DAC signal paths simultaneously. The DSP functions include 5 notch filters, 5-band EQ, dynamic range control and the ReTune™ feature. The ReTune™ feature is a sophisticated digital filter that can compensate for imperfect characteristics of the housing, loudspeaker or microphone components in an application. The ReTune algorithm can provide acoustic equalisation and selective phase (delay) control of specific frequency bands. The WM8944B is controlled via a I2C or SPI interface. Additional functions include Digital beep generator, Video buffer, programmable GPIO functions, Frequency Locked Loop (FLL) for flexible clocking support and integrated LDO for low noise supply regulation. The WM8944B is supplied in 25-ball W-CSP package, ideal for portable systems. DCVDD DBVDD SPKVDD Hi-fi audio CODEC - 94dB SNR during ADC recording (‘A’ weighted) - 96dB SNR during DAC playback (‘A’ weighted) 2 analogue audio inputs Integrated bias reference for electret microphones Digital microphone interface (Stereo) Powerful digital mixing / DSP functions: - 5-notch filters - 5-band equalizer (EQ) - ReTune™ parametric filter - Dynamic range control and noise gate - Low-pass/High-pass filters - Direct Form 1 (DF1) programmable digital filter - 3D stereo enhancement (for digital mic input) Digital beep generator Mono line output Mono BTL headphone/speaker output driver I2S digital audio interface - sample rates 8kHz to 48kHz Frequency Locked Loop (FLL) frequency conversion / filter Video buffer function Integrated LDO low-noise voltage regulator 25-ball W-CSP package (2.38 x 2.38 x 0.7mm, 0.5mm pitch) APPLICATIONS VBIN Digital Still Cameras (DSC) Multimedia phones VBREFR VBOUT WM8944B CURRENT MODE VIDEO BUFFER AUX LINEOUT Analogue Mic Mux / PGA IN1/DMICDAT ADC L DAC L ADC / Record Digital Filters DMICDAT Digital Mic Interface DMICCLK (GPIO) DSP Core (L/HPF, 3D Surround, 5-notch filter, Re-Tune EQ, Dynamic Range Control) -1 OUTPUT MIXERS SPKOUTP DAC Digital Filters SPKOUTN Digital Beep Generator DIGITAL AUDIO INTERFACE FLL CONTROL INTERFACE GPIO SDA SCLK CS/GPIO1 CIFMODE/GPIO2 MCLK ADCDAT DACDAT LRCLK BCLK LDOVDD LDO LDOVOUT GND http://www.cirrus.com VMIDC Reference MICBIAS Copyright Cirrus Logic, Inc., 2010–2016 (All Rights Reserved) Rev 4.2 MAY ‘16 WM8944B TABLE OF CONTENTS DESCRIPTION ................................................................................................................ 1 FEATURES ..................................................................................................................... 1 APPLICATIONS.............................................................................................................. 1 TABLE OF CONTENTS .................................................................................................. 2 BLOCK DIAGRAM ......................................................................................................... 5 PIN CONFIGURATION ................................................................................................... 6 ORDERING INFORMATION ........................................................................................... 6 PIN DESCRIPTION ......................................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ................................................................................. 8 RECOMMENDED OPERATING CONDITIONS .............................................................. 8 THERMAL PERFORMANCE .......................................................................................... 9 ELECTRICAL CHARACTERISTICS ............................................................................ 10 TERMINOLOGY ....................................................................................................................... 13 TYPICAL PERFORMANCE .......................................................................................... 14 TYPICAL POWER CONSUMPTION ........................................................................................ 15 AUDIO SIGNAL PATHS DIAGRAM ............................................................................. 16 SIGNAL TIMING REQUIREMENTS ............................................................................. 17 SYSTEM CLOCK TIMING ........................................................................................................ 17 AUDIO INTERFACE TIMING ................................................................................................... 17 MASTER MODE .................................................................................................................................................... 17 SLAVE MODE ....................................................................................................................................................... 18 CONTROL INTERFACE TIMING ............................................................................................. 19 DEVICE DESCRIPTION ............................................................................................... 21 INTRODUCTION ...................................................................................................................... 21 ANALOGUE INPUT SIGNAL PATH ......................................................................................... 22 INPUT PGA ENABLE ............................................................................................................................................ 22 INPUT PGA CONFIGURATION ............................................................................................................................ 23 MICROPHONE BIAS CONTROL .......................................................................................................................... 23 INPUT PGA GAIN CONTROL ............................................................................................................................... 24 DIGITAL MICROPHONE INTERFACE .................................................................................... 26 ANALOGUE-TO-DIGITAL CONVERTER (ADC) ...................................................................... 27 ADC VOLUME CONTROL..................................................................................................................................... 28 ADC HIGH PASS FILTER ..................................................................................................................................... 30 DSP CORE ............................................................................................................................... 31 DSP CONFIGURATION MODES .......................................................................................................................... 31 LOW-PASS / HIGH-PASS FILTER (LPF/HPF) ...................................................................................................... 32 3D SURROUND .................................................................................................................................................... 33 5-NOTCH FILTER ................................................................................................................................................. 34 DF1 FILTER........................................................................................................................................................... 35 HPF ....................................................................................................................................................................... 35 RETUNE FILTER................................................................................................................................................... 36 5-BAND EQ ........................................................................................................................................................... 36 DYNAMIC RANGE CONTROL (DRC) ................................................................................................................... 37 SIGNAL ENHANCEMENT REGISTER CONTROLS ............................................................................................. 37 DYNAMIC RANGE CONTROL (DRC) ..................................................................................... 39 DRC COMPRESSION / EXPANSION / LIMITING ................................................................................................. 39 GAIN LIMITS ......................................................................................................................................................... 43 GAIN READBACK ................................................................................................................................................. 44 DYNAMIC CHARACTERISTICS ........................................................................................................................... 44 ANTI-CLIP CONTROL ........................................................................................................................................... 46 2 Rev 4.2 WM8944B QUICK-RELEASE CONTROL ............................................................................................................................... 47 DRC INITIAL CONDITION ..................................................................................................................................... 47 DIGITAL-TO-ANALOGUE CONVERTER (DAC) ...................................................................... 48 DAC DIGITAL VOLUME CONTROL...................................................................................................................... 48 DAC AUTO-MUTE ................................................................................................................................................. 50 DAC SLOPING STOPBAND FILTER .................................................................................................................... 50 DIGITAL BEEP GENERATOR ................................................................................................. 51 OUTPUT SIGNAL PATH .......................................................................................................... 51 OUTPUT SIGNAL PATHS ENABLE ...................................................................................................................... 53 LINE OUTPUT MIXER CONTROL ........................................................................................................................ 54 SPEAKER PGA MIXER CONTROL ...................................................................................................................... 55 SPEAKER PGA VOLUME CONTROL ................................................................................................................... 56 SPEAKER OUTPUT CONTROL............................................................................................................................ 58 ANALOGUE OUTPUTS ........................................................................................................... 59 LINE OUTPUT ....................................................................................................................................................... 59 SPEAKER OUTPUTS ............................................................................................................................................ 59 EXTERNAL COMPONENTS FOR LINE OUTPUT ................................................................................................ 59 LDO REGULATOR ................................................................................................................... 60 REFERENCE VOLTAGES AND MASTER BIAS ..................................................................... 62 POP SUPPRESSION CONTROL ............................................................................................ 64 DISABLED OUTPUT CONTROL ........................................................................................................................... 64 OUTPUT DISCHARGE CONTROL ....................................................................................................................... 65 DIGITAL AUDIO INTERFACE .................................................................................................. 67 MASTER AND SLAVE MODE OPERATION ......................................................................................................... 67 AUDIO DATA FORMATS ...................................................................................................................................... 68 COMPANDING ...................................................................................................................................................... 71 AUDIO INTERFACE LOOPBACK ......................................................................................................................... 73 ADC TO DAC LOOPBACK .................................................................................................................................... 74 DIGITAL PULL-UP AND PULL-DOWN .................................................................................................................. 75 CLOCKING AND SAMPLE RATES.......................................................................................... 75 DIGITAL MIC CLOCKING ..................................................................................................................................... 78 FREQUENCY LOCKED LOOP (FLL) .................................................................................................................... 78 EXAMPLE FLL CALCULATION............................................................................................................................. 82 EXAMPLE FLL SETTINGS .................................................................................................................................... 83 VIDEO BUFFER ....................................................................................................................... 84 RECOMMENDED VIDEO BUFFER INITIALISATION SEQUENCES.................................................................... 86 GENERAL PURPOSE INPUT/OUTPUT .................................................................................. 88 GPIO FUNCTION SELECT ................................................................................................................................... 89 INTERRUPTS .......................................................................................................................... 90 CONTROL INTERFACE........................................................................................................... 92 SELECTION OF CONTROL INTERFACE MODE ................................................................................................. 92 2-WIRE (I2C) CONTROL MODE ........................................................................................................................... 93 3-WIRE (SPI) CONTROL MODE ........................................................................................................................... 95 Rev 4.2 3 WM8944B POWER MANAGEMENT ......................................................................................................... 96 THERMAL SHUTDOWN .......................................................................................................... 98 POWER ON RESET ................................................................................................................ 98 SOFTWARE RESET AND DEVICE ID................................................................................... 100 RECOMMENDED POWER UP / POWER-DOWN SEQUENCES............................... 101 REGISTER MAP ......................................................................................................... 103 REGISTER BITS BY ADDRESS ............................................................................................ 108 DIGITAL FILTER CHARACTERISTICS ..................................................................... 153 ADC FILTER RESPONSE...................................................................................................... 154 ADC HIGHPASS FILTER RESPONSE .................................................................................. 155 DAC FILTER RESPONSE...................................................................................................... 156 VIDEO BUFFER LOWPASS FILTER RESPONSE ................................................................ 158 APPLICATIONS INFORMATION ............................................................................... 159 RECOMMENDED EXTERNAL COMPONENTS .................................................................... 159 AUDIO INPUT PATHS ......................................................................................................................................... 159 LINE OUTPUT PATHS ........................................................................................................................................ 159 BTL SPEAKER OUTPUT CONNECTION ........................................................................................................... 160 POWER SUPPLY DECOUPLING ....................................................................................................................... 160 MICROPHONE BIAS CIRCUIT ........................................................................................................................... 161 VIDEO BUFFER COMPONENTS........................................................................................................................ 162 RECOMMENDED EXTERNAL COMPONENTS DIAGRAM ................................................................................ 163 PCB LAYOUT CONSIDERATIONS ....................................................................................... 163 PACKAGE DIMENSIONS ........................................................................................... 164 IMPORTANT NOTICE ................................................................................................ 165 REVISION HISTORY .................................................................................................. 166 4 Rev 4.2 IN1/DMICDAT DCVDD 5k 50k 250k 50k 250k SPKVDD LDO ADCREF, DACREF ADC / Record Digital Filters VBIN Digital Mic Interface ADC L DIGITAL AUDIO INTERFACE DSP Core (L/HPF, 3D, 5-notch filter, Re-Tune EQ, Dynamic Range Control) Digital Beep Generator DAC Digital Filters VBOUT 4k DMICCLK (GPIO) INPGA -12dB to +35.25dB in 0.75dB steps VBREFR DMICDAT DBVDD - Rev 4.2 + AUX clamp LPF DAC LDOVDD FLL SYSCLK -1 BYPASS IN1 AUX DAC DAC BYPASS AUX/IN1 DIFF CONTROL INTERFACE + - IN1 AUX INVERTED DAC + - AUX/IN1 DIFF BYPASS IN1 AUX INVERTED DAC + MIXSPK + MIXOUT GPIO SPKPGA -57dB to +6dB in 1dB steps -1 SPKOUTN + SPKOUTP + WM8944B SPKOUTN SPKOUTP LINEOUT WM8944B BLOCK DIAGRAM CIFMODE/GPIO2 CS/GPIO1 SCLK SDA MCLK BCLK LRCLK DACDAT ADCDAT LDOVDD LDOVOUT VMIDC GND MICBIAS 5 WM8944B PIN CONFIGURATION The WM8944B is supplied in a 25-ball CSP format. The pin configuration is illustrated below, showing the top-down view from above the chip. 1 2 3 4 5 A SPKVDD LINEOUT VMIDC LDOVOUT MICBIAS B SPKOUTN SPKOUTP AUX IN1/ DMICDAT LDOVDD TOP VIEW – WM8944B C CIFMODE/ GPIO2 GND SDA SCLK CS/ GPIO1 D BCLK LRCLK DACDAT VBREFR VBOUT E MCLK DBVDD DCVDD ADCDAT VBIN ORDERING INFORMATION ORDER CODE WM8944BECS/R TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE -40C to +85C 25-ball W-CSP (Pb-free, tape and reel) MSL1 260oC Note: Reel quantity = 3500 6 Rev 4.2 WM8944B PIN DESCRIPTION PIN NO NAME A1 SPKVDD Supply TYPE Supply for speaker driver DESCRIPTION A2 LINEOUT Analogue Output Line mixer output A3 VMIDC Analogue Output Midrail voltage decoupling capacitor A4 LDOVOUT Supply LDO output voltage A5 MICBIAS Analogue Output Microphone bias output voltage B1 SPKOUTN Analogue Output Negative speaker mixer output B2 SPKOUTP Analogue Output Positive speaker mixer output B3 AUX Analogue Input Aux audio input B4 IN1/DMICDAT Analogue Input / Digital Input Analogue input / Digital Microphone data input B5 LDOVDD Supply LDO supply input Digital Input / Output Control interface mode select / GPIO2 C1 CIFMODE/GPIO2 C2 GND Supply Ground C3 SDA Digital Input / Output Control interface data input / output C4 SCLK Digital Input Control interface clock input C5 CS ¯¯ /GPIO1 Digital Input / Output 3-wire (SPI) Control Mode Chip Select / GPIO1 D1 BCLK Digital Input / Output Audio interface bit clock D2 LRCLK Digital Input / Output Audio interface left / right clock D3 DACDAT Digital Input DAC digital audio data input D4 VBREFR Analogue Output Video buffer current reference resistor connection D5 VBOUT Analogue Output Video buffer output E1 MCLK Digital Input Master clock input E2 DBVDD Supply Digital buffer (I/O) supply E3 DCVDD Supply Digital core supply E4 ADCDAT Digital Output ADC / Digital Microphone digital audio data output E5 VBIN Analogue Input Video buffer input Rev 4.2 7 WM8944B ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Cirrus Logic tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. MIN MAX Supply voltages (DCVDD) CONDITION -0.3V 2.5V Supply voltages (LDOVDD, DBVDD, SPKVDD) -0.3V 4.5V Voltage range digital inputs -0.7V DBVDD +0.7V Voltage range analogue inputs -0.7V LDOVDD +0.7V Operating temperature range, TA -40ºC +85ºC Junction temperature, TJMAX -40ºC +150ºC Storage temperature after soldering -65ºC +150ºC RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN TYP MAX UNIT Digital supply range (Core) DCVDD 1.62 1.8 1.98 V Digital supply range (I/O) DBVDD 1.62 3.3 3.6 V Analogue supply LDOVDD 2.4 3.3 3.6 V Speaker supply range SPKVDD 1.71 3.3 3.6 V Ground 8 GND 0 V Rev 4.2 WM8944B THERMAL PERFORMANCE Thermal analysis should be performed in the intended application to prevent the WM8944B from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the GND balls through thermal vias and into a large ground plane will aid heat extraction. Three main heat transfer paths exist to surrounding air as illustrated below in Figure 1: Package top to air (radiation). Package bottom to PCB (radiation). Package balls to PCB (conduction). W-CSP Package PCB Figure 1 Heat Transfer Paths The temperature rise TR is given by TR = PD * ӨJA PD is the power dissipated in the device. ӨJA is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. ӨJA is determined with reference to JEDEC standard JESD51-9. The junction temperature TJ is given by TJ = TA +TR, where TA is the ambient temperature. PARAMETER SYMBOL MIN TYP MAX UNIT Operating temperature range TA Operating junction temperature TJ -40 85 °C -40 125 Thermal Resistance ӨJB 26 °C/W ӨJA 70 °C/W °C (Junction to Board) Thermal Resistance (Junction to Ambient) Note: 1. Junction temperature is a function of ambient temperature and of the device operating conditions. The ambient temperature limits and junction temperature limits must both be observed. Rev 4.2 9 WM8944B ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Inputs (IN1, AUX) Maximum input signal level (changes in proportion to LDOVOUT) Single-ended input 1.0 INPGA_VOL = 0dB 0 dBV Pseudo-differential input 0.7 Vrms INPGA_VOL = 0dB -3.1 dBV Input resistance (IN1/DMICDAT) Input PGA path (+35.25dB) 4.5 k Input PGA path (0dB) 105 Input PGA path (-12dB) 160 Output mixer path (0dB) 15 Output mixer path (-6dB) 30 Direct speaker (0dB) 10 Direct speaker (-6dB) 20 Input PGA path (All gain settings) 96 k 10 pF Minimum programmable gain -12 dB Maximum programmable gain 35.25 dB 0.75 dB 92 dB 110 dB Minimum programmable gain -57 dB Maximum programmable gain 6 dB 1 dB 71 dB Input resistance (AUX) Input capacitance Vrms Analogue Inputs Programmable Gain Amplifier (PGA) Gain step size Guaranteed monotonic Mute attenuation Common Mode Rejection Ratio 1kHz input Speaker Output Programmable Gain Amplifier (PGA) Gain step size Guaranteed monotonic Mute attenuation ADC Input Path Performance (Input PGA to ADC) SNR (A-weighted) 84 94 dB THD -1dBFS input -83 -72 dB THD+N -1dBFS input -77 -70 dB PSRR (with respect to LDOVDD) 217Hz, 100mV pk-pk 77 1kHz, 100mV pk-pk 90 10 dB Rev 4.2 WM8944B PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Bypass to Line Output (IN1/AUX to LINEMIX Differential Input to LINEOUT, 10k / 50pF) SNR (A-weighted) INPGA_VOL = 0dB THD+N INPGA_VOL = 0dB 90 98 -89.5 dB -80 dB Bypass to Speaker Output (IN1/AUX to SPKMIX Differential Input to SPKOUTP/SPKOUTN, 8R BTL) SNR (A-weighted) SPKVOL = 0dB THD+N SPKVOL = 0dB 90 96 -75 dB -65 dB DAC Output Path Performance (DAC to LINEOUT, 10k / 50pF) Maximum output signal level (changes in proportion to LDOVOUT) 1 SNR (A-weighted) 85 Vrms 96 dB THD -80 -71 dB THD+N -78 -70 dB Mute attenuation 125 dB 217Hz, 100mV pk-pk 48 dB 1kHz, 100mV pk-pk 60 PSRR (with respect to LDOVDD) Line Output Resistance 10 k Line Output Capacitance 50 pF 1 Vrms DAC Output Path Performance (DAC to SPKOUTP or SPKOUTN, 10k / 50pF) Maximum output signal level (changes in proportion to LDOVOUT) SNR (A-weighted) 85 96 dB THD -78 -68 dB THD+N -76 -66 dB Speaker Output Performance (Speaker Output SPKOUTP/SPKOUTN, 8 BTL) SNR (A-weighted) THD 90 PO=150mW 96 0.03 dB % dB -68 PO=350mW THD+N PO=150mW PO=350mW Mute attenuation 2.944 % -30.6 dB 0.05 % -66 dB 3.72 % -28.6 dB 92 dB dB PSRR (with respect to LDOVDD) 217Hz 48 1kHz 60 PSRR (with respect to SPKVDD) 217Hz, 100mV pk-pk 89 1kHz, 100mV pk-pk 79 dB Speaker Resistance 8 Speaker Capacitance 50 pF Rev 4.2 11 WM8944B PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Inputs/Outputs Input high level 0.7DBVDD V Input low level 0.3DBVDD Output high level IOL = 1mA Output low level IOH = -1mA 0.8DBVDD V 0.2DBVDD Input capacitance 10 Input leakage V V pF All digital pins except CIFMODE -900 900 nA CIFMODE pin -90 90 uA 3.6 V LDO Regulator Input voltage LDOVDD Output voltage LDOVOUT LDO_REF_SEL = 0 3.0 V Dropout Voltage LDOVDDLDOVOUTLDOVDD - LDOVOUT ILOAD=50mA, LDOVOUT>2.4V 200 mV ILOAD=50mA, LDOVOUT≤2.4V 400 mV 50 mA 2.4 Maximum output current (see note) 3.3 Output voltage accuracy ILOAD = 50mA 2 % Quiescent current No Load 55 A 1 A 217Hz, 100mV pk-pk 40 dB 1kHz, 100mV pk-pk 49 Leakage current PSRR (with respect to LDOVDD) Video Buffer Maximum output voltage swing Voltage gain Vom Av f=100kHz, THD=1% 1.10 1.25 1.50 V pk-pk VB_GAIN = 1, RREF=187, RLOAD=75, RSOURCE=75 5.08 6 7.94 dB VB_GAIN = 0, RREF=187, RLOAD=75, RSOURCE=75 -0.92 0 1.94 dB Gain step size 6 dB Differential gain DG Vin = 1V pk-pk -2.0 0.3 +2.0 % Differential phase DP Vin = 1V pk-pk -2.0 0 +2.0 Deg 40 60 100 dB 0 40 75 mV SNR VSNR SYNC tip offset above GND VB_PD = 0 Third order Low Pass Filter response (referenced to 100kHz) 2.4MHz -0.5 0 0.5 dB 5.13MHz -0.5 -0.2 0.5 dB 9.04MHz -3.0 -1.6 0 dB 13.32MHz -11.0 -7.0 -3.0 dB VB_GAIN = 1 (+6dB) RREF=187, RLOAD=75, RSOURCE=75, 0dB gain PSRR (with respect to LDOVDD) PSRR 100kHz, 50mV pk-pk 60 dB Clocking MCLK frequency 30Hz 27MHz Hz FLL output frequency 2.045 50 MHz FLL lock time 12 2 ms Rev 4.2 WM8944B PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 2.7 2.85 V MICBIAS Bias voltage (changes in proportion to LDOVOUT) MICBIAS MICB_LVL = 0 2.55 MICB_LVL = 1 1.95 V Bias Current source VMICBIAS within +/-3% Output noise spectral density 1kHz to 20kHz 40 nV/Hz PSRR (with respect to LDOVDD) 217Hz, 100mV pk-pk 70 dB 1kHz, 100mV pk-pk 85 3 mA Bandgap Reference Bandgap Voltage -10% 1.5 +10% V Analogue Reference Levels Midrail Reference Voltage (changes in proportion to LDOVOUT) VMID Bandgap Reference VMID_REF_SEL = 1 1.5 V VMID_CTRL=1 BG_VSEL=01010 -10% 1.5 +10% V Note: The maximum LDO output current is the total internal and external load capability; internal circuits of the WM8944B will typically account for 25mA of this capacity. TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20Hz to 20kHz. This ratio is also called idle channel noise. (No Auto-zero or Mute function is employed). 2. Total Harmonic Distortion (dB) – THD is the difference in level between a 1kHz reference sine wave output signal and the first seven harmonics of the output signal. The amplitude of the fundamental frequency of the output signal is compared to the RMS value of the next seven harmonics and expressed as a ratio. 3. Total Harmonic Distortion plus Noise (dB) – THD+N is the difference in level between a 1kHz reference sine wave output signal and all noise and distortion products in the audio band. The amplitude of the fundamental reference frequency of the output signal is compared to the RMS value of all other noise and distortion products and expressed as a ratio. 4. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied. 5. Power Supply Rejection Ratio (dB) – PSRR is a measure of ripple attenuation between a power supply rail and a signal output path. With the signal path idle, a small sine wave ripple is applied to power supply rail. The amplitude of the supply ripple is compared to the amplitude of the output signal generated and is expressed as a ratio. 6. All performance measurements are carried out with 20kHz AES17 low pass filter for distortion measurements, and an A-weighted filter for noise measurement. Failure to use such a filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out-of-band noise; although it is not audible, it may affect dynamic specification values. Rev 4.2 13 WM8944B TYPICAL PERFORMANCE WM8944B_IN1_ADC_THD+NvsAmpl -60 -65 -70 -75 -80 d B F S -85 -90 -95 -100 -105 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 -40 -30 -20 -10 +0 -30 -20 -10 +0 dBV WM8944B_DAC_Lineout_THD+NvsAmpl -60 -65 -70 -75 -80 d B V -85 -90 -95 -100 -105 -110 -120 -110 -100 -90 -80 -70 -60 -50 dBFS WM8944B_DAC_Spkout_8BTL_350mW_THD+NvsAmpl +0 T -10 -20 -30 -40 d B r A -50 -60 -70 -80 -90 -100 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 dBFS 14 Rev 4.2 WM8944B TYPICAL POWER CONSUMPTION DCVDD DBVDD LDOVDD SPKVDD (mA) (mA) (mA) (mA) 1.8 3.3 3.3 3.3 Total (mA) Power (mW) -- -- -- 5.776E-05 -- 0.000 0.0016 0.007 0.00717 0.00133 0.017 0.054 0.113 0.012 0.00679 0.00138 0.133 0.270 0.245 0.017 0.00717 0.00133 0.271 0.525 Playback to Lineout (SE_CONFIG=DSP playback, no data) 2.55 0.127 1.5 0.00146 4.18 9.964 Playback to Speaker 8ohm BTL (SE_CONFIG=DSP playback, no data) 2.55 0.127 1.64 5.48 9.80 28.505 2.55 0.127 1.99 5.32 9.99 29.132 2.85 0.127 3.87 0.00134 8.7 18.325 IN1 to Record + Playback to Lineout + Speaker 8ohm BTL + MICBIAS (SE_CONFIG=DSP playback / record, no data) 4.01 / 5.03 0.126 6.22 5.48 15.8 46.2 / 48.1 IN1 to Record + Playback to Lineout + Speaker 8ohm BTL + MICBIAS + FLL (SE_CONFIG=DSP playback / record, no data) 5.32 / 6.29 0.265 6.22 5.48 17.3 49.1 / 50.8 IN1 to Record + Playback to Lineout + Speaker 8ohm BTL + MICBIAS + FLL + Video Buffer (SE_CONFIG=DSP playback / record, no data) 5.32 / 6.29 0.264 7.21 5.48 18.3 52.3 / 54.1 IN1 to Record + Playback to Lineout + Speaker 8ohm BTL with Low VMID + MICBIAS + FLL + Video Buffer (SE_CONFIG=DSP playback / record, no data) 5.32 / 6.27 0.264 7.56 5.32 18.5 53.0 / 54.7 IN1 to Record + Playback to Lineout + Speaker 8ohm BTL with Low VMID + MICBIAS + FLL + Video Buffer + Bandgap (SE_CONFIG=DSP playback / record, no data) 5.30 / 6.27 0.265 7.5 5.31 18.4 52.7 / 54.4 Condition Powerdown Supplies are all off except SPKVDD Powerdown (register settings are default value, no MCLK, THERR_ACT=0, CIFMODE/GPIO2 configured as an input) Powerdown (register settings are default value, MCLK=12.288MHz, THERR_ACT=0, CIFMODE/GPIO2 configured as an input) Powerdown (register settings are default value, MCLK=24.576MHz, THERR_ACT=0, CIFMODE/GPIO2 configured as an input) Playback Playback (Low VMID) Playback to Speaker 8ohm BTL with Low VMID (SE_CONFIG=DSP playback, no data) Record IN1 to Record (SE_CONFIG=DSP record, no data) Record and Playback Record and Playback (Low VMID) Rev 4.2 15 4k MICB_ENA MICB_LVL DMICCLK (GPIO) 5k 50k 250k 50k 250k LDO ADCREF, DACREF Digital Mic Interface DMIC_ENA ADCL_VOL[7:0] SPKVDD DMICDAT INPGA ADC L ADC / Record Digital Filters DSP Core (L/HPF, 3D, 5-notch filter, Re-Tune EQ, Dynamic Range Control) DIGITAL AUDIO INTERFACE ADC_HPF_MODE ADC_HPF_SR[1:0] ADC_HPF_CUT[1:0] ADC_HPF DAC_VOL[7:0] DAC DAC_ENA LDOVDD Digital Beep Generator BEEP_GAIN[3:0] BEEP_RATE[1:0] BEEP_ENA DAC Digital Filters DAC_SB_FLT VBOUT AUX_TO_N_INPGA DCVDD - 16 INPGA_ENA INPGA_VOL[5:0] ADCL_ENA VBIN IN1/DMICDAT DBVDD P_INPGA_SEL[1:0] VBREFR + AUX clamp LPF FLL SYSCLK -1 BYPASS IN1 AUX CONTROL INTERFACE + - AUXDIFF_TO_PGA BYP_TO_PGA AUX_TO_PGA IN1_TO_PGA DAC_TO_PGA MDAC_TO_PGA + - AUXDIFF_TO_OUT DAC_TO_OUT MDAC_TO_OUT AUX_TO_OUT IN1_TO_OUT BYP_TO_OUT + MIXSPK + MIXOUT GPIO PGA_TO_SPKP AUX_TO_SPKP -1 PGA_TO_SPKN IN1_TO_SPKN SPKPGA SPK_PGA_ENA SPK_VOL SPK_MIX_ENA SPK_MIX_MUTE OUT_ENA LINE_MUTE SPKOUTN + SPKN_SPKVDD_ENA SPKN_OP_ENA SPKN_OP_MUTE SPKOUTP + SPKP_SPKVDD_ENA SPKP_OP_ENA SPKP_OP_MUTE WM8944B SPKOUTN SPKOUTP LINEOUT WM8944B AUDIO SIGNAL PATHS DIAGRAM CIFMODE/GPIO2 CS/GPIO1 SCLK SDA MCLK BCLK LRCLK DACDAT ADCDAT LDOVDD LDOVOUT VMIDC GND MICBIAS Rev 4.2 WM8944B SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING tMCLKY MCLK tMCLKL tMCLKH Figure 2 Master Clock Timing Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25oC. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Master Clock Timing MCLK cycle time TMCLKY 0.037s MCLK duty cycle s 60:40 40:60 (= TMCLKH : TMCLKL) AUDIO INTERFACE TIMING MASTER MODE BCLK (Output) tDL LRCLK (Output) t DDA ADCDAT DACDAT t DST tDHT Figure 3 Audio Interface Timing - Master Mode Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode LRCLK propagation delay from BCLK falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 20 ns DACDAT setup time to BCLK rising edge tDST 20 ns DACDAT hold time from BCLK rising edge tDHT 10 ns Rev 4.2 17 WM8944B SLAVE MODE tBCY BCLK (input) tBCH tBCL LRCLK (input) tLRH tLRSU ADCDAT (output) tDD DACDAT (input) tDS tDH Figure 4 Audio Interface Timing – Slave Mode Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 20 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ADCDAT propagation delay from BCLK falling edge tDD DACDAT set-up time to BCLK rising edge tDS Audio Interface Timing - Slave Mode ns 20 20 ns ns Note: BCLK period must always be greater than or equal to MCLK period. 18 Rev 4.2 WM8944B CONTROL INTERFACE TIMING START STOP SCLK (input) t4 t3 t2 t8 t7 t1 t6 SDA t5 t9 Figure 5 Control Interface Timing - 2-wire (I2C) Control Mode Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL MIN SCLK Frequency TYP MAX UNIT 400 kHz SCLK Low Pulse-Width t1 1300 ns SCLK High Pulse-Width t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 SDA, SCLK Rise Time t6 300 ns SDA, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 Data Hold Time t9 Pulse width of spikes that will be suppressed tps Rev 4.2 ns 600 0 ns 900 ns 5 ns 19 WM8944B tCHO tCSU CS (input) tSCY SCLK (input) tSCH SDA (input) tSCL tDSU tDHO Figure 6 Control Interface Timing - 3-wire (SPI) Control Mode (Write Cycle) Note: The data is latched on the 32nd falling edge of SCLK after 32 bits have been clocked into the device. CS (input) SCLK (input) SDA (output) tDL Figure 7 Control Interface Timing - 3-wire (SPI) Control Mode (Read Cycle) Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER 20 SYMBOL MIN TYP MAX UNIT CS ¯¯ falling edge to SCLK rising edge tCSU 40 ns SCLK falling edge to CS ¯¯ rising edge tCHO 10 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDA to SCLK set-up time tDSU 40 ns SDA to SCLK hold time tDHO 10 ns Pulse width of spikes that will be suppressed tps 0 SCLK falling edge to SDA output transition tDL 5 ns 40 ns Rev 4.2 WM8944B DEVICE DESCRIPTION INTRODUCTION The WM8944B is a highly integrated low power hi-fi CODEC designed for portable devices such as digital still cameras and multimedia phones. Flexible analogue interfaces and powerful digital signal processing (DSP) in a 2.38 x 2.38mm footprint make it ideal for small portable devices. The WM8944B supports up to 2 analogue audio inputs. One single-ended or pseudo differential microphone / line input may be selected as the ADC input source. The analogue inputs can also be configured as inputs to the output mixers, either as two single ended inputs or as a differential pair. An integrated bias reference is provided to power standard electret microphones. A stereo digital microphone interface is also supported, with direct input to the DSP core. The hi-fi ADC and DAC operate at sample rates from 8kHz up to 48kHz. A high pass filter is available in the ADC path for removing DC offsets and suppressing low frequency noise such as mechanical vibration and wind noise. A digital tone (‘beep’) generator allows audio tones to be injected into the DAC output path. The WM8944B provides a powerful DSP capability for configurable filtering and processing of the digital audio path. The DSP provides low-pass / high-pass filtering, notch filters, 5-band EQ, dynamic range control (DRC) and a programmable DF1 digital filter. The tuned notch filters allow narrow frequency bands to be attenuated, to provide filtering of motor noise or other unwanted sounds; the 5band EQ allows the signal to be adjusted for user-preferences. The dynamic range control provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. The DF1 filter allows user-specified filters to be implemented in the digital signal chain. 3D stereo enhancement is provided; this may be used on the stereo digital microphone input path. The ReTune™ feature is a highly-configurable DSP algorithm which can be tailored to cancel or compensate for imperfect characteristics of the housing, loudspeaker or microphone components in the target application. The ReTune algorithm coefficients and register contents are calculated using Cirrus Logic’s WISCE™ software; lab bench tests and audio reference measurements must be performed in order to determine the optimum settings. The digital signal routing between the ADC, DAC and I2S digital audio interface can be configured in different ways according to the application requirements. The DSP functions may be applied to the ADC record path, the DAC playback path, or split between the two paths (refer to the DSP Configuration Modes section). Two analogue output mixers are provided, connected to 3 analogue output pins. A mono line output and mono BTL speaker may be connected to these outputs. The WM8944B incorporates an LDO regulator for compatibility with a wide range of supply rails; the internal LDO can also reduce any interference resulting from a noisy supply rail. The LDO regulator can also be used to provide a regulated supply voltage to other circuits. I2C or SPI control interface modes for read/write access to the register map. A single external clock provides timing reference for all the digital functions; an integrated Frequency Locked Loop (FLL) also provides flexibility to perform frequency conversions and to remove noise/jitter from the external clock. The FLL can be configured for reduced power consumption, or for different filtering requirements of the reference source. Additional functions include a current-mode video buffer providing excellent video signal reproduction at low operating voltages. Up to 2 GPIO pins may be configured for miscellaneous input/output, or for status indications from the temperature monitoring functions. Rev 4.2 21 WM8944B ANALOGUE INPUT SIGNAL PATH The WM8944B has two analogue input pins, which may be selected in different configurations. The analogue input paths can support line and microphone inputs, in single-ended or pseudo-differential modes. The analogue inputs IN1/DMICDAT AUX may be configured as inputs to the input PGA or to the output mixers as single-ended or differential signals. The input PGA (PGA) is routed to the Analogue to Digital converter (ADC). There is also a bypass path, enabling the signal to be routed directly to the output mixers. The WM8944B input signal paths and control registers are illustrated in Figure 8. WM8944B AUX AUX IN1 BYPASS P_INPGA_SEL[1:0] INPGA_ENA INPGA_VOL[5:0] ADCL_ENA ADC_HPF_MODE ADC_HPF_SR[1:0] ADC_HPF_CUT[1:0] ADC_HPF + IN1/DMICDAT ADC L INPGA - ADCL_VOL[7:0] AUX_TO_N_INPGA ADC / Record Digital Filters DMIC_ENA DMICDAT Digital Mic Interface DMICCLK (GPIO) Figure 8 Input Signal Paths INPUT PGA ENABLE The input PGA (Programmable Gain Amplifier) is enabled using the register bit INPGA_ENA, as described in Table 1. REGISTER ADDRESS R2 (02h) BIT 12 Power Management 1 LABEL INPGA_ENA DEFAULT 0 DESCRIPTION Input PGA Enable 0 = Disabled 1 = Enabled Table 1 Input PGA Enable To enable the input PGA, the reference voltage VMID and the bias current must also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls VMID_SEL and BIAS_ENA. 22 Rev 4.2 WM8944B INPUT PGA CONFIGURATION Microphone and Line level audio inputs can be connected to the WM8944B in single-ended or differential configurations. (These two configurations are illustrated in Figure 55 and Figure 56 in the section describing the external components requirements - see “Applications Information”.) For single-ended microphone inputs, the microphone signal is connected to the non-inverting input of the PGA (IN1/DMICDAT), whilst the inverting input of the PGA is connected to VMID. For differential microphone inputs, the non-inverted microphone signal is connected to the non-inverting input of the PGA (IN1/DMICDAT), whilst the inverted (or ‘noisy ground’) signal is connected to the inverting input pin (AUX). Line level inputs are connected in the same way as a single-ended microphone signal. The non-inverting input of the PGA (IN1/DMICDAT) is configured using the P_INPGA_SEL register bit. This register allows the selection of the two possible input pins to the PGA. The inverting input is configured using the AUX_TO_N_INPGA register bit. The registers for configuring the Input PGA are described in Table 2. REGISTER ADDRESS R39 (27h) BIT LABEL DEFAULT 9 AUX_TO_N_INP GA 0 P_INPGA_SEL [1:0] 01 Input ctrl DESCRIPTION Input PGA Inverting Input Select 0 = Connected to VMID 1 = Connected to AUX 1:0 Input PGA Non-Inverting Input Select 00 = Reserved 01 = Connected to IN1/DMICDAT 10 = Connected to AUX 11 = Reserved Table 2 Input PGA Configuration MICROPHONE BIAS CONTROL The WM8944B provides a low noise reference voltage suitable for biasing electret condenser (ECM) type microphones via an external resistor. Refer to the “Applications Information” section for recommended components. The MICBIAS voltage is enabled using the MICB_ENA register bit; the voltage can be selected using the MICB_LVL bit, as described in Table 3. REGISTER ADDRESS R2 (02h) BIT 4 LABEL MICB_ENA DEFAULT 0 Power Management 1 R39 (27h) DESCRIPTION Microphone Bias Enable 0 = Disabled 1 = Enabled 6 MICB_LVL Input Ctrl 0 Microphone Bias Voltage control 0 = 0.9 x LDOVOUT 1 = 0.65 x LDOVOUT Table 3 Microphone Bias Control Rev 4.2 23 WM8944B INPUT PGA GAIN CONTROL The volume control gain for the PGA is adjusted using the INPGA_VOL register field as described in Table 4. The gain range is -12dB to +35.25dB in 0.75dB steps. The gains on the inverting and noninverting inputs to the PGA are always equal. The input PGA can be muted using the INPGA_MUTE mute bit. To prevent "zipper noise", a zero-cross function is provided on the input PGA. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. The Input PGA volume control register fields are described in Table 4. REGISTER ADDRESS R40 (28h) BIT 7 LABEL INPGA_ZC DEFAULT 0 Input PGA gain ctrl DESCRIPTION Input PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 6 INPGA_MUTE 1 Input PGA Mute 0 = Disable Mute 1 = Enable Mute 5:0 INPGA_VOL [5:0] 01_0000 Input PGA Volume (0dB) 00_0000 = -12dB 00_0001 = -11.25dB … 01_0000 = 0dB ... 11_1111 = +35.25 (See Table 5 for volume range) Table 4 Input PGA Volume Control 24 Rev 4.2 WM8944B INPGA_VOL[5:0] VOLUME INPGA_VOL[5:0] (dB) VOLUME (dB) 00_0000 -12 10_0000 12 00_0001 -11.25 10_0001 12.75 00_0010 -10.5 10_0010 13.5 00_0011 -9.75 10_0011 14.25 00_0100 -9 10_0100 15 00_0101 -8.25 10_0101 15.75 00_0110 -7.5 10_0110 16.5 00_0111 -6.75 10_0111 17.25 00_1000 -6 10_1000 18 00_1001 -5.25 10_1001 18.75 00_1010 -4.5 10_1010 19.5 00_1011 -3.75 10_1011 20.25 00_1100 -3 10_1100 21 00_1101 -2.25 10_1101 21.75 00_1110 -1.5 10_1110 22.5 00_1111 -0.75 10_1111 23.25 01_0000 0 11_0000 24 01_0001 0.75 11_0001 24.75 01_0010 1.5 11_0010 25.5 01_0011 2.25 11_0011 26.25 01_0100 3 11_0100 27 01_0101 3.75 11_0101 27.75 01_0110 4.5 11_0110 28.5 01_0111 5.25 11_0111 29.25 01_1000 6 11_1000 30 01_1001 6.75 11_1001 30.75 01_1010 7.5 11_1010 31.5 01_1011 8.25 11_1011 32.25 01_1100 9 11_1100 33 01_1101 9.75 11_1101 33.75 01_1110 10.5 11_1110 34.5 01_1111 11.25 11_1111 35.25 Table 5 Input PGA Volume Range Rev 4.2 25 WM8944B DIGITAL MICROPHONE INTERFACE The WM8944B supports a stereo digital microphone interface, using the IN1/DMICDAT input pin for data and a GPIO pin for the data clock. The analogue signal path from the IN1/DMICDAT pin must be disabled when using the digital microphone interface; this is achieved by disabling the input PGA, (ie. INPGA_ENA = 0). Note that, although the WM8944B is largely a mono device, it supports a stereo signal path from the digital microphone interface to the digital audio interface. DSP processing, including 3D stereo enhancement, can be enabled on this signal path - see the “DSP Core” section. The Digital Microphone Input, DMICDAT, is provided on the IN1/DMICDAT pin. The associated clock, DMICCLK, is provided on a GPIO pin. The Digital Microphone Input is selected as input by setting the DMIC_ENA bit. When the Digital Microphone Input is selected, the ADC input is deselected. The digital microphone interface configuration is illustrated in Figure 9. Note that the digital microphone may be powered from MICBIAS or from LDOVOUT; care must be taken to ensure that the respective digital logic levels of the microphone are compatible with the digital input thresholds of the WM8944B. The digital input thresholds are referenced to DBVDD, as defined in “Electrical Characteristics”. MICBIAS Input PGA ADC DMIC_ENA INPGA_ENA=0 Decimation ADCL_ENA ADCR_ENA SR[3:0] MICBIAS IN1/ DMICDAT DMIC DMICDAT DMICCLK DMIC interface HPF DRC ADC Volume Digital Audio Interface (ADCDAT) GPIO GPIOn Figure 9 Digital Microphone Interface When any GPIO pin is configured as DMICCLK output, the WM8944B outputs a clock which supports Digital Mic operation at the ADC sampling rate. The ADC and Record Path filters must be enabled and the ADC sampling rate must be set in order to ensure correct operation of all DSP functions associated with the digital microphone. Volume control for the Digital Microphone Interface signals is provided using the ADC Volume Control. The WM8944B supports stereo digital microphone operation. The ADCL_ENA register enables the Left channel; the ADCR_ENA register enables the Right channel. Note that only the digital blocks are enabled by the ADCR_ENA register. See “Analogue-to-Digital Converter (ADC)” for details of the ADC Enable and volume control functions. See “General Purpose Input/Output” for details of configuring the DMICCLK output. See “Clocking and Sample Rates” for the details of the sample rate control. When the DMIC_ENA bit is set, then the IN1 pin is used as the digital microphone input DMICDAT. Up to two microphones can share this pin; the two microphones are interleaved as illustrated in Figure 10. The digital microphone interface requires that MIC1 (Left Channel) transmits a data bit each time that DMICCLK is high, and MIC2 (Right Channel) transmits when DMICCLK is low. The WM8944B samples the digital microphone data in the middle of each DMICCLK clock phase. Each microphone must tri-state its data output when the other microphone is transmitting. 26 Rev 4.2 WM8944B DMICCLK pin hi-Z MIC1 output (Left Channel) 1 MIC2 output (Right Channel) 1 1 2 DMICDAT pin (Left/Right channels interleaved) 1 2 2 1 2 2 1 2 Figure 10 Digital Microphone Interface Timing The digital microphone interface control fields are described in Table 6. REGISTER ADDRESS R2 (02h) BIT 7 LABEL DMIC_ENA DEFAULT 0 Power Management 1 DESCRIPTION Enables Digital Microphone mode 0 = Audio DSP input is from ADC 1 = Audio DSP input is from digital microphone interface When DMIC_ENA = 0, the Digital microphone clock (DMICCLK) is held low. Table 6 Digital Microphone Interface Control ANALOGUE-TO-DIGITAL CONVERTER (ADC) The WM8944B uses a 24-bit sigma-delta ADC. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full-scale input level is proportional to LDOVOUT. See “Electrical Characteristics” section for further details. Any input signal greater than full scale may overload the ADC and cause distortion. The ADC and associated digital record filters are enabled by the ADCL_ENA register bit. The ADC digital blocks are also required for the digital microphone interface; the Left and Right digital microphone paths are enabled by ADCL_ENA and ADCR_ENA respectively. REGISTER ADDRESS R2 (02h) BIT 11 LABEL ADCR_ENA DEFAULT 0 Power Management 1 DESCRIPTION Right ADC Enable 0 = Disabled 1 = Enabled ADCR_ENA must be set to 1 when processing right channel data from the Digital Microphone. 10 ADCL_ENA 0 Left ADC Enable 0 = Disabled 1 = Enabled ADCL_ENA must be set to 1 when processing data from the ADC or from the Left Digital Microphone. Table 7 ADC Enable Control Rev 4.2 27 WM8944B ADC VOLUME CONTROL The output of the ADC (or digital microphone interface) can be digitally amplified or attenuated over a range from -71.625dB to +23.625dB in 0.375dB steps. The volume of each channel is controlled using ADCL_VOL or ADCR_VOL. The ADC Volume is part of the ADC Digital Filters block. The gain for a given eight-bit code X is given by: 0.375 (X-192) dB for 1 X 255; MUTE for X = 0 The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the ADCL_VOL or ADCR_VOL control data is loaded into the respective control register, but does not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to ADC_VU. This makes it possible to update the gain of both channels simultaneously. The output of the ADC or digital microphone (DMIC) interface can be digitally muted using the ADCL_MUTE or ADCR_MUTE bits. Both channels are muted simultaneously when the ADC_MUTEALL bit is set. REGISTER ADDRESS R25 (19h) BIT 8 LABEL ADC_MUTEALL DEFAULT DESCRIPTION 1 ADC Digital Mute for All Channels ADC Control 1 0 = Disable Mute 1 = Enable Mute on all channels R27 (1Bh) 12 ADC_VU 0 ADC Digital Vol ADC Volume Update Writing a 1 to this bit will cause Left and Right ADC / DMIC volume to be updated simultaneously 8 ADCL_MUTE 0 ADC / Left DMIC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 ADCL_VOL [7:0] 1100_0000 (0dB) ADC / Left DMIC Digital Volume 0000_0000 = mute 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB (See Table 9 for volume range) R28 (1Ch) Right ADC Digital Vol 12 ADC_VU 0 ADC Volume Update Writing a 1 to this bit will cause Left and Right ADC / Digital Mic volume to be updated simultaneously 8 ADCR_MUTE 0 Right DMIC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 ADCR_VOL [7:0] 1100_0000 Right DMIC Digital Volume 0000_0000 = mute 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB (See Table 9 for volume range) Table 8 ADC Digital Volume Control 28 Rev 4.2 WM8944B ADCL_VOL or ADCR_VOL Volume (dB) ADCL_VOL or ADCR_VOL Volume (dB) ADCL_VOL or ADCR_VOL Volume (dB) ADCL_VOL or ADCR_VOL Volume (dB) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 18.000 18.375 18.750 19.125 19.500 19.875 20.250 20.625 21.000 21.375 21.750 22.125 22.500 22.875 23.250 23.625 Table 9 ADC Digital Volume Range Rev 4.2 29 WM8944B ADC HIGH PASS FILTER A digital high-pass filter is enabled by default to the ADC path to remove DC offsets. This filter can also be used to remove low frequency noise in handheld applications (e.g. wind noise, handling noise or mechanical vibration). The ADC High Pass filter is enabled by ADC_HPF. Note that this filter must always be set when the Dynamic Range Controller (DRC) is enabled. The DRC will not function correctly if ADC_HPF is not set. The filter operates in one of two modes, selected by ADC_HPF_MODE. The ADC_HPF_SR register should be set according to the selected ADC sample rate. See “Clocking and Sample Rates” for details of the ADC sample rate. In Hi-Fi mode (ADC_HPF_MODE = 0), the high-pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.5Hz when the sample rate (fs) = 44.1kHz. In Application mode (ADC_HPF_MODE = 1), the HPF cut-off frequency is set using ADC_HPF_CUT. This mode is intended for voice communication; it is recommended to set the cut-off frequency below 300Hz (e.g. ADC_HPF_CUT = 101 when fs = 8kHz or fs = 16kHz). REGISTER ADDRESS BIT LABEL DEFAULT R26 (1Ah) ADC Control 2 6 ADC_HPF_MOD E 0 DESCRIPTION ADC Digital HPF Mode 0 = Hi-Fi mode (1st order) 1 = Application mode (2nd order) 5:4 ADC_HPF_SR [1:0] ADC Digital HPF Sample Rate 10 00 = 8kHz to 12kHz 01 = 16kHz to 24kHz 10 = 32kHz to 48kHz 11 = Reserved 3:1 0 ADC_HPF_CUT [2:0] 000 ADC Digital High Pass Filter Cutoff Note that the cut-off frequency scales with sample rate. See Table 11 for cut-off frequencies at all supported sample rates. ADC_HPF ADC Digital High Pass Filter Enable 1 0 = Disabled 1 = Enabled Table 10 ADC High-pass Filter Control Registers CUT-OFF FREQUENCY (Hz) SAMPLE FREQUENCY HI-FI (kHz) MODE APPLICATION MODE / ADC_HPF_CUT[2:0] 000 001 010 011 100 101 110 111 8.000 3.0 80.5 100.5 129.0 160.5 200.5 256.5 320.5 400.5 11.025 4.5 111.0 138.5 177.5 221.0 276.5 353.0 442.0 551.5 12.000 4.5 120.5 151.0 193.0 240.5 300.5 384.5 481.0 600.5 16.000 3.0 80.0 101.0 129.0 161.0 200.5 256.5 321.0 401.0 22.050 4.5 110.5 139.0 177.5 221.5 276.0 353.5 442.0 552.5 24.000 4.5 120.5 151.5 193.5 241.5 300.5 385.0 481.5 601.0 32.000 2.5 80.0 101.5 129.0 160.5 200.0 257.5 320.0 401.0 44.100 3.5 110.0 139.5 177.5 221.0 275.5 355.0 441.0 552.5 48.000 4.0 119.5 152.0 193.0 240.5 300.0 386.5 480.0 601.0 Table 11 ADC High-pass Filter Cut-off Frequencies 30 Rev 4.2 WM8944B Filter response plots for the ADC high-pass filter are shown in “Digital Filter Characteristics”. DSP CORE DSP Core is at the centre of the ADC / DAC / Digital Audio Interface (I2S) blocks. It provides signal routing, and also implements a number of configurable signal processing functions. The signal processing functions are arranged in three blocks, as follows: Signal Enhancement 1 (SE1) - Low-pass / High-pass filter, 3D-stereo enhancement, 5 notch filters, generic ‘Direct Form 1’ filter. Signal Enhancement 2 (SE2) – High Pass Filter, ReTune™ processing, 5-band equalizer. Signal Enhancement 3 (SE3) - Dynamic range control. Note that, although the WM8944B is largely a mono device, it supports a stereo signal path from the digital microphone interface to the digital audio interface. In the default configuration, the analogue input/output paths are associated with the Left channel of the digital audio interface. The DSP Configuration modes and each of the Signal Enhancement blocks is described in the following sections. DSP CONFIGURATION MODES The DSP Configuration Mode is determined using the SE_CONFIG register field; this configures the signal paths between the Signal Enhancement blocks and the ADC, Digital Microphone, DAC and Digital Audio interfaces. The supported DSP modes are illustrated in Figure 11. ADC (Left) ADC (Left) SE1 (LPF/HPF, 3D surround, 5-notch, DF1) SE1 (LPF/HPF, 5-notch, DF1) DAC SE2 (HPF, Re-Tune, 5-band EQ) Digital Mic Interface (Left + Right) SE2 (HPF, Re-Tune, 5-band EQ) Digital Mic Interface (Left + Right) SE3 (Dynamic Range Control) DIGITAL AUDIO INTERFACE DIGITAL AUDIO INTERFACE DSP Record Mode DSP Playback Mode BCLK LRCLK DACDAT ADCDAT BCLK LRCLK DACDAT ADCDAT ADC (Left) ADC (Left) SE1 (LPF/HPF, 3D surround, 5-notch, DF1) SE1 (LPF/HPF, 3D surround, 5-notch, DF1) SE2 (HPF, Re-Tune, 5-band EQ) DAC SE2 (HPF, Re-Tune, 5-band EQ) DAC SE3 (Dynamic Range Control) SE3 (Dynamic Range Control) Digital Mic Interface (Left + Right) Digital Mic Interface (Left + Right) DIGITAL AUDIO INTERFACE DIGITAL AUDIO INTERFACE DSP General Mode 2 DSP General Mode 1 BCLK LRCLK DACDAT ADCDAT BCLK LRCLK DACDAT ADCDAT Rev 4.2 DAC SE3 (Dynamic Range Control) 31 WM8944B Figure 11 DSP Configuration Modes Record mode enables the entire set of Signal Enhancement functions in the ADC / Digital Microphone path. The direct DAC path is also active, without any Signal Enhancement functions; this allows basic audio playback and digital beep generation. Playback mode enables the entire set of DSP functions in the DAC path. The direct ADC / Digital Microphone path is also active, without any DSP functions; this allows basic audio record functions to the host system. REGISTER ADDRESS R64 (40h) BIT LABEL 3:0 SE_CONFIG [3:0] SE Config Selection DEFAULT DESCRIPTION DSP Configuration Mode select 0000 0000 = Record mode 0001 = Playback mode 0010 = DSP General mode 1 0011 = DSP General mode 2 Table 12 DSP Configuration Mode Select LOW-PASS / HIGH-PASS FILTER (LPF/HPF) L/HPF 3D surround 5-notch filter DF1 filter Signal Enhancement Block 1 (SE1) The Low-pass / High-pass filter is part of the SE1 block. This first-order filter can be configured to be high-pass, low-pass; it can also be bypassed. The cut-off frequency is programmable; the default setting is bypass (OFF). The filters are enabled using the SE1_LHPF_L_ENA and SE1_LHPF_R_ENA register bits defined in Table 13. The 3D enhancement coefficients are programmed in registers R65 to R67. For the derivation of these registers, refer to the configuration tools supplied with the WM8944B Evaluation Kit. Example plots of the Low-pass / High-pass filter response are shown in Figure 12. 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 20 32 39.91 79.62 158.9 317 632.5 1.262k 2.518k 5.024k 10.02k 1kLPF.res Magnitude(dB) 1kHPF.res Magnitude(dB) 5kLPF.res Magnitude(dB) 5kHPF.res Magnitude(dB) 200LPF.res Magnitude(dB) 200HPF.res Magnitude(dB) 20k Rev 4.2 WM8944B Figure 12 Low-pass / High-pass Filter Responses 3D SURROUND L/HPF 3D surround 5-notch filter DF1 filter Signal Enhancement Block 1 (SE1) The 3D-stereo surround effect is part of the SE1 block. This function uses time delays and controlled cross-talk mechanisms to adjust the depth or width of the stereo audio. The 3D-stereo surround effect includes programmable high-pass or low-pass filtering to limit the 3D effect to specific frequency bands if required. The structure of the 3D surround processing is illustrated in Figure 13. forward_l + L z-n HPF LPF bypass cross_r cross_l R z-n HPF LPF bypass + forward_r Figure 13 3D Surround Processing The 3D surround depth is programmable; the default setting is OFF. The 3D surround processing can also be configured to create a mono mix of the Left and Right channels in the ADC path. Note that the 3D surround processing can only be used with the stereo digital microphone in the ADC path. The 3D enhancement is enabled on the left and right channels using the SE1_3D_L_ENA and SE1_3D_R_ENA register bits defined in Table 13. (Note that these bits can be enabled independently of each other.) The 3D enhancement coefficients are programmed in registers R68 to R70. For the derivation of these registers, refer to the configuration tools supplied with the WM8944B Evaluation Kit. Rev 4.2 33 WM8944B 5-NOTCH FILTER L/HPF 3D surround 5-notch filter DF1 filter Signal Enhancement Block 1 (SE1) The 5-notch filter is part of the SE1 block. This function allows up to 5 programmable frequency bands to be attenuated. The frequency and width of each notch is configurable; the depth of the attenuation may also be adjusted. The default setting is bypass (OFF). The notch filters are enabled on the left and right channels using the SE1_NOTCH_L_ENA and SE1_NOTCH_R_ENA register bits defined in Table 13. Note that, although the 5-notch filter can be enabled on the left/right channels independently, the parameters that define the notch filters apply equally to the left and right channels, when enabled. The notch filter coefficients are programmed in registers R72 to R91. For the derivation of these registers, refer to the configuration tools supplied with the WM8944B Evaluation Kit. Note that the notch filters should not be configured for centre-frequencies below 120Hz. To apply filtering at low frequencies, the SE1 High Pass Filter should be used. Typical applications for the notch filters are filtering of fixed-frequency noise or resonances; these might arise from a motor (eg. DSC zoom lens motor) or from characteristics of the application housing. Example plots of the Notch filter response are shown in Figure 14. Notch Response - Slave Mode - fc=1kHz, fb=100, 500, 1k, 5k, 10kHz Depth=100% Notch Response - Slave Mode - fc=1kHz, fb=1kHz Depth 0 to 100% +0 T +0 -10 T -10 -20 -20 -30 -30 d B V -40 d B V -50 -60 -70 -50 -60 -70 -80 -80 -90 -100 -40 -90 520 550 600 650 700 750 800 850 900 1k 1.2k -100 20 1.5k Hz 50 100 200 500 1k 2k 5k 10k 20k Hz 1kHz notch, bandwidth 1kHz, depth 0% to 100% in 20% steps 1kHz notch, 100% depth, bandwidth 100Hz, 500Hz, 1kHz, 5kHz, 10kHz Notch Response - Slave Mode - fc=200, 500, 1k, 2k, 5k, 10kHz, fb=fc/2, Depth 100% +0 T -10 -20 -30 d B V -40 -50 -60 -70 -80 -90 -100 100 200 500 1k 2k 5k 10k 20k Hz 6 notches, bandwidth Fcentre/2, depth 100% Figure 14 Notch Filter Responses 34 Rev 4.2 WM8944B DF1 FILTER L/HPF 3D surround 5-notch filter DF1 filter Signal Enhancement Block 1 (SE1) The DF1 filter is part of the SE1 block. This provides a direct-form 1 standard filter, as illustrated in Figure 15. The default coefficients give a transparent filter response. x c1 + + y z-1 z-1 c2 c3 Figure 15 Direct-Form 1 Standard Filter Structure The DF1 response is defined by the following equations: y[n] c1 x[n] c2 x[n 1] c3 y[n 1] H y c1 c2 z 1 x 1 c3 z 1 The DF1 filters are enabled using the SE1_DF1_L_ENA and SE1_DF1_R_ENA registers bit defined in Table 13. The DF1 filter coefficients are programmed in registers R92 to R98. For the derivation of these registers, refer to the configuration tools supplied with the WM8944B Evaluation Kit. The DF1 filter can be used to implement very complex response patterns, with specific phase and gain responses at different frequencies. Typical applications of this type of filter include the application of refinements or compensations to other user-selected filters. HPF HPF ReTuneTM 5-band EQ Signal Enhancement Block 2 (SE2) The High Pass Filter (HPF) is part of the SE2 block. The HPF cut-off frequency is fixed at 3.7Hz, suitable for removing DC offsets in the record or playback path. The filters are enabled using the SE2_HPF_L_ENA and SE2_HPF_R_ENA register bits defined in Table 14. Rev 4.2 35 WM8944B RETUNE FILTER HPF ReTuneTM 5-band EQ Signal Enhancement Block 2 (SE2) The ReTune™ filter is part of the SE2 block. This is a very advanced feature that is intended to perform frequency linearization according to the particular needs of the application microphone, loudspeaker or housing. The ReTune algorithms can provide acoustic equalisation and selective phase (delay) control of specific frequency bands. The ReTune™ filters are enabled using the SE2_RETUNE_L_ENA and SE2_RETUNE_R_ENA register bits defined in Table 14. The ReTune™ filter coefficients are programmed in registers R101 to R132. For the derivation of the other ReTune configuration parameters, the WISCE™ software must be used to analyse the requirements of the application. (Refer to WISCE™ for further information.) If desired, one or more sets of register coefficients might be derived for different operating scenarios, and these may be recalled and written to the CODEC registers as required in the target application. The ReTune configuration procedure involves the generation and analysis of test signals as outlined below. To determine the characteristics of the microphone in an application, a test signal is applied to a loudspeaker that is in the acoustic path to the microphone. The received signal through the application microphone is analysed and compared with the received signal from a reference microphone in order to determine the characteristics of the application microphone. To determine the characteristics of the loudspeaker in an application, a test signal is applied to the target application. A reference microphone is positioned in the normal acoustic path of the loudspeaker, and the received signal is analysed to determine how accurately the loudspeaker has reproduced the test signal. 5-BAND EQ HPF ReTuneTM 5-band EQ Signal Enhancement Block 2 (SE2) The 5-band EQ is part of the SE2 block. This function allows 5 frequency bands to be controlled. The upper and lower frequency bands are controlled by low-pass and high-pass filters respectively. The middle three frequency bands are notch filters. The cut-off / centre frequency of each filter is programmable, and up to 12dB gain or attenuation can be selected in each case. The 5-band EQ is enabled using the SE2_5BEQ_L_ENA register bit defined in Table 14. The 5-band EQ coefficients are programmed in registers R132 to R175. For the derivation of these registers, refer to the WISCETM software. Typical applications of the 5-band EQ include the selection of user-preferences for different music types, such as ‘rock’, ‘dance’ or ‘classical’ EQ profiles. Note that when the right channel 5BEQ filter is disabled the gains for each of the frequency bands must be set to 0dB. 36 Rev 4.2 WM8944B DYNAMIC RANGE CONTROL (DRC) DRC Signal Enhancement Block 3 (SE3) The Dynamic Range Control (DRC) forms the SE3 block. The DRC provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. The DRC is configured using the control fields in registers R29 to R35 - see “Dynamic Range Control”. SIGNAL ENHANCEMENT REGISTER CONTROLS The SE1 ‘enable’ bits are described in Table 13. Note that other control fields must also be determined and written to the WM8944B using WISCE™ or other tools. The registers described below only allow the sub-blocks of SE1 to be enabled or disabled. Note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers R65 to R95. REGISTER ADDRESS R65 (41h) BIT LABEL DEFAULT DESCRIPTION 1 SE1_LHPF_R_E NA 0 SE1 Right channel low-pass / highpass filter enable SE1_LHPF_C ONFIG 0 = Disabled 1 = Enabled 0 SE1_LHPF_L_E NA 0 SE1 Left channel low-pass / highpass filter enable 0 = Disabled 1 = Enabled R68 (41h) 1 SE1_3D_R_ENA 0 SE1_3D_CON FIG SE1 Right channel 3D stereo enhancement enable 0 = Disabled 1 = Enabled 0 SE1_3D_L_ENA 0 SE1 Left channel 3D stereo enhancement enable 0 = Disabled 1 = Enabled R71 (47h) 1 SE1_NOTCH_ CONFIG SE1_NOTCH_R _ENA 0 SE1 Right channel notch filters enable 0 = Disabled 1 = Enabled 0 SE1_NOTCH_L_ ENA 0 SE1 Left channel notch filters enable 0 = Disabled 1 = Enabled R92 (5Ch) 1 SE1_DF1_CO NFIG SE1_DF1_R_EN A 0 SE1_DF1_L_EN A 0 SE1 Right channel DF1 filter enable 0 = Disabled 1 = Enabled 0 SE1 Left channel DF1 filter enable 0 = Disabled 1 = Enabled Table 13 Signal Enhancement Block 1 (SE1) Rev 4.2 37 WM8944B The SE2 ‘enable’ bits are described in Table 14. Note that (with the exception of the SE2 HPF) other control fields must also be determined and written to the WM8944B using WISCE™ or other tools. The registers described below only allow the sub-blocks of SE2 to be enabled or disabled. Note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers R99 to R175. REGISTER ADDRESS BIT R99 (63h) SE2_HPF_CO NFIG 1 LABEL SE2_HPF_R_E NA DEFAULT 0 DESCRIPTION SE2 Right channel High-pass filter enable 0 = Disabled 1 = Enabled 0 SE2_HPF_L_EN A 0 SE2 Left channel High-pass filter enable 0 = Disabled 1 = Enabled R100 (64h) 1 SE2_RETUNE _CONFIG SE2_RETUNE_ R_ENA 0 SE2 Right channel ReTune filter enable 0 = Disabled 1 = Enabled 0 SE2_RETUNE_ L_ENA 0 SE2 Left channel ReTune filter enable 0 = Disabled 1 = Enabled R133 (85h) SE2_5BEQ_C ONFIG 0 SE2_5BEQ_L_E NA 0 SE2 Left channel 5-band EQ enable 0 = Disabled 1 = Enabled Table 14 Signal Enhancement Block 2 (SE2) The register controls for Signal Enhancement Block SE3 are defined in the “Dynamic Range Control (DRC)” section. 38 Rev 4.2 WM8944B DYNAMIC RANGE CONTROL (DRC) The dynamic range controller (DRC) is a circuit which can be enabled in the digital playback or digital record path of the WM8944B, depending upon the selected DSP mode. The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anticlip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. The DRC also incorporates a Noise Gate function, which provides additional attenuation of very lowlevel input signals. This means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. The DRC is enabled as described in Table 15. The audio signal path controlled by the DRC depends upon the selected DSP Configuration mode - see “DSP Core” for details. If the DRC is used in the record path then to remove any DC offset from the input signal the ADC high pass filter must be enabled. The ADC HPF is enabled when ADC_HPF = 1. This is the default condition. The DRC will not function correctly if there is any DC offset.. REGISTER ADDRESS R29 (1Dh) BIT 7 LABEL DEFAULT DRC_ENA DESCRIPTION DRC Enable 0 DRC Control 1 0 = Disabled 1 = Enabled Table 15 DRC Enable DRC COMPRESSION / EXPANSION / LIMITING The DRC supports two different compression regions, separated by a “Knee” at a specific input amplitude. In the region above the knee, the compression slope DRC_HI_COMP applies; in the region below the knee, the compression slope DRC_LO_COMP applies. The DRC also supports a noise gate region, where low-level input signals are heavily attenuated. This function can be enabled or disabled according to the application requirements. The DRC response in this region is defined by the expansion slope DRC_NG_EXP. For additional attenuation of signals in the noise gate region, an additional “knee” can be defined (shown as “Knee2” in Figure 16). When this knee is enabled, this introduces an infinitely steep dropoff in the DRC response pattern between the DRC_LO_COMP and DRC_NG_EXP regions. The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is nearconstant) is illustrated in Figure 16. DRC Output Amplitude (dB) (Y0) Knee1 DRC_KNEE_OP DRC DR L C_ C _HI_ OMP MP CO O_ Knee2 DR C_ NG _E XP DRC_KNEE2_OP DRC_KNEE2_IP DRC_KNEE_IP 0dB DRC Input Amplitude (dB) Rev 4.2 39 WM8944B Figure 16 DRC Response Characteristic The slope of the DRC response is determined by register fields DRC_HI_COMP and DRC_LO_COMP. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. When the noise gate is enabled, the DRC response in this region is determined by the DRC_NG_EXP register. A slope of 1 indicates constant gain in this region. A slope greater than 1 represents expansion (ie. a change in input amplitude produces a larger change in output amplitude). When the DRC_KNEE2_OP knee is enabled (“Knee2” in Figure 16), this introduces the vertical line in the response pattern illustrated, resulting in infinitely steep attenuation at this point in the response. The DRC parameters are listed in Table 16. REF PARAMETER DESCRIPTION 1 DRC_KNEE_IP Input level at Knee1 (dB) 2 DRC_KNEE_OP Output level at Knee1 (dB) 3 DRC_HI_COMP Compression ratio above Knee1 4 DRC_LO_COMP Compression ratio below Knee1 5 DRC_KNEE2_IP Input level at Knee2 (dB) 6 DRC_NG_EXP Expansion ratio below Knee2 7 DRC_KNEE2_OP Output level at Knee2 (dB) Table 16 DRC Response Parameters The noise gate is enabled when the DRC_NG_ENA register is set. When the noise gate is not enabled, parameters 5, 6, 7 above are ignored, and the DRC_LO_COMP slope applies to all input signal levels below Knee1. The DRC_KNEE2_OP knee is enabled when the DRC_KNEE2_OP_ENA register is set. When this bit is not set, then parameter 7 above is ignored, and the Knee2 position always coincides with the low end of the DRC_LO_COMP region. The “Knee1” point in Figure 16 is determined by register fields DRC_KNEE_IP and DRC_KNEE_OP. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation: Y0 = DRC_KNEE_OP – (DRC_KNEE_IP * DRC_HI_COMP) The DRC Compression / Expansion / Limiting parameters are defined in Table 17. REGISTER ADDRESS R29 (1Dh) DRC Control 1 BIT LABEL DEFAULT 8 DRC_NG_ENA 0 DESCRIPTION DRC Noise Gate Enable 0 = Disabled 1 = Enabled 40 Rev 4.2 WM8944B REGISTER ADDRESS R32 (20h) BIT LABEL DEFAULT DESCRIPTION 12:8 DRC_KNEE2_IP 000000 Input signal level at the Noise Gate threshold ‘Knee2’. DRC Control 4 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB See Table 18 for details Only applicable when DRC_NG_ENA = 1. 7:2 DRC_KNEE_IP 000000 Input signal level at the Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved See Table 18 for details R33 (21h) 13 DRC Control 5 DRC_KNEE2_OP _ENA 0 DRC_KNEE2_OP 00000 DRC_KNEE2_OP Enable 0 = Disabled 1 = Enabled 12:8 Output signal at the Noise Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB See Table 18 for details Only applicable when DRC_KNEE2_OP_ENA = 1. 7:3 DRC_KNEE_OP 00000 Output signal at the Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved See Table 18 for details 2:0 DRC_HI_COMP 011 Compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved Rev 4.2 41 WM8944B REGISTER ADDRESS BIT LABEL DEFAULT 9:8 DRC_NG_EXP 00 DESCRIPTION 111 = Reserved R35 (23h) DRC Control 7 Noise Gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 7:5 DRC_LO_COMP 000 Compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved Table 17 DRC Control Registers KNEE INPUT LEVEL (DRC_KNEE_IP) R32[7:2] 42 KNEE OUTPUT LEVEL (DRC_KNEE_OP) LEVEL R32[7:2] LEVEL R33[7:3] 00h 0.00 20h -24.00 01h -0.75 21h -24.75 02h -1.50 22h 03h -2.25 04h KNEE2 INPUT LEVEL (DRC_KNEE2_IP) KNEE2 OUTPUT LEVEL (DRC_KNEE2_OP) LEVEL R32[12:8] LEVEL R33[12:8] LEVEL 00h 0.00 00h -36.00 00h -30.00 01h -0.75 01h -37.50 01h -31.50 -25.50 02h -1.50 02h -39.00 02h -33.00 23h -26.25 03h -2.25 03h -40.50 03h -34.50 -3.00 24h -27.00 04h -3.00 04h -42.00 04h -36.00 05h -3.75 25h -27.75 05h -3.75 05h -43.50 05h -37.50 06h -4.50 26h -28.50 06h -4.50 06h -45.00 06h -39.00 07h -5.25 27h -29.25 07h -5.25 07h -46.50 07h -40.50 08h -6.00 28h -30.00 08h -6.00 08h -48.00 08h -42.00 09h -6.75 29h -30.75 09h -6.75 09h -49.50 09h -43.50 0Ah -7.50 2Ah -31.50 0Ah -7.50 0Ah -51.00 0Ah -45.00 0Bh -8.25 2Bh -32.25 0Bh -8.25 0Bh -52.50 0Bh -46.50 0Ch -9.00 2Ch -33.00 0Ch -9.00 0Ch -54.00 0Ch -48.00 0Dh -9.75 2Dh -33.75 0Dh -9.75 0Dh -55.50 0Dh -49.50 0Eh -10.50 2Eh -34.50 0Eh -10.50 0Eh -57.00 0Eh -51.00 0Fh -11.25 2Fh -35.25 0Fh -11.25 0Fh -58.50 0Fh -52.50 10h -12.00 30h -36.00 10h -12.00 10h -60.00 10h -54.00 11h -12.75 31h -36.75 11h -12.75 11h -61.50 11h -55.50 12h -13.50 32h -37.50 12h -13.50 12h -63.00 12h -57.00 13h -14.25 33h -38.25 13h -14.25 13h -64.50 13h -58.50 14h -15.00 34h -39.00 14h -15.00 14h -66.00 14h -60.00 15h -15.75 35h -39.75 15h -15.75 15h -67.50 15h -61.50 16h -16.50 36h -40.50 16h -16.50 16h -69.00 16h -63.00 17h -17.25 37h -41.25 17h -17.25 17h -70.50 17h -64.50 18h -18.00 38h -42.00 18h -18.00 18h -72.00 18h -66.00 19h -18.75 39h -42.75 19h -18.75 19h -73.50 19h -67.50 1Ah -19.50 3Ah -43.50 1Ah -19.50 1Ah -75.00 1Ah -69.00 1Bh -20.25 3Bh -44.25 1Bh -20.25 1Bh -76.50 1Bh -70.50 1Ch -21.00 3Ch -45.00 1Ch -21.00 1Ch -78.00 1Ch -72.00 1Dh -21.75 3Dh Reserved 1Dh -21.75 1Dh -79.50 1Dh -73.50 1Eh -22.50 3Eh Reserved 1Eh -22.50 1Eh -81.00 1Eh -75.00 1Fh -23.25 3Fh Reserved 1Fh Reserved 1Fh -82.50 1Fh -76.50 Rev 4.2 WM8944B Table 18 DRC Digital Gain Range GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN, DRC_MAXGAIN and DRC_NG_MINGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 16. If the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. The minimum gain in the Compression regions of the DRC response is set by DRC_MINGAIN. The mimimum gain in the Noise Gate region is set by DRC_NG_MINGAIN. The minimum gain limit prevents excessive attenuation of the signal path. The maximum gain limit set by DRC_MAXGAIN prevents quiet signals (or silence) from being excessively amplified. REGISTER ADDRESS R30 (1Eh) BIT LABEL DEFAULT 12:9 DRC_NG_MING AIN [3:0] 0110 DRC Control 2 DESCRIPTION Minimum gain the DRC can use to attenuate audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 = 36dB 1101 to 1111 = Reserved 4:2 DRC_MINGAIN [2:0] 001 Minimum gain the DRC can use to attenuate audio signals 000 = 0dB 001 = -12dB (default) 010 = -18dB 011 = -24dB 100 = -36dB 101 = Reserved 11X = Reserved 1:0 DRC_MAXGAIN [1:0] 01 Maximum gain the DRC can use to boost audio signals (dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 36dB Table 19 DRC Gain Limits Rev 4.2 43 WM8944B GAIN READBACK The gain applied by the DRC can be read from the DRC_GAIN register. This is a 16-bit, fixed-point value, which expresses the DRC gain as a voltage multiplier. DRC_GAIN is coded as a fixed-point quantity, with an MSB weighting of 64. The first 7 bits represent the integer portion; the remaining bits represent the fractional portion. If desired, the value of this field may be interpreted by treating DRC_GAIN as an integer value, and dividing the result by 512, as illustrated in the following examples: DRC_GAIN = 05D4 (hex) = 1380 (decimal) Divide by 512 gives 2.914 voltage gain, or 4.645dB DRC_GAIN = 0100 (hex) = 256 (decimal) Divide by 512 gives 0.5 voltage gain, or -3.01dB The DRC_GAIN register is defined in Table 20. REGISTER ADDRESS R36 (24h) DRC Status BIT 15:0 LABEL DRC_GAIN [15:0] (Read only) DEFAULT DESCRIPTION DRC Gain value (Read only). This is the DRC gain, expressed as a voltage multiplier. Fixed point coding, MSB = 64. The first 7 bits are the integer portion; the remaining bits are the fractional part. Table 20 DRC Gain Readback DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the peak signal amplitude over a period of time. The DRC_ATK determines how quickly the DRC gain decreases when the signal amplitude is high. The DRC_DCY determines how quickly the DRC gain increases when the signal amplitude is low. These register fields are described in Table 21. Note that the register defaults are suitable for general purpose microphone use. 44 Rev 4.2 WM8944B REGISTER ADDRESS R31 (1Fh) BIT 7:4 LABEL DRC_ATK [3:0] DEFAULT 0100 DRC Control 3 DESCRIPTION Attack rate relative to the input signal (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100-1111 = Reserved 3:0 DRC_DCY [3:0] 0010 Decay rate relative to the input signal (seconds/6dB) 0000 = 186ms 0001 = 372ms 0010 = 743ms 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = Reserved Table 21 DRC Time Constants Under the following conditions, it is possible to predict the attack times with an input sine wave: Decay rate is set at least 8 times the attack rate. Attack time * input frequency > 1 To estimate the attack time for 10%-90%: Attack Time = Register Value * 2.24 For example, if DRC_ATK = 1.45ms/6dB, then the attack time (10%-90%) = 1.45ms * 2.24 = 3.25ms. The decay time for 10%-90% can be estimated using the graph in Figure 17. Rev 4.2 45 WM8944B Figure 17 Decay Time vs Register Value Decay Rate The decay rate register value read from the horizontal axis and the decay time (10%-90%) read from the vertical axis. For example, if DRC DRC_DCY = 743ms/6dB, then the estimate decay time (10%-90%) taken from the graph is 1.0s. ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the DRC_ANTICLIP bit. Note that the feed-forward processing increases the latency in the input signal path. The DRC AntiClip control is described in Table 22. REGISTER ADDRESS R29 (1Dh) BIT LABEL DEFAULT 1 DRC_ANTICLIP 1 DRC Control 1 DESCRIPTION DRC Anti-clip Enable 0 = Disabled 1 = Enabled Table 22 DRC Anti-Clip Control Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. Note that the Anti-Clip and Quick Release features should not be used at the same time. 46 Rev 4.2 WM8944B QUICK-RELEASE CONTROL The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. The Quick Release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of DRC_DCY. The Quick-Release feature is enabled by setting the DRC_QR bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by DRC_QR_THR, then the normal decay rate (DRC_DCY) is ignored and a faster decay rate (DRC_QR_DCY) is used instead. The DRC Quick-Release control bits are described in Table 23. REGISTER ADDRESS R29 (1Dh) BIT 2 LABEL DRC_QR DEFAULT 1 DRC Control 1 DESCRIPTION DRC Quick-release Enable 0 = Disabled 1 = Enabled R34 (22h) 3:2 DRC Control 6 DRC_QR_THR [1:0] 00 DRC Quick-release threshold (crest factor in dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB 1:0 DRC_QR_DCY [1:0] 00 DRC Quick-release decay rate (seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved Table 23 DRC Quick-Release Control Note that the Anti-Clip and Quick Release features should not be used at the same time. DRC INITIAL CONDITION The DRC can be set up to a defined initial condition based on the expected signal level when the DRC is enabled. This can be set using the DRC_INIT bits in register R35 (23h) bits 4 to 0. Note: This does NOT set the initial gain of the DRC. It sets the expected signal level of the DRC input signal when the DRC is enabled. REGISTER ADDRESS R35 (23h) BIT 4:0 LABEL DRC_INIT DRC Control 7 DEFAULT 00000 DESCRIPTION Initial value at DRC startup 00000 = 0dB 00001 = -3.75dB … (-3.75dB steps) 11111 = -116.25dB Table 24 DRC Initial Condition Rev 4.2 47 WM8944B DIGITAL-TO-ANALOGUE CONVERTER (DAC) The WM8944B DAC receives digital input data from the digital audio interface. (Note that, depending on the DSP Configuration mode, the digital input may first be processed and filtered in the DSP Core.) The digital audio data is converted to an oversampled bit-stream in the on-chip, true 24-bit digital interpolation filter. The bit-stream data enters the multi-bit, sigma-delta DAC, which converts it to high quality analogue audio. The analogue output from the DAC can then be mixed with other analogue inputs before being sent to the analogue output pins (see “Output Signal Path”). The DAC is enabled by the DAC_ENA register bit. REGISTER ADDRESS R3 (03h) BIT 0 LABEL DAC_ENA DEFAULT 0 Power Management 2 DESCRIPTION DAC Enable 0 = Disabled 1 = Enabled DAC_ENA must be set to 1 when processing data from the DAC or Digital Beep Generator. Table 25 DAC Enable Control DAC DIGITAL VOLUME CONTROL The output of the DAC can be digitally amplified or attenuated over a range from -71.625dB to +23.625dB in 0.375dB steps. The volume can be controlled using DAC_VOL. The DAC Volume is part of the DAC Digital Filters block. The gain for a given eight-bit code X is given by: 0.375 (X-192) dB for 1 X 255; MUTE for X = 0 The output of the DAC can be digitally muted using the DAC_MUTE bit. A digital soft-mute feature is provided in order to avoid sudden glitches in the analogue signal. When DAC_VOL_RAMP is enabled, then all mute, un-mute or volume change commands are implemented as a gradual volume change in the digital domain. The rate at which the volume ramps up is half of the sample freq (fs/2). The DAC_VOL_RAMP register field is described in Table 26. REGISTER ADDRESS R22 (16h) BIT LABEL DEFAULT 4 DAC_VOL_RAMP 1 DAC Control 2 DESCRIPTION DAC Volume Ramp control 0 = Disabled 1 = Enabled R23 (17h) 8 DAC_MUTE 1 DAC Digital Vol DAC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 DAC_VOL [7:0] 1100_0000 DAC Digital Volume (0dB) 0000_0000 = mute 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB (See Table 27 for volume range) Table 26 DAC Digital Volume Control 48 Rev 4.2 WM8944B DAC_VOL Volume (dB) DAC_VOL Volume (dB) DAC_VOL Volume (dB) DAC_VOL Volume (dB) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 18.000 18.375 18.750 19.125 19.500 19.875 20.250 20.625 21.000 21.375 21.750 22.125 22.500 22.875 23.250 23.625 Table 27 DAC Digital Volume Range Rev 4.2 49 WM8944B DAC AUTO-MUTE The DAC digital mute and volume controls are described earlier in Table 26. The DAC also incorporates an analogue auto-mute, which is enabled by setting DAC_AUTOMUTE. When the auto-mute is enabled, and a series of 1024 consecutive zero-samples is detected, the DAC output is muted in order to attenuate noise that might be present in output signal path. The DAC resumes normal operation as soon as digital audio data is detected. REGISTER ADDRESS R21 (15h) BIT 4 DAC Control 1 LABEL DAC_AUTOMUT E DEFAULT 1 DESCRIPTION DAC Auto-Mute Control 0 = Disabled 1 = Enabled Table 28 DAC Auto Mute Note: The DAC_AUTOMUTE bit should not be set when the BEEP generator is used. DAC SLOPING STOPBAND FILTER Two DAC filter types are available, selected by the register bit DAC_SB_FLT. When operating at lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (DAC_SB_FLT=1) to reduce out-of-band noise which can be audible at low DAC sample rates. See “Digital Filter Characteristics” for details of DAC filter characteristics. REGISTER ADDRESS R22 (16h) BIT 0 LABEL DAC_SB_FLT DAC Control 2 DEFAULT 0 DESCRIPTION Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode Table 29 DAC Sloping Stopband Filter 50 Rev 4.2 WM8944B DIGITAL BEEP GENERATOR The WM8944B provides a digital signal generator which can be used to inject an audio tone (beep) into the DAC signal path. The output of the beep generator is digitally mixed with the DAC outputs, after the DAC digital volume. The beep is enabled using BEEP_ENA. The beep function creates an approximation of a Sine wave. The audio frequency is set using BEEP_RATE. The beep volume is set using BEEP_GAIN. Note that the volume of the digital beep generator is not affected by the DAC volume or DAC mute controls but the DAC_ENA bit must be set. The DAC_AUTOMUTE bit should not be set when the BEEP generator is used. The digital beep generator control fields are described in Table 30. REGISTER ADDRESS R37 (25h) BIT LABEL DEFAULT 6:3 BEEP_GAIN [3:0] 0000 Beep Control 1 DESCRIPTION Digital Beep Volume Control 0000 = mute 0001 = -83dB 0010 = -77dB … (6dB steps) 2:1 0 BEEP_RATE [1:0] BEEP_ENA 01 1111 = +1dB Beep Waveform Control 0 00 = Reserved 01 = 1kHz 10 = 2kHz 11 = 4kHz Digital Beep Enable 0 = Disabled 1 = Enabled Note that the DAC and associated signal path needs to be enabled when using the digital beep. Table 30 Digital Beep Generator OUTPUT SIGNAL PATH The WM8944B provides a Line Output mixer and a Speaker Output mixer. Multiple inputs to each mixer provide a high degree of flexibility to route different signal paths to each of the analogue outputs. The DAC output can be routed to the mixers either directly or in inverted phase. This provides additional capability to generate differential (BTL) output signals. The analogue inputs AUX and IN1 can be configured as a differential signal path to the mixers, bypassing the Input PGA. This configuration can be used to minimise power consumption. The analogue inputs AUX and IN1 can be routed directly to the Speaker outputs, bypassing the Speaker PGA and mixers. This can be used to provide a fixed-gain signal path for a “PC Beep” or similar application. The output signal paths and associated control registers are illustrated in Figure 18. Note that the speaker outputs are intended to drive a mono headset or speaker (in BTL configuration). They are not designed to drive stereo speakers. Rev 4.2 51 52 Digital Beep Generator -1 + - AUXDIFF_TO_PGA BYP_TO_PGA AUX_TO_PGA IN1_TO_PGA DAC DAC_VOL[7:0] DAC_TO_PGA MDAC_TO_PGA DAC_ENA BEEP_GAIN[3:0] BEEP_RATE[1:0] BEEP_ENA DAC Digital Filters DAC_SB_FLT BYPASS IN1 AUX + - AUXDIFF_TO_OUT DAC_TO_OUT MDAC_TO_OUT AUX_TO_OUT IN1_TO_OUT BYP_TO_OUT + MIXSPK + MIXOUT PGA_TO_SPKP AUX_TO_SPKP -1 PGA_TO_SPKN IN1_TO_SPKN SPKPGA SPK_PGA_ENA SPK_VOL SPK_MIX_ENA SPK_MIX_MUTE OUT_ENA LINE_MUTE SPKOUTN + SPKN_SPKVDD_ENA SPKN_OP_ENA SPKN_OP_MUTE SPKOUTP + SPKP_SPKVDD_ENA SPKP_OP_ENA SPKP_OP_MUTE WM8944B SPKOUTN SPKOUTP LINEOUT WM8944B Figure 18 Output Signal Paths Rev 4.2 WM8944B OUTPUT SIGNAL PATHS ENABLE Each analogue output pin can be independently enabled or disabled using the register bits described in Table 31. The speaker PGA and mixers can also be controlled. REGISTER ADDRESS R3 (03h) Power management 2 BIT 14 LABEL OUT_ENA DEFAULT 0 DESCRIPTION LINEOUT enable 0 = Disabled 1 = Enabled 12 SPK_PGA_ENA 0 Speaker PGA enable 0 = Disabled 1 = Enabled 11 SPKN_SPKVDD_ ENA 0 SPKOUTN enable 0 = Disabled 1 = Enabled Note that SPKOUTN is also controlled by SPKN_OP_ENA. When powering down SPKOUTN, the SPKN_SPKVDD_ENA bit should be reset first. 10 SPKP_SPKVDD_ ENA 0 SPKOUTP enable 0 = Disabled 1 = Enabled Note that SPKOUTP is also controlled by SPKP_OP_ENA. When powering down SPKOUTP, the SPKP_SPKVDD_ENA bit should be reset first 7 SPKN_OP_ENA 0 SPKOUTN enable 0 = Disabled 1 = Enabled Note that SPKOUTN is also controlled by SPKN_SPKVDD_ENA. When powering up SPKOUTN, the SPKN_OP_ENA bit should be enabled first. 6 SPKP_OP_ENA 0 SPKOUTP enable 0 = Disabled 1 = Enabled Note that SPKOUTP is also controlled by SPKP_SPKVDD_ENA. When powering up SPKOUTP, the SPKP_OP_ENA bit should be enabled first 2 SPK_MIX_ENA 0 Speaker output mixer enable 0 = Disabled 1 = Enabled Table 31 Output Signal Paths Enable To enable the output PGA and mixers, the reference voltage VMID and the bias current must also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls VMID_SEL and BIAS_ENA. Note that the Line output, Speaker outputs, Speaker PGA mixer and Speaker PGA are all muted by default. The required signal paths must be un-muted using the control bits described in the respective tables below. Rev 4.2 53 WM8944B LINE OUTPUT MIXER CONTROL The Line Output mixer (OUTMIX) controls are described in Table 32. These allow any of the DAC, Inverted DAC, IN1, AUX and ADC Bypass signals to be mixed. A differential AUX/IN1 signal can also be selected in the Line Output mixer. The output of the mixer can be muted using the LINE_MUTE bit. Note that, when selecting the differential AUX/IN1 signal as an input to the Line Output mixer, the IN1 pin provides the non-inverting path and the AUX pin provides the inverting signal path. Care should be taken when mixing more than one path to the Line Output mixer in order to avoid clipping. The gain of each input path is adjustable using a selectable -6dB control in each path to facilitate this. Note that the attenuation control field DAC_TO_OUT_ATTEN controls the DAC and the Inverted DAC mixer paths to the Line Output mixer. Note that the DAC input level may also be controlled by the DAC digital volume control - see “Digital to Analogue Converter (DAC)” for further details. REGISTER ADDRESS R42 (2Ah) BIT 8 LABEL LINE_MUTE DEFAULT 1 Output ctrl DESCRIPTION LINEOUT Output Mute 0 = Disable Mute 1 = Enable Mute R49 (31h) 10 Line mixer control 1 AUXDIFF_TO_O UT 0 Differential AUX/IN1 to Line Output Mixer select 0 = Disabled 1 = Enabled 9 IN1_TO_OUT 0 IN1 to Line Output Mixer select 0 = Disabled 1 = Enabled 6 BYP_TO_OUT 0 Input PGA (ADC bypass) to Line Output Mixer select 0 = Disabled 1 = Enabled 5 MDAC_TO_OUT 0 Inverted DAC to Line Output Mixer select 0 = Disabled 1 = Enabled 3 DAC_TO_OUT 0 DAC to Line Output Mixer select 0 = Disabled 1 = Enabled 0 AUX_TO_OUT 0 AUX to Line Output Mixer select 0 = Disabled 1 = Enabled R51 (33h) 10 Line mixer control 2 AUXDIFF_TO_O UT_ATTEN 0 Differential AUX/IN1 to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 9 IN1_TO_OUT_AT TEN 0 BYP_TO_OUT_A TTEN 0 IN1 to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 6 Input PGA (ADC bypass) to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 3 DAC_TO_OUT_A TTEN 0 DAC to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 54 Rev 4.2 WM8944B REGISTER ADDRESS BIT LABEL DEFAULT 0 AUX_TO_OUT_A TTEN 0 DESCRIPTION AUX to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation Table 32 Line Output Mixer (MIXOUT) Control SPEAKER PGA MIXER CONTROL The Speaker PGA mixer (MIXSPK) controls are described in Table 33. These allow any of the DAC, Inverted DAC, IN1, AUX and ADC Bypass signals to be mixed. A differential AUX/IN1 signal can also be selected in the Speaker PGA mixer. The output of the Speaker PGA mixer can be muted using the SPK_MIX_MUTE bit. Note that, when selecting the differential AUX/IN1 signal as an input to the Speaker PGA mixer, the IN1 pin provides the non-inverting path and the AUX pin provides the inverting signal path. Note that the output from the Speaker PGA mixer is also controlled by the Speaker PGA Volume control and the Speaker Output control described in the following sections. Care should be taken when enabling more than one path to the Speaker PGA mixer in order to avoid clipping. The gain of each input path is adjustable using a selectable -6dB control in each path to facilitate this. Note that the attenuation control field DAC_TO_PGA_ATTEN controls the DAC and the Inverted DAC mixer paths to the Speaker PGA mixer. Note that the DAC input level may also be controlled by the DAC digital volume control - see “Digital to Analogue Converter (DAC)” for further details. REGISTER ADDRESS R3 (03h) BIT LABEL DEFAULT 4 SPK_MIX_MUTE 1 Power Management 1 R43 (2Bh) DESCRIPTION Speaker PGA Mixer Mute 0 = Disable Mute 1 = Enable Mute 10 SPK mixer control 1 AUXDIFF_TO_PG A 0 Differential AUX/IN1 to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 9 IN1_TO_PGA 0 IN1 to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 6 BYP_TO_PGA 0 Input PGA (ADC bypass) to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 5 MDAC_TO_PGA 0 Inverted DAC to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 3 DAC_TO_PGA 0 DAC to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 0 AUX_TO_PGA 0 AUX to Speaker PGA Mixer select 0 = Disabled 1 = Enabled R45 (2Dh) SPK mixer control 3 10 AUXDIFF_TO_PG A_ATTEN 0 Differential AUX/IN1 to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation Rev 4.2 55 WM8944B REGISTER ADDRESS BIT LABEL DEFAULT 9 IN1_TO_PGA_AT TEN 0 DESCRIPTION IN1 to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation 6 BYP_TO_PGA_A TTEN 0 Input PGA (ADC bypass) to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation 3 DAC_TO_PGA_A TTEN 0 DAC to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation 0 AUX_TO_PGA_A TTEN 0 AUX to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation Table 33 Speaker PGA Mixer (MIXSPK) Control SPEAKER PGA VOLUME CONTROL The volume control of the Speaker PGA can be adjusted using the SPK_VOL register field as described in Table 34. The gain range is -57dB to +6dB in 1dB steps. Note that the output from the Speaker PGA Volume control is an input to the Speaker Output control described in the following section. To prevent "zipper noise", a zero-cross function is provided on the Speaker PGA. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. Note that any dc offset in the DAC data should be less than the peak data to ensure there are zerocrossings. The Speaker PGA volume control register fields are described in Table 34. REGISTER ADDRESS R47 (2Fh) BIT 7 LABEL SPK_ZC DEFAULT 0 SPK volume ctrl DESCRIPTION Speaker PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 6 SPK_PGA_MUTE 1 Speaker PGA Mute 0 = Disable Mute 1 = Enable Mute 5:0 SPK_VOL [5:0] 11_1001 Speaker PGA Volume (0dB) 00_0000 = -57dB gain 00_0001 = -56dB … 11_1001 = 0dB ... 11_1111 = +6dB (See Table 35 for volume range) Table 34 Speaker PGA Volume Control 56 Rev 4.2 WM8944B PGA GAIN SETTING VOLUME (dB) PGA GAIN SETTING VOLUME (dB) 00h -57 20h -25 01h -56 21h -24 02h -55 22h -23 03h -54 23h -22 04h -53 24h -21 05h -52 25h -20 06h -51 26h -19 07h -50 27h -18 08h -49 28h -17 09h -48 29h -16 0Ah -47 2Ah -15 0Bh -46 2Bh -14 0Ch -45 2Ch -13 0Dh -44 2Dh -12 0Eh -43 2Eh -11 0Fh -42 2Fh -10 10h -41 30h -9 11h -40 31h -8 12h -39 32h -7 13h -38 33h -6 14h -37 34h -5 15h -36 35h -4 16h -35 36h -3 17h -34 37h -2 18h -33 38h -1 19h -32 39h 0 1Ah -31 3Ah +1 1Bh -30 3Bh +2 1Ch -29 3Ch +3 1Dh -28 3Dh +4 1Eh -27 3Eh +5 1Fh -26 3Fh +6 Table 35 Speaker PGA Volume Range Rev 4.2 57 WM8944B SPEAKER OUTPUT CONTROL Each Speaker output has its own output mixer. This allows the output of the Speaker PGA to be enabled or disabled, and also allows the AUX and IN1 inputs to be routed directly to the Speaker outputs. (AUX can be routed to SPKOUTP; IN1 can be routed to SPKOUTN, as illustrated in Figure 18. The two Speaker outputs can be muted also, using SPKN_OP_MUTE and SPKP_OP_MUTE. As described above, the analogue inputs AUX and IN1 can be routed directly to the Speaker outputs, bypassing the Speaker PGA and mixers. This can be used to provide a fixed-gain signal path that is unaffected by the Speaker PGA setting. This feature is intended for a “PC Beep” or similar applications. Care should be taken when enabling more than one path to the Speaker Output mixers in order to avoid clipping. The gain of each input path is adjustable using a selectable -6dB control in each path to facilitate this. The Speaker Output control registers are described in Table 36. REGISTER ADDRESS R3 (03h) Power Management 1 BIT LABEL DEFAULT 9 SPKN_OP_MUTE 1 DESCRIPTION SPKOUTN Output Mute 0 = Disable Mute 1 = Enable Mute 8 SPKP_OP_MUTE 1 SPKOUTP Output Mute 0 = Disable Mute 1 = Enable Mute R43 (2Bh) 8 AUX_TO_SPKP 0 SPK mixer control 1 AUX to SPKOUTP select 0 = Disabled 1 = Enabled 7 PGA_TO_SPKP 0 Speaker PGA Mixer to SPKOUTP select 0 = Disabled 1 = Enabled R44 (2Ch) SPK mixer control2 9 IN1_TO_SPKN 0 IN1 to SPKOUTN select 0 = Disabled 1 = Enabled 7 PGA_TO_SPKN 0 Speaker PGA Mixer to SPKOUTN select 0 = Disabled 1 = Enabled R45 (2Dh) SPK mixer control3 8 AUX_TO_SPKP_ ATTEN 0 PGA_TO_SPKP_ ATTEN 0 AUX to SPKOUTP attenuation 0 = 0dB 1 = -6dB attenuation 7 Speaker PGA Mixer to SPKOUTP attenuation 0 = 0dB 1 = -6dB attenuation R46 (2Eh) SPK mixer control4 9 IN1_TO_SPKN_ 0 ATTEN IN1 to SPKOUTN attenuation 0 = 0dB 1 = -6dB attenuation 7 PGA_TO_SPKN_ ATTEN 0 Speaker PGA Mixer to SPKOUTN attenuation 0 = 0dB 1 = -6dB attenuation Table 36 Speaker Output Control 58 Rev 4.2 WM8944B ANALOGUE OUTPUTS The Line output and Speaker output pins are highly configurable and may be used in many different ways. The output mixers can be configured to generate single-ended or differential outputs. The Class AB Speaker output driver can deliver up to 400mW into an 8 speaker in BTL mode. LINE OUTPUT The line output LINEOUT is the external connection to the MIXOUT mixer. This is a single-ended output driver. Note that single-ended line output can also be provided on SPKOUTP and SPKOUTN. SPEAKER OUTPUTS The speaker outputs SPKOUTP and SPKOUTN are the external connections to the Speaker Output mixers. These outputs are intended for a mono speaker or headphone in BTL configuration or for a twin mono line load. In a typical application, a BTL output from the DAC may be generated at the speaker outputs by routing the Speaker PGA to the SPKOUTP and SPKOUTN pins. The analogue inputs AUX and IN1 may also be routed to the SPKOUTP and SPKOUTN outputs by enabling the respective signal path in each of the speaker output mixers. EXTERNAL COMPONENTS FOR LINE OUTPUT In single-ended output configurations, DC blocking capacitors are required at the output pins (LINEOUT, SPKOUTP and SPKOUTN). See “Applications Information” for details of these components. Rev 4.2 59 WM8944B LDO REGULATOR The WM8944B provides an internal LDO which provides a regulated voltage for use as an internal supply and reference, which can also be used to power external circuits. The LDO is enabled by setting the LDO_ENA register bit. The LDO supply is drawn from the LDOVDD pin; the LDO output is provided on the LDOVOUT pin. The LDO requires a reference voltage and a bias source; these are configured as described below. The LDO bias source (master bias or start-up bias) is selected using BIAS_SRC. Care is required during start-up to ensure that the selected bias is enabled; the master bias will not normally be available at initial start-up, and the start-up bias should be selected in the first instance. The LDO reference voltage can be selected using LDO_REF_SEL; this allows selection of either the internal bandgap reference or one of the VMID resistor strings. When VMID is selected as the reference, then LDO_REF_SEL_FAST selects either the Normal VMID reference or the Fast-Start VMID reference. Care is required during start-up to ensure that the selected reference is enabled; the VMID references are enabled using VMID_ENA and VMID_FAST_START as described in Table 40 and Table 41 respectively.The internal bandgap reference is nominally 1.5V. Note that this value is not trimmed and may vary significantly (+/-10%) between different devices. When using this reference, the internal bandgap reference must be enabled by setting the BG_ENA register, as described in Table 37. The bandgap voltage can be adjusted using the BG_VSEL register as described in Table 39. The LDO output voltage is set using the LDO_VSEL register, which sets the ratio of the output voltage to the LDO reference voltage. See Table 38 for LDO output voltages. Example1: How to generate an LDOVOUT voltage of 3.0V from a 3.3V LDOVDD supply voltage. If VMID is selected as the reference voltage for the LDO (LDO_REF_SEL = 0) then the VMID voltage must be supplied from LDOVDD (VMID_REF_SEL = 0) and the VMID ratio set to 5/11 (VMID_CTRL = 0). This gives VMID = 1.5V. The default LDO_VSEL gives LDOVOUT = Vref * 1.97 = 1.5V * 1.97 = 2.96V (see Table 38). Example2: Generating an LDOVOUT voltage of 2.4V from a 3.0V LDOVDD supply. For maximum signal swing the VMID voltage should be half of the LDOVOUT voltage. For LDOVOUT of 2.4V the optimum VMID voltage is 1.2V. Select the VMID source voltage as LDOVOUT (VMID_REF_SEL = 1) and the VMID ratio as 1/2 (VMID_CTRL = 1). This gives VMID = 1.2V. VMID cannot be used as the LDO reference voltage so use the Bandgap voltage as the LDO reference voltage (LDO_REF_SEL = 1, BG_ENA = 1). The default Bandgap voltage is 1.467V. For LDOVOUT of 2.4V LDOVSEL should be set to 2.4V / 1.467V = 1.636. Referring to Table 38 LDO_VSEL = 03h will give LDOVOUT = 1.467 * 1.66 = 2.435V. Note that the Bnadgap voltage is not trimmed so if required the Bandgap voltage can be changed (BG_VSEL – see Table 39) to get closer to the required voltage. By default, the LDO output is actively discharged to GND through internal resistors when the LDO is disabled. This is desirable in shut-down to prevent any external connections being affected by the internal circuits. The LDO output can be set to float when the LDO is disabled; this is selected by setting the LDO_OP_FLT bit. This option should be selected if the LDO is bypassed and an external voltage is applied to LDOVOUT. The LDO output is monitored for voltage accuracy. The LDO undervoltage status can be read at any time from the LDO_UV_STS bit, as described in Table 37. This bit can be polled at any time, or may output directly on a GPIO pin, or may be used to generate Interrupt events. 60 Rev 4.2 WM8944B REGISTER ADDRESS R7 (07h) BIT 7 LABEL BIAS_SRC DEFAULT 0 Additional control R17 (11h) DESCRIPTION Bias Source select 0 = Master bias 1 = Start-Up bias 0 LDO_UV_STS 0 Status Flags LDO Undervoltage status (Read only) 0 = Normal 1 = Undervoltage R53 (35h) 15 LDO_ENA 0 LDO LDO Enable 0 = Disabled 1 = Enabled 14 LDO_REF_SEL_F AST 0 LDO Voltage reference select 0 = VMID (normal) 1 = VMID (fast start) This field is only effective when LDO_REF_SEL = 0 13 LDO_REF_SEL 0 LDO Voltage reference select 0 = VMID 1 = Bandgap 12 LDO_OPFLT 0 LDO Output float 0 = Disabled (Output discharged when disabled) 1 = Enabled (Output floats when disabled) 4:0 LDO_VSEL [4:0] 00111 LDO Voltage select (Sets the LDO output as a ratio of the selected voltage reference. The voltage reference is set by LDO_REF_SEL.) 00111 = Vref x 1.97 (default) (See Table 38 for range) R54 (36h) 15 BG_ENA 0 Bandgap Bandgap Reference Control 0 = Disabled 1 = Enabled 4:0 BG_VSEL [4:0] 01010 Bandgap Voltage select (Sets the Bnadgap voltage) 00000 = 1.200V … 26.7mV steps 01010 = 1.467V (default) … 01111 = 1.600V 10000 to 11111 = reserved (See Table 39 for values) Table 37 LDO Regulator Control Rev 4.2 61 WM8944B LDO_VSEL [4:0] LDO OUTPUT LDO_VSEL [4:0] LDO OUTPUT 00h Vref x 1.42 10h Vref x 2.85 01h Vref x 1.50 11h Vref x 3.00 02h Vref x 1.58 12h Vref x 3.16 03h Vref x 1.66 13h Vref x 3.32 04h Vref x 1.74 14h Vref x 3.49 05h Vref x 1.82 15h Vref x 3.63 06h Vref x 1.90 16h Vref x 3.79 07h Vref x 1.97 17h Vref x 3.95 08h Vref x 2.06 18h Vref x 4.12 09h Vref x 2.13 19h Vref x 4.28 0Ah Vref x 2.21 1Ah Vref x 4.42 0Bh Vref x 2.29 1Bh Vref x 4.58 0Ch Vref x 2.37 1Ch Vref x 4.75 0Dh Vref x 2.45 1Dh Vref x 4.90 0Eh Vref x 2.53 1Eh Vref x 5.06 0Fh Vref x 2.69 1Fh Vref x 5.23 Note – Vref is the applicable voltage reference, selected by LDO_REF_SEL. Table 38 LDO Output Voltage Control BG_VSEL [4:0] BG VOLTAGE (V) BG_VSEL [4:0] BG VOLTAGE (V) 00h 1.200 08h 1.414 01h 1.227 09h 1.440 02h 1.253 0Ah 1.467 03h 1.280 0Bh 1.494 04h 1.307 0Ch 1.520 05h 1.334 0Dh 1.547 06h 1.360 0Eh 1.574 07h 1.387 0Fh 1.600 Table 39 Bandgap Voltage Control REFERENCE VOLTAGES AND MASTER BIAS This section describes the analogue reference voltage and bias current controls. It also describes the VMID soft-start circuit for pop suppressed start-up and shut-down. The analogue circuits in the WM8944B require a mid-rail analogue reference voltage, VMID. This reference is generated via a programmable resistor chain. Together with the external decoupling capacitor (connected to the VMIDC pin), the programmable resistor chain results in a slow, normal or fast charging characteristic on the VMID reference. This is enabled using VMID_ENA and VMID_SEL. The different resistor options controlled by VMID_SEL can be used to optimize the reference for normal operation, low power standby or for fast start-up as described in Table 40. The VMID resistor chain can be powered from the LDO output (LDOVOUT) or from the LDO supply (LDOVDD). This is selected using VMID_REF_SEL. Note that when VMID is selected as the LDO reference voltage, VMID cannot be generated from the LDOVOUT supply voltage (VMID_REF_SEL = 1) and must be generated from the LDOVDD supply voltage (VMID_REF_SEL = 0). The VMID ratio can be selected using VMID_CTRL. This selects the ratio of VMID to the supply voltage that has been selected by VMID_REF_SEL. VMID should be half of the LDOVOUT supply voltage for maximum voltage swing. In the case where VMID_REF_SEL has selected the LDOVOUT supply voltage, then VMID_CTRL should select the ratio “1/2”. In the case where VMID_REF_SEL 62 Rev 4.2 WM8944B has selected the LDOVDD supply voltage, then the alternate ratio “5/11” may be preferred, as described below. Note that the “5/11” ratio is designed for the case where LDOVDD = 3.3V and LDOVOUT = 3.0V. This results in a VMID = 3.3V x (5/11) = 1.5V which is half of the LDOVOUT voltage. If these conditions are not being used or the LDO has been bypassed then VMID_REF should be set to select LDOVOUT as the VMID source and VMID_CTRL should be set to select the ratio “1/2”. The speaker output drivers require a mid-rail reference voltage. The default operating conditions assume SPKVDD >= 3.0V, and use VMID as the reference. The reference can also be adjusted for SPKVDD = 1.8V. If SPKVDD = 1.8V, then the SPK_LOWVMID_ENA register should be set to 1. This selects a 0.9V mid-rail reference, enabling optimal power and THD performance at the lower SPKVDD voltage. Note that the speaker output reference is fixed with respect to LDOVOUT or LDOVDD; it does not scale with SPKVDD. Therefore, the speaker reference cannot be otimised for all SPKVDD conditions. If SPKVDD > 1.8V and < 3.0V, then SPK_LOWVMID_ENA should be set to 1, but the THD performance may be degraded. The analogue circuits in the WM8944B require a bias current. The normal (Master) bias current is enabled by setting BIAS_ENA. Note that the Master bias current source requires VMID to be enabled also. The Master Reference and Bias Control bits are defined in Table 40. REGISTER ADDRESS R7 (07h) BIT 10 LABEL VMID_REF_SEL DEFAULT 0 Additional control DESCRIPTION VMID Source Select 0 = LDO supply (LDOVDD) 1 = LDO output (LDOVOUT) 9 VMID_CTRL 0 VMID Ratio control Sets the ratio of VMID to the source selected by VMID_REF_SEL 0 = 5/11 1 = 1/2 4 VMID_ENA 0 VMID Enable 0 = Disabled 1 = Enabled R2 (02h) 5 Power Management 1 SPK_LOWVMID_ ENA 0 Selects 0.9V midrail voltage for speaker output drivers 0 = Disabled 1 = Enabled This bit should be enabled if SPKVDD = 1.8V 3 BIAS_ENA 0 Master Bias Enable 0 = Disabled 1 = Enabled 1:0 VMID_SEL [1:0] 00 VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast startup) Table 40 Reference Voltages and Master Bias Enable A pop-suppressed start-up requires VMID to be enabled smoothly, without the step change normally associated with the initial stage of the VMID capacitor charging. A pop-suppressed start-up also Rev 4.2 63 WM8944B requires the analogue bias current to be enabled throughout the signal path prior to the VMID reference voltage being applied. The WM8944B incorporates pop-suppression circuits which address these requirements. An alternate bias current source (Start-Up Bias) is provided for pop-free start-up; this is enabled by the STARTUP_BIAS_ENA register bit. The start-up bias is selected (in place of the Master bias) using the BIAS_SRC bit. It is recommended that the start-up bias is used during start-up, before switching back to the higher quality, normal bias. A soft-start circuit is provided in order to control the switch-on of the VMID reference. The soft-start control circuit offers two slew rates for enabling the VMID reference; these are selected and enabled by VMID_RAMP. When the soft-start circuit is enabled prior to enabling VMID_SEL, the reference voltage rises smoothly, without the step change that would otherwise occur. It is recommended that the soft-start circuit and the output signal path be enabled before VMID is enabled by VMID_SEL. A soft shut-down is provided, using the soft-start control circuit and the start-up bias current generator. The soft shut-down of VMID is achieved by setting VMID_RAMP, STARTUP_BIAS_ENA and BIAS_SRC to select the start-up bias current and soft-start circuit prior to setting VMID_SEL=00. The internal LDO (described in the previous section) requires a voltage reference. Under normal operating conditions, this is provided from VMID, via the register controls described in Table 40. Note, however, that VMID is normally generated from the LDO output. Therefore, an alternative voltage reference is required for start-up, which is not dependent on the LDO output. The VMID_FAST_START bit enables a ‘Fast-Start’ reference powered from LDOVDD. This alternate VMID can be selected as the LDO reference using the LDO_REF_SEL_FAST bit as described in Table 37. The VMID soft-start and fast start register controls are defined in Table 41. REGISTER ADDRESS R7 (07h) BIT LABEL DEFAULT 11 VMID_FAST_STA RT 0 STARTUP_BIAS_ ENA 0 BIAS_SRC 0 Additional control DESCRIPTION VMID (fast-start) Enable 0 = Disabled 1 = Enabled 8 Start-Up Bias Enable 0 = Disabled 1 = Enabled 7 Bias Source select 0 = Master bias 1 = Start-Up bias 6:5 VMID_RAMP [1:0] 00 VMID soft start enable / slew rate control 00 = Disabled 01 = Fast soft start 10 = Normal soft start 11 = Slow soft start Table 41 Soft Start Control POP SUPPRESSION CONTROL The WM8944B incorporates a number of features which are designed to suppress pops normally associated with Start-Up, Shut-Down or signal path control. These include the option to maintain an analogue output to VMID even when the output driver is disabled. In addition, there is the ability to actively discharge an output to GND. Note that, to achieve maximum benefit from these features, careful attention may be required to the sequence and timing of these controls. DISABLED OUTPUT CONTROL The line outputs and speaker outputs are biased to VMID in normal operation. In order to avoid audible pops caused by a disabled signal path dropping to GND, the WM8944B can maintain these connections at VMID when the relevant output stage is disabled. This is achieved by connecting a buffered VMID reference to the output. 64 Rev 4.2 WM8944B The buffered VMID reference is enabled by setting VMID_BUF_ENA. This is applied to any disabled outputs, provided that the respective _VMID_OP_ENA bit is also set. The output resistance can be either 1k or 20k, depending on the respective _VROI register bit. The disabled output control bits are described in Table 42. See “Output Signal Path” for details of how to disable any of the audio outputs. REGISTER ADDRESS R2 (02h) BIT LABEL DEFAULT 2 VMID_BUF_ENA 0 Power management 1 DESCRIPTION VMID Buffer Enable. (The buffered VMID may be applied to disabled input and output pins.) 0 = Disabled 1 = Enabled R42 (2Ah) 13 Output ctrl SPKN_VMID_OP _ENA 0 Buffered VMID to SPKOUTN Enable 0 = Disabled 1 = Enabled 12 SPKP_VMID_OP _ENA 0 Buffered VMID to SPKOUTP Enable 0 = Disabled 1 = Enabled 10 LINE_VMID_OP_ ENA 0 SPK_VROI 0 Buffered VMID to LINEOUT Enable 0 = Disabled 1 = Enabled 1 Buffered VREF to SPKOUTP / SPKOUTN resistance (Disabled outputs) 0 = approx 20k ohms 1 = approx 1k4 ohms 0 LINE_VROI 0 Buffered VREF to LINEOUT resistance (Disabled output) 0 = approx 20k ohms 1 = approx 1k1 ohms Table 42 Disabled Output Control OUTPUT DISCHARGE CONTROL The line outputs and speaker outputs can be actively discharged to GND through internal resistors if desired. This is desirable at start-up in order to achieve a known output stage condition prior to enabling the soft-start VMID reference voltage. This is also desirable in shut-down to prevent the external connections from being affected by the internal circuits. The individual control bits for discharging each audio output are described in Table 43. Rev 4.2 65 WM8944B REGISTER ADDRESS R42 (2Ah) BIT 7 LABEL SPKN_DISCH DEFAULT 0 Output ctrl DESCRIPTION Discharges SPKOUTN output via approx 550 ohm resistor 0 = Not active 1 = Actively discharging SPKOUTN 6 SPKP_DISCH 0 Discharges SPKOUTP output via approx 550 ohm resistor 0 = Not active 1 = Actively discharging SPKOUTP 4 LINE_DISCH 0 Discharges LINEOUT output via approx 550 ohm resistor 0 = Not active 1 = Actively discharging LINEOUT Table 43 Output Discharge Control 66 Rev 4.2 WM8944B DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data into the WM8944B and outputting ADC data from it. It uses four pins: ADCDAT - ADC / Digital Microphone data output DACDAT - DAC data input LRCLK - DAC and ADC data alignment clock BCLK - Bit clock, for synchronisation MASTER AND SLAVE MODE OPERATION The digital audio interface can be configured as a Master or a Slave interface, using the MSTR register bit. The two modes are illustrated in Figure 19 and Figure 20. BCLK BCLK LRCLK WM8944B LRCLK Processor ADCDAT WM8944B DACDAT ADCDAT Processor DACDAT Figure 19 Master Mode Figure 20 Slave Mode In Master mode, LRCLK and BCLK are configured as outputs, and the WM8944B controls the timing of the data transfer on the ADCDAT and DACDAT pins. In Master mode, the LRCLK frequency is determined automatically according to the sample rate (see “Clocking and Sample Rates”). The BCLK frequency is set by the BCLK_DIV register. BCLK_DIV must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer the complete data words from the ADCs and to the DACs. In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an external master. REGISTER ADDRESS R6 (06h) BIT 3:1 LABEL BCLK_DIV [2:0] DEFAULT 011 Clock Gen control DESCRIPTION BCLK Frequency (Master mode) 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 4 011 = SYSCLK / 8 100 = SYSCLK / 16 101 = SYSCLK / 32 110 = reserved 111 = reserved 0 MSTR 0 Digital Audio Interface Mode select 0 = Slave mode 1 = Master mode Table 44 Digital Audio Interface Control Rev 4.2 67 WM8944B AUDIO DATA FORMATS Three basic audio data formats are supported: Left justified I2S DSP mode All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. PCM operation is supported using the DSP mode. The WM8944B is largely a mono device. In the default configuration, the WM8944B transmits ADC data on the Left channel only of the Digital Audio Interface, and receives DAC data on the Left channel. The WM8944B also supports a stereo digital microphone interface, enabling stereo output on the digital audio interface (ADCDAT pin). The digital audio interface transmit configuration can be set using the ADCR_SRC and ADCL_SRC bits; the DAC receive channel can be selected using the DAC_SRC bit. Digital inversion of the ADC and DAC data is also possible. The register bits controlling audio data format and channel configuration are described in Table 45. REGISTER ADDRESS R4 (04h) BIT 9 LABEL ADCR_SRC DEFAULT DESCRIPTION 1 Right Digital Audio interface source Audio Interface 0 = ADC / Left DMIC data is output on right channel 1 = Right DMIC data is output on right channel 8 ADCL_SRC 0 Left Digital Audio interface source 0 = ADC / Left DMIC data is output on left channel 1 = Right DMIC data is output on left channel 6 DAC_SRC 0 DAC Data Source Select 0 = DAC outputs left interface data 1 = DAC outputs right interface data 5 BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 4 LRCLK_INV 0 LRCLK Polarity / DSP Mode A-B select. Left Justified and I2S modes – LRCLK polarity 0 = Not Inverted 1 = Inverted DSP Mode – Mode A-B select 0 = MSB is available on 2nd BCLK rising edge after LRCLK rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRCLK rising edge (mode B) 68 Rev 4.2 WM8944B REGISTER ADDRESS BIT LABEL WL [1:0] 3:2 DEFAULT DESCRIPTION 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note – see “Companding” for the selection of 8-bit mode. FMT [1:0] 1:0 Digital Audio Interface Format 10 00 = Reserved 01 = Left Justified 10 = I2S format 11 = DSP/PCM mode R21 (15h) DAC_DATINV 0 DAC Data Invert 0 DAC Control 1 0 = DAC output not inverted 1 = DAC output inverted R25 (19h) 1 ADCR_DATINV Right DMIC Data Invert 0 ADC Control 1 0 = Right DMIC output not inverted 1 = Right DMIC output inverted 0 ADCL_DATINV ADC / Left DMIC Data Invert 0 0 = ADC / Left DMIC output not inverted 1 = ADC / Left DMIC inverted Table 45 Audio Data Format Control In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) n-1 n 1 2 3 n-2 n-1 n LSB Figure 21 Left Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Rev 4.2 69 WM8944B 1/fs LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK 1 BCLK DACDAT/ ADCDAT 1 2 1 BCLK 3 MSB n-2 n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 22 I2S Justified Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selected by LRCLK_INV) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRCLK output resembles the frame pulse shown in Figure 23 and Figure 24. In device slave mode, Figure 25 and Figure 26, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. 1/fs 1/2fs LRCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 23 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=0, Master) 1/fs 1/2fs LRCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 MSB 2 3 n-2 Input Word Length (WL) RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Figure 24 DSP/PCM Mode Audio Interface (mode B, LRCLK_INV=1, Master) 70 Rev 4.2 WM8944B 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 n 1 2 3 n-2 n-1 n LSB Input Word Length (WL) Figure 25 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=1, Slave) 1/fs LRCLK Falling edge can occur anywhere in this area 1 BCLK 1 BCLK BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 MSB 3 n-2 RIGHT CHANNEL n-1 Input Word Length (WL) n 1 2 3 n-2 n-1 n LSB Figure 26 DSP/PCM Mode Audio Interface (mode B, LRCLK_INV=1, Slave) COMPANDING The WM8944B supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 46. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low-amplitude signals than for high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. REGISTER ADDRESS R5 (05h) BIT 3 LABEL DAC_COMP DEFAULT 0 Companding control DESCRIPTION DAC Companding Enable 0 = Disabled 1 = Enabled 2 DAC_COMPMO DE 0 ADC_COMP 0 DAC Companding Mode 0 = µ-law 1 = A-law 1 ADC Companding Enable 0 = Disabled 1 = Enabled 0 ADC_COMPMO DE 0 ADC Companding Mode 0 = µ-law 1 = A-law Table 46 Companding Control Rev 4.2 71 WM8944B Companding uses a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) } for -1 ≤ x ≤ 1 A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) for x ≤ 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) for 1/A ≤ x ≤ 1 u-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input Figure 27 µ-Law Companding A-law Companding 1 120 0.9 Companded Output 0.7 80 0.6 0.5 60 0.4 40 0.3 Normalised Output 0.8 100 0.2 20 0.1 0 0 0 0.2 0.4 0.6 0.8 1 Normalised Input Figure 28 A-Law Companding 72 Rev 4.2 WM8944B The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). Companded data is transmitted in the first 8 MSBs of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4 bits), as shown in Table 47. BIT7 BIT[6:4] BIT[3:0] SIGN EXPONENT MANTISSA Table 47 8-bit Companded Word Composition 8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles per Left/Right Clock frame. When using DSP mode B, 8-bit data words may be transferred consecutively every 8 BCLK cycles. 8-bit mode (without Companding) may be enabled by setting ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0. DAC_COMPMODE=1 or AUDIO INTERFACE LOOPBACK A loopback function is provided for test and evaluation purposes. When the LOOPBACK register bit is set, the DAC input data is fed through the DSP Core to the Left ADC output, as illustrated in Figure 29. Note that this is only possible when ADCL_ENA = 1 and ADCR_ENA = 0. There is no output on the Right ADC channel when the Audio Interface Loopback is enabled. SE1 (LPF/HPF, 3D surround, 5-notch, DF1) SE2 (HPF, Re-Tune, 5-band EQ) ADC DAC SE3 (Dynamic Range Control) DIGITAL AUDIO INTERFACE Audio Interface Loopback Mode BCLK LRCLK DACDAT ADCDAT Figure 29 Audio Interface Loopback Rev 4.2 73 WM8944B REGISTER ADDRESS BIT R5 (05h) 5 LABEL LOOPBACK DEFAULT DESCRIPTION Audio Interface Loopback Function 0 Companding control 0 = No loopback 1 = Audio Interface Loopback enabled (DACDAT input is fed through the DSP Core to the ADCDAT output). Table 48 Audio Interface Loopback Control ADC TO DAC LOOPBACK A loopback function is also provided to allow the ADC digital data output to be fed internally to the DAC data input. This function is enabled by ADC_DAC_LOOPBACK and is illustrated in Figure 30. SE1 (LPF/HPF, 5-notch, DF1) SE2 (HPF, Re-Tune, 5-band EQ) ADC DAC SE3 (Dynamic Range Control) DIGITAL AUDIO INTERFACE ADC to DAC Loopback Mode BCLK LRCLK DACDAT ADCDAT Figure 30 ADC to DAC Loopback REGISTER ADDRESS R5 (05h) Companding control BIT LABEL 15 ADC_DAC_LOO PBACK DEFAULT DESCRIPTION ADC to DAC Loopback Function 0 = No loopback 1 = ADC to DAC Loopback enabled (ADC data is fed directly into DAC data input). Table 49 ADC to DAC Loopback Control 74 Rev 4.2 WM8944B DIGITAL PULL-UP AND PULL-DOWN The WM8944B provides integrated pull-up and pull-down resistors on each of the DACDAT, LRCLK and BCLK pins. This provides a flexible capability for interfacing with other devices. Each of the pullup and pull-down resistors can be configured independently using the register bits described in Table 50. REGISTER ADDRESS R4 (04h) BIT LABEL DEFAULT DESCRIPTION 15:14 DACDATA_PUL L [1:0] 00 DACDAT pull-up / pull-down Enable Audio interface 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 13:12 FRAME_PULL [1:0] 00 LRCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 BCLK_PULL [1:0] 00 BCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved Table 50 Pull-Up and Pull-Down Control CLOCKING AND SAMPLE RATES The internal clocks for the CODEC and Digital Audio Interface are derived from a common internal clock source, SYSCLK. This clock can either be derived directly from MCLK, or may be generated using the Frequency Locked Loop (FLL) using MCLK as a reference. All commonly-used audio sample rates can be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a wider range of MCLK frequencies. The WM8944B supports a wide range of standard audio sample rates from 8kHz to 48kHz. When the ADC and DAC are both enabled, they operate at the same sample rate, fs. Other functions such as the Interrupts and GPIO input de-bounce are clocked using a free-running oscillator. The control registers associated with Clocking and Sample Rates are described in Table 51. The overall clocking scheme for the WM8944B is illustrated in Figure 31. Rev 4.2 75 WM8944B SYSCLK_DIV [2:0] SYSCLK_ENA MCLK fREF fOUT FLL FLL_ENA FLL_CLK_REF_DIV FLL_N FLL_K FLL_FRATIO FLL_FRAC FLL_OUTDIV f/N SYSCLK (512 x fs) or (256 x fs) CODEC DSP SYSCLK_SRC SR [3:0] SYSCLK_RATE MASTER MODE CLOCK OUTPUTS f/64 f/N LRCLK BCLK MSTR BCLK_DIV [2:0] CLKOUT_DIV [1:0] CLKOUT_SEL f/N Oscillator CLKOUT CLKOUT may be output on a GPIO pin OSC_CLK_ENA Clocking for GPIO de-bounce and Interrupt functions TOCLK_ENA Clocking for PGA Zero-Cross timeouts Figure 31 WM8944B Clocking Overview SYSCLK may be derived either from MCLK or from the FLL; this is selected using the SYSCLK_SRC register bit. SYSCLK is enabled using the SYSCLK_ENA and may be modified using a programmable divider configured by SYSCLK_DIV. The SYSCLK_RATE register must be set according to the ratio of SYSCLK to the audio sample rate. It is required that SYSCLK_DIV is correctly set in order to produce either 512 x fs or 256 x fs at its output, where fs is the audio sampling rate. The sampling rate for the CODEC and Digital Audio Interface is configured using the SR register field. In Master mode, the frequency of the Left/Right Clock output on the LRCLK pin is the BCLK frequency divided by 64 producing 32 BCLK cycles per channel. In Master mode, the BCLK_DIV register configures the bit clock frequency output on BCLK. The WM8944B can output a configurable clock on the GPIO pins; this is enabled automatically whenever a GPIO pin is configured for CLKOUT output. The source can either be before or after the SYSCLK divider, as shown in Figure 31. The source is selected using CLKOUT_SEL, and may be modified using a programmable divider configured by CLKOUT_DIV. The WM8944B free-running oscillator required for GPIO input de-bounce and Interrupt functions must be enabled using OSC_CLK_ENA whenever any of these functions is required. REGISTER ADDRESS R6 (06h) BIT LABEL DEFAULT 15 OSC_CLK_ENA 0 Clock Gen control DESCRIPTION Oscillator Enable 0 = Disabled 1 = Enabled This needs to be set when a timeout clock is required for GPIO input detection 14:13 MCLK_PULL [1:0] 00 MCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 76 Rev 4.2 WM8944B REGISTER ADDRESS BIT 12 LABEL CLKOUT_SEL DEFAULT 0 DESCRIPTION CLKOUT Source Select 0 = SYSCLK 1 = FLL or MCLK (set by SYSCLK_SRC register) 11:10 CLKOUT_DIV [1:0] 00 CLKOUT Clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 9 SYSCLK_ENA 0 SYSCLK Enable 0 = Disabled 1 = Enabled 8 SYSCLK_SRC 0 SYSCLK Source Select 0 = MCLK 1 = FLL output 7:5 SYSCLK_DIV [2:0] 000 SYSCLK Clock divider (Sets the scaling for either the MCLK or FLL clock output, depending on SYSCLK_SRC) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 4 TOCLK_ENA 0 TOCLK Enabled (Enables timeout clock for GPIO level detection) 0 = Disabled 1 = Enabled R7 (07h) 15 SYSCLK_RATE 1 Additional control Selects the SYSCLK / fs ratio 0 = SYSCLK = 256 x fs 1 = SYSCLK = 512 x fs 3:0 SR [3:0] 1101 Audio Sample Rate select 0011 = 8kHz 0100 = 11.025kHz 0101 = 12kHz 0111 = 16kHz 1000 = 22.05kHz 1001 = 24kHz 1011 = 32kHz 1100 = 44.1kHz 1101 = 48kHz Table 51 Clocking and Sample Rate Control Rev 4.2 77 WM8944B DIGITAL MIC CLOCKING When any GPIO is configured as DMICCLK output, the WM8944B outputs a clock which supports Digital Mic operation at the ADC sampling rate. Although the ADC is not used, the SYSCLK and Sample Rate control fields must still be set as they would for ADC operation. The clock frequencies for each of the sample rates is shown in Table 52. PCM SAMPLE RATE DMICCLK FS RATE 8kHz 1.024MHz 128fs 11.025kHz 1.411MHz 128fs 12kHz 1.536MHz 128fs 16kHz 2.048MHz 128fs 22.05kHz 2.8224MHz 128fs 24kHz 3.072MHz 128fs 32kHz 2.048MHz 64fs 44.1kHz 2.8224MHz 64fs 48kHz 3.072MHz 64fs Table 52 Digital Microphone Clock Frequencies FREQUENCY LOCKED LOOP (FLL) The integrated FLL can be used to generate SYSCLK from a wide variety of different reference sources and frequencies. The FLL uses MCLK as its reference, which may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32,768kHz) reference. The FLL is tolerant of jitter and may be used to generate a stable SYSCLK from a less stable input signal. The FLL characteristics are summarised in “Electrical Characteristics”. The FLL control registers are described in Figure 32. MCLK Divide by FLL_CLK_REF_DIV FREF Multiply by N.K Multiply by FLL_FRATIO N.K = Real number FLL_FRATIO = 1, 2, 4, 8, 16 FREF<13.5MHz FLL_CLK_REF_DIV = 1, 2, 4, 8 FVCO FOUT Divide by FLL_OUTDIV 90MHz < Fvco < 100MHz FLL_OUTDIV = 4, 8, 16, 32 Figure 32 FLL Configuration The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other register settings have been updated. When changing the input reference frequency FREF, it is recommended that the FLL be reset by setting FLL_ENA to 0. The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK) by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For best performance, it is recommended that the highest possible frequency – within the 13.5MHz limit – should be selected. The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only the default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should be set to the recommended value. The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the field FLL_FRAC. Power consumption in the FLL is reduced in integer mode; however, the performance may also be reduced, with increased noise or jitter on the output. If low power consumption is required, then FLL settings must be chosen where N.K is an integer (ie. FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0. 78 Rev 4.2 WM8944B For best FLL performance, a non-integer value of N.K is required. In this case, the fractional mode must be enabled by setting FLL_FRAC = 1. The FLL settings must be adjusted, if necessary, to produce a non-integer value of N.K. The FLL output frequency is generated according to the following equation: FOUT = (FVCO / FLL_OUTDIV) The FLL operating frequency, FVCO is set according to the following equation: FVCO = (FREF x N.K x FLL_FRATIO) FREF is the input frequency, as determined by FLL_CLK_REF_DIV. FVCO must be in the range 90-100 MHz. Frequencies outside this range cannot be supported. Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures. In order to follow the above requirements for FVCO, the value of FLL_OUTDIV should be selected according to the desired output FOUT, as described in Table 53. OUTPUT FREQUENCY FOUT FLL_OUTDIV 2.8125 MHz – 3.125 MHz 4h (divide by 32) 5.625 MHz – 6.25 MHz 3h (divide by 16) 7.5 MHz - 8.333 MHz 7h (divide by 12) 11.25 MHz – 12.5 MHz 2h (divide by 8) 15 MHz - 16.667 MHz 6h (divide by 6) 22.5 MHz – 25 MHz 1h (divide by 4) 45 MHz – 50 MHz 0h (divide by 2) Table 53 Selection of FLL_OUTDIV The value of FLL_FRATIO should be selected as described in Table 54. REFERENCE FREQUENCY FREF FLL_FRATIO 1MHz - 13.5MHz 0h (divide by 1) 256kHz - 1MHz 1h (divide by 2) 128kHz - 256kHz 2h (divide by 4) 16kHz - 128kHz 3h (divide by 8) Less than 16kHz 4h (divide by 16) Table 54 Selection of FLL_FRATIO In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be calculated, as given by the following equation: FVCO = (FOUT x FLL_OUTDIV) The value of FLL_N and FLL_K can then be determined as follows: N.K = FVCO / (FLL_FRATIO x FREF) Note that FREF is the input frequency, after division by FLL_CLK_REF_DIV, where applicable. Rev 4.2 79 WM8944B In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field. This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if desired, the value of this field may be calculated by multiplying K by 2^16 and treating FLL_K as an integer value, as illustrated in the following example: If N.K = 8.192, then K = 0.192. Multiplying K by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) Apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex) For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations yield an integer value of N.K, then it is recommended to adjust FLL_FRATIO in order to obtain a noninteger value of N.K. Care must always be taken to ensure that the FLL operating frequency, FVCO, is within its recommended limits of 90-100 MHz. The register fields that control the FLL are described in Table 55. Example settings for a variety of reference frequencies and output frequencies are shown in Table 56. REGISTER ADDRESS R8 (08h) BIT LABEL DEFAULT 12:11 FLL_CLK_RE F_DIV [1:0] 00 FLL Control 1 DESCRIPTION FLL Clock Reference Divider 00 = MCLK / 1 01 = MCLK / 2 10 = MCLK / 4 11 = MCLK / 8 MCLK must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired. 10:8 FLL_OUTDIV [2:0] 001 FOUT clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 6 111 = 12 (FOUT = FVCO / FLL_OUTDIV) 7:5 FLL_CTRL_R ATE [2:0] 000 Frequency of the FLL control block 000 = FVCO / 1 (Recommended value) 001 = FVCO / 2 010 = FVCO / 3 011 = FVCO / 4 100 = FVCO / 5 101 = FVCO / 6 110 = FVCO / 7 111 = FVCO / 8 Recommended that this register is not changed from default. 80 Rev 4.2 WM8944B REGISTER ADDRESS BIT LABEL DEFAULT 4:2 FLL_FRATIO [2:0] 000 DESCRIPTION FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 000 recommended for FREF > 1MHz 100 recommended for FREF < 16kHz 011 recommended for all other cases 1 FLL_FRAC 1 Fractional enable 0 = Integer Mode 1 = Fractional Mode Integer mode offers reduced power consumption. Fractional mode offers best FLL performance, provided also that N.K is a non-integer value. 0 FLL_ENA 0 FLL Enable 0 = Disabled 1 = Enabled R9 (09h) 15:0 FLL_K [15:0] 3127h 14:5 FLL_N [9:0] 008h FLL Control 2 R10 (0Ah) Fractional multiply for FREF (MSB = 0.5) FLL Control 3 Integer multiply for FREF (LSB = 1) 3:0 FLL_GAIN [3:0] 0000 Gain applied to error 0000 = x 1 (Recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 Recommended that this register is not changed from default. Table 55 Frequency Locked Loop Control Rev 4.2 81 WM8944B EXAMPLE FLL CALCULATION To generate 24.576MHz output (FOUT) from a 12.000MHz reference clock (FREF): 82 Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz: FLL_CLK_REF_DIV = 00 (divide by 1) Set FLL_CTRL_RATE to the recommended setting: FLL_CTRL_RATE = 000 (divide by 1) Sett FLL_GAIN to the recommended setting: FLL_GAIN = 0000 (multiply by 1) Set FLL_OUTDIV for the required output frequency as shown in Table 53:FOUT = 24.576MHz, therefore FLL_OUTDIV = 1h (divide by 4) Set FLL_FRATIO for the given reference frequency as shown in Table 54: FREF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1) Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:FVCO = 24.576 x 4 = 98.304MHz Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF): N.K = 98.304 / (1 x 12) = 8.192 Determine FLL_N and FLL_K from the integer and fractional portions of N.K:FLL_N is 8(dec) = 008(hex). FLL_K is 0.192 (dec) = 3127(hex). Confirm that N.K is a fractional quantity and set FLL_FRAC: N.K is fractional. Set FLL_FRAC = 1. Note that, if N.K is an integer, then an alternative value of FLL_FRATIO may be selected in order to produce a fractional value of N.K. Rev 4.2 WM8944B EXAMPLE FLL SETTINGS Table 56 provides example FLL settings for generating common SYSCLK frequencies from a variety of low and high frequency reference inputs. FREF FOUT FLL_CLK_ REF_DIV FVCO FLL_N FLL_K FLL_ FRATIO FLL_ OUTDIV 8.000 22.5792 divide by 1 90.3168 705 0.6 16 4 kHz MHz (0h) MHz (2C1h) (9999h) (4h) (1h) 8.000 24.576 divide by 1 98.304 768 0.0 16 4 kHz MHz (0h) MHz (300h) (0000h) (4h) (1h) 32.768 22.5792 divide by 1 90.3168 344 0.53125 8 4 kHz MHz (0h) MHz (158h) (8800h) (3h) (1h) 32.768 24.576 divide by 1 98.304 375 0.0 8 4 kHz MHz (0h) MHz (177h) (0000h) (3h) (1h) 768.000 22.5792 divide by 1 90.3168 14 0.7 8 4 kHz MHz (0h) MHz (00Eh) (B333h) (3h) (1h) 768.000 24.576 divide by 1 98.304 16 0.0 8 4 kHz MHz (0h) MHz (010h) (0000h) (3h) (1h) 1.024 22.5792 divide by 1 90.3168 88 0.2 1 4 MHz MHz (0h) MHz (058h) (3333h) (0h) (1h) 1.024 24.576 divide by 1 98.304 96 0.0 1 4 MHz MHz (0h) MHz (060h) (0000h) (0h) (1h) 6.144 22.5792 divide by 1 90.3168 14 0.7 1 4 MHz MHz (0h) MHz (00Eh) (B333h) (0h) (1h) 6.144 24.576 divide by 1 98.304 16 0.0 1 4 MHz MHz (0h) MHz (010h) (0000h) (0h) (1h) 11.2896 22.5792 divide by 1 90.3168 8 0.0 1 4 MHz MHz (0h) MHz (008h) (0000h) (0h) (1h) 11.2896 24.576 divide by 1 98.304 8 0.70749 1 4 MHz MHz (0h) MHz (008h) (B51Eh) (0h) (1h) 12.000 22.5792 divide by 1 90.3168 7 0.5264 1 4 MHz MHz (0h) MHz (007h) (86C2h) (0h) (1h) 12.000 24.576 divide by 1 98.304 8 0.192 1 4 MHz MHz (0h) MHz (008h) (3127h) (0h) (1h) 12.288 22.5792 divide by 1 90.3168 7 0.35 1 4 MHz MHz (0h) MHz (007h) (599Ah) (0h) (1h) 12.288 24.576 divide by 1 98.304 8 0.0 1 4 MHz MHz (0h) MHz (008h) (0000h) (0h) (1h) 13.000 22.5792 divide by 1 90.3168 6 0.94745 1 4 MHz MHz (0h) MHz (006h) (F28Ch) (0h) (1h) 13.000 24.576 divide by 1 98.304 7 0.56185 1 4 MHz MHz (0h) MHz (007h) (8FD5h) (0h) (1h) 19.200 22.5792 divide by 2 90.3168 9 0.408 1 4 MHz MHz (1h) MHz (009h) (6873h) (0h) (1h) 19.200 24.576 divide by 2 98.304 10 0.24 1 4 MHz MHz (1h) MHz (00Ah) (3D71h) (0h) (1h) 27.000 22.5792 divide by 2 90.3168 6 0.69013 1 4 MHz MHz (1h) MHz (006h) (B0ADh) (0h) (1h) 27.000 24.576 divide by 2 98.304 7 0.28178 1 4 MHz MHz (1h) MHz (007h) (4823h) (0h) (1h) FLL_ FRAC 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 Table 56 Example FLL Settings Rev 4.2 83 WM8944B VIDEO BUFFER The WM8944B provides a current mode output video buffer with an input 3rd order Butterworth low pass filter (LPF) and clamp. The video buffer is powered from LDOVDD - typically 3.3V. The video buffer is compatible with PAL and NTSC video formats. The low pass filter (LPF) is intended to remove images in the video DAC output waveform at multiples of the DAC clock frequency. The input clamp supports AC coupling at the input to the video buffer. The current mode output employed by the WM8944B video buffer allows operation at lower supply voltages than voltage mode video buffers. The current mode output also provides inherent protection against short circuits during jack insertion and removal. A current reference resistor (positioned close to the WM8944B) ensures that the signal swing at the output of the buffer is the same as that at the receiving equipment (e.g. a television set), thus providing excellent signal reproduction. For best performance, the input to the video buffer should be AC coupled and terminated to 75. Note that the input clamp and pull-down features described below are only applicable to the AC-coupled input configuration. Care should be taken with PCB layout, designing for at least 1GHz frequencies to avoid degrading performance. PCB vias and sharp corners should be avoided and parasitic capacitance minimised on signal paths; these should be kept as short and straight as possible. The LDOVDD supply should be decoupled as close to the WM8944B as possible. See the “External Components” section for more information. The video buffer is enabled using the VB_ENA register bit. The gain of the video buffer is selected using VB_GAIN; this can be set to 0dB or 6dB (corresponding to 6dB or 12dB unloaded). The LPF response can be adjusted by setting the VB_QBOOST register; this provides a small amount of additional gain in the region of the cut-off frequency. The input signal clamp is enabled using VB_CLAMP; this controls the DC component of the video signal for compatibility with the WM8944B. The video buffer pull-down can be enabled using VB_PD; this may be used during power-up of the video buffer in order to align the signal levels between the source and the WM8944B. Note that the pull-down should not be enabled during normal operation of the video buffer; it should be enabled when the video buffer is first powered up, and subsequently disabled (eg. after20ms) once the circuit has settled. A programmable DC offset can be applied to the output signal using the VB_DISOFF register field; this can be set to 0mV, 20mV or 40mV offset. Note that the VMID reference (see “Voltage References and Master Bias”) must be enabled when using the WM8944B video buffer. VMID is enabled by setting VMID_ENA, as defined in Table 40. The video buffer control registers are described in Table 57. REGISTER ADDRESS R38 (26h) BIT 7 LABEL VB_ENA DEFAULT 0 Video Buffer DESCRIPTION Video buffer enable 0 = Disabled 1 = Enabled 6 VB_QBOOST 0 Video buffer filter Q-Boost control 0 = Disabled 1 = Enabled 5 VB_GAIN 0 Video buffer gain 0 = 0dB (=6dB unloaded) 1 = 6dB (=12dB unloaded) 84 Rev 4.2 WM8944B REGISTER ADDRESS BIT LABEL 4:3 VB_DISOFF [1:0] DEFAULT 111 DESCRIPTION Video buffer DC offset control 000 = Reserved 001 = 40mV offset 010 = Reserved 011 = 20mV offset 100 = Reserved 101 = Reserved 110 = Reserved 111 = 0mV offset Note - the specified offset applies to the 0dB gain setting (VB_GAIN=0). When 6dB gain is selected, the DC offset is doubled. VB_PD 1 0 Video buffer pull-down 0 = pull-down disabled 1 = pull-down enabled VB_CLAMP 0 0 Enable the clamp between the video input and ground 0 = no clamp 1 = Video buffer input is clamped to ground Table 57 Video Buffer Control The video buffer circuit is illustrated in Figure 33. LDOVDD VIDEO BUFFER 6dB / 12dB (unloaded) 0dB / 6dB (fully loaded) TV in VBIN LPF VBOUT clamp RLOAD VBREF RSOURCE RREF Figure 33 Video Buffer Block Diagram The video buffer requires two external resistor components, as illustrated in Figure 33. For best performance, the resistor RSOURCE should be matched (equal) to the load impedance RLOAD. The resistance RREF is a function of the circuit gain and a function of the parallel combination of RSOURCE and RLOAD. When VB_GAIN = 0 (0dB gain), the current gain of the video buffer is 5, as described by the equation IVBOUT = 5 x IVBREF. The resistor RREF should be set equal to 5 x (RSOURCE // RLOAD), where (RSOURCE // RLOAD) is the effective resistance of the parallel combination of RSOURCE and RLOAD. (Note that the required resistance RREF is the same for both settings of VB_GAIN.) In a typical application, RLOAD = 75, RSOURCE = 75, RREF = 187. Rev 4.2 85 WM8944B RECOMMENDED VIDEO BUFFER INITIALISATION SEQUENCES Recommended power-up sequences for Video Buffer applications are described in Table 58 and Table 59. DESCRIPTION LABEL REGISTER [BITS] Turn on external supplies and wait for the supply voltages to settle. Reset registers to default state (software reset). SW_RESET R0 (00h) [15:0] Enable VMID Fast Start and Start up Bias. Select Start-Up Bias and set VMID soft start for start-up ramp. VMID_FAST_START = 1 STARTUP_BIAS_ENA = 1 BIAS_SRC = 1 VMID_RAMP[1:0] = 01 R7 (07h) [11] R7 (07h) [8] R7 (07h) [7] R7 (07h) [6:5] If using VMID as the reference voltage for the LDO then select VMID fast start or set to 0 if using the Bandgap as the reference voltage for LDO. Select LDO Start-Up Bias and enable LDO. LDO_ENA = 1 LDO_REF_SEL_FAST = 1 LDO_BIAS_SRC = 1 R53 (35h) [15] R53 (35h) [14] R53 (35h) [5] Set VMID_SEL[1:0] for fast start-up. BIAS_ENA = 1 VMID_BUF_ENA = 1 VMID_SEL[1:0] = 11 R2 (02h) [3] R2 (02h) [2] R2 (02h) [1:0] Enable VMID. VMID_ENA = 1 R7 (07h) [4] Set LDO and VMID for normal operation. LDO_REF_SEL_FAST = 0 LDO_BIAS_SRC = 0 VMID_FAST_START = 0 STARTUP_BIAS_ENA = 0 VMID_SEL = 01 R53 (35h) [14] R53 (35h) [5] R7 (07h) [11] R7 (07h) [8] R2 (02h) [1:0] Set Video Buffer Gain as required. VB_GAIN R38 (26h) [5] Set Video Buffer Filter Q Boost as required. VB_QBOOST R38 (26h) [6] Enable Video Buffer Clamp. VB_CLAMP = 1 R38 (26h) [0] Enable Video Buffer Pulldown. VB_PD = 1 R38 (26h) [1] Enable video buffer. VB_ENA = 1 R38 (26h) [7] VB_PD = 0 R38 (26h) [1] Delay 300ms for LDO to settle. Enable VMID Buffer and Master Bias. Delay 50ms to allow VMID to settle. Delay 20ms for buffer to capture input level. Disable Video Buffer Pulldown. Table 58 Power-Up Sequence (Video Signal AC-coupled to Video Buffer input) 86 Rev 4.2 WM8944B DESCRIPTION LABEL REGISTER [BITS] Turn on external supplies and wait for the supply voltages to settle. Reset registers to default state (software reset). SW_RESET R0 (00h) [15:0] Enable VMID Fast Start and Start up Bias. Select Start-Up Bias and set VMID soft start for start-up ramp. VMID_FAST_START = 1 STARTUP_BIAS_ENA = 1 BIAS_SRC = 1 VMID_RAMP[1:0] = 01 R7 (07h) [11] R7 (07h) [8] R7 (07h) [7] R7 (07h) [6:5] If using VMID as the reference voltage for the LDO then select VMID fast start or set to 0 if using the Bandgap as the reference voltage for LDO. Select LDO Start-Up Bias and enable LDO. LDO_ENA = 1 LDO_REF_SEL_FAST = 1 LDO_BIAS_SRC = 1 R53 (35h) [15] R53 (35h) [14] R53 (35h) [5] Set VMID_SEL[1:0] for fast start-up. BIAS_ENA = 1 VMID_BUF_ENA = 1 VMID_SEL[1:0] = 11 R2 (02h) [3] R2 (02h) [2] R2 (02h) [1:0] Enable VMID VMID_ENA = 1 R7 (07h) [4] Set LDO and VMID for normal operation. LDO_REF_SEL_FAST = 0 LDO_BIAS_SRC = 0 VMID_FAST_START = 0 STARTUP_BIAS_ENA = 0 VMID_SEL = 01 R53 (35h) [14] R53 (35h) [5] R7 (07h) [11] R7 (07h) [8] R2 (02h) [1:0] Set Video Buffer Gain as required VB_GAIN R38 (26h) [5] Set Video Buffer Filter Q Boost as required VB_QBOOST R38 (26h) [6] Enable video buffer VB_ENA = 1 R38 (26h) [7] Delay 300ms for LDO to settle. Enable VMID Buffer and Master Bias. Delay 50ms to allow VMID to settle Table 59 Power-Up Sequence (Video Signal DC-coupled to Video Buffer input) Rev 4.2 87 WM8944B GENERAL PURPOSE INPUT/OUTPUT The WM8944B provides two multi-function pins which can be configured to provide a number of different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins are: CS ¯¯ /GPIO1 CIFMODE/GPIO2 Note that the GPIO pins are shared with Control Interface functions. The pins available for GPIO function depend on the selected Control Interface mode, as described in Table 60. CONTROL INTERFACE MODE 2-wire (I2C) GPIO PIN AVAILABILITY GPIO1 GPIO2 3-wire (SPI) GPIO2 Table 60 GPIO Pin Availability Note that CIFMODE/GPIO2 pin selects between I2C and SPI Control Interface modes (see “Control Interface”). To enable GPIO functions on GPIO2, the MODE_GPIO register bit must be set in order to disconnect this pin from the Control Interface circuit. Setting the MODE_GPIO register bit causes the Control Interface mode selection to be latched; it will remain latched until a Software Reset or Power On Reset occurs. The register fields that control the GPIO pins are described in Table 61. For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1 or 2). The pin direction, set by GPn_DIR, must be set according to function selected by GPn_SEL. When a pin is configured as a GPIO output, its level can be set to logic 0 or logic 1 using the GPn_LVL field. When a pin is configured as a GPIO input, the logic level can be read from the respective GPn_LVL bit. The GPIO output is inverted with respect to the GPn_LVL register when the polarity bit GPn_POL is set; the equivalent is true of GPIO inputs also. Internal pull-up and pull-down resistors may be enabled using the GPn_PULL fields; this allows greater flexibility to interface with different signals from other devices. Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt event. This may be configured as level-triggered or edge-triggered using the GPn_FN registers. Edge detect raises an interrupt when the GPIO status changes; level detect asserts the interrupt for as long as the GPIO status is asserted. See “Interrupts”. An edge-triggered GPIO can be configured to trigger on a single edge or on both edges of the input signal; this is selected using the GPn_INT_MODE registers. A level-triggered or single-edge-triggered input may be configured using the GPn_POL registers to respond to a high level/edge (when GPn_POL = 0) or a low level/edge (when GPn_POL = 1). The GPIO control fields are defined in Table 61. REGISTER ADDRESS R11 (0Bh) BIT 0 LABEL MODE_GPIO DEFAULT DESCRIPTION 0 CIFMODE/GPIO2 pin configuration GPIO Config 0 = Pin configured as CIFMODE 1 = Pin configured as GPIO2 Note - when this bit is set to 1, it is latched and cannot be reset until Power-Off or Software Reset. R13 (0Dh) GPIO1 Control 88 15 GP1_DIR 1 GPIO1 Pin Direction 0 = Output 1 = Input Rev 4.2 WM8944B REGISTER ADDRESS BIT LABEL DEFAULT 14:13 GP1_PULL [1:0] 00 DESCRIPTION GPIO1 pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 GP1_INT_ 0 MODE GPIO1 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP1_POL=0) or falling edge triggered (if GP1_POL =1) 1 = GPIO interrupt is triggered on rising and falling edges 10 GP1_POL 0 GPIO1 Polarity Select 0 = Non-inverted 1 = Inverted 5 GP1_LVL 0 GPIO1 level. Write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP1_POL is set, the register contains the opposite logic level to the external pin. 3:0 GP1_FN [3:0] 15 GP2_DIR 0000 GPIO1 Pin Function (see Table 62 for details) R14 (0Eh) 1 GPIO2 Control GPIO2 Pin Direction 0 = Output 1 = Input 14:13 GP2_PULL [1:0] 10 GPIO2 pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 GP2_INT_ 0 MODE GPIO2 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP2_POL=0) or falling edge triggered (if GP2_POL =1) 1 = GPIO interrupt is triggered on rising and falling edges 10 GP2_POL 0 GPIO2 Polarity Select 0 = Non-inverted 1 = Inverted 5 GP2_LVL 0 GPIO2 level. Write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP2_POL is set, the register contains the opposite logic level to the external pin. 3:0 GP2_FN [3:0] 0000 GPIO2 Pin Function (see Table 62 for details) Table 61 GPIO Control GPIO FUNCTION SELECT The available GPIO functions are described in Table 62. The function of each GPIO is set using the GPn_FN register, where n identifies the GPIO pin (1 or 2). Note that the polarity of the GPIO inputs and outputs may be selected using the GPn_POL register bits. When GPn_POL = 1, then the polarity is inverted with respect to the descriptions below. Rev 4.2 89 WM8944B The GPIO input functions may be used to detect headphone jack insertion or a button press. These signals may be used as inputs to the Interrupt Controller, via the integrated de-bounce circuit. GPn_FN DESCRIPTION 0000 Logic level input 0001 Edge detection input COMMENTS External logic level is read from GPn_LVL. Associated interrupt (when enabled) is level-triggered. External logic level is read from GPn_LVL. Associated interrupt (when enabled) is edge triggered. Note that TOCLK_ENA must be set. 0010 CLKOUT output Output clock frequency is set by CLKOUT_DIV. 0011 Interrupt (IRQ) output Hardware output of all unmasked Interrupts. 0100 Reserved 0101 Reserved 0110 Reserved 0111 Temperature flag output Indicates the temperature sensor output. This is a hardware output of the TEMP_STS bit (assuming GPn_POL = 0). 0 = Normal 1 = Overtemperature 1000 Reserved 1001 DMICCLK output Output clock for digital microphone interface 1010 Logic level output Pin logic level is set by GPn_LVL. 1011 LDO_UV output Indicates the LDO undervoltage status. This is a hardware output of the LDO_UV_STS bit (assuming GPn_POL = 0). 0 = Normal 1 = LDO undervoltage 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Table 62 GPIO Function Select INTERRUPTS The Interrupt Controller has multiple inputs. These include the GPIO input pins, Temperature sensor and the LDO Regulator. Any combination of these inputs can be used to trigger an Interrupt (IRQ) event. There is an Interrupt Status field associated with each of the IRQ inputs. These are listed within the System Interrupts Register (R16), as described in Table 63. The status of the IRQ inputs can be read at any time from this register or else in response to the Interrupt (IRQ) output being signalled via a GPIO pin. Individual mask bits can select or deselect different functions from the Interrupt controller. These are listed within the System Interrupts Mask Register (R19), as described in Table 63. Note that the status fields remain valid, even when masked, but the masked bits will not cause the Interrupt (IRQ) output to be asserted. The Interrupt (IRQ) output represents the logical ‘OR’ of all the unmasked IRQ inputs. The bits within the System Interrupts Register (R16) are latching fields and, once they are set, they are not reset until the System Interrupts Register is read. Accordingly, the Interrupt (IRQ) output is not reset until the System Interrupts Register has been read. Note that, if the condition that caused the IRQ input to be asserted is still valid, then the Interrupt (IRQ) output will remain set even after the System Interrupts Register has been read. When GPIO input is used to trigger an Interrupt event, polarity can be set using the GPn_POL bits as described in Table 61. This allows the IRQ event to be used to indicate a rising or a falling edge of the external logic signal. If desired, the GPn_INT_MODE bits can be used to select an Interrupt event on both the rising and falling edges. 90 Rev 4.2 WM8944B The GPIO inputs to the Interrupt Controller are de-bounced to avoid false detections. The timeout clock (TOCLK) is required for this function. When using GPIO inputs to the Interrupt Controller, the TOCLK must be enabled by setting the TOCLK_ENA and OSC_CLK_ENA bits as described in “Clocking and Sample Rates”. The Interrupt (IRQ) output can be globally masked by setting the IM_IRQ register. The Interrupt is masked by default. The Interrupt (IRQ) output may be configured on any of the GPIO pins. See “General Purpose Input / Output” for details of how to configure GPIO pins for Interrupt (IRQ) output. The Interrupt control fields are defined in Table 63. REGISTER ADDRESS BIT R16 (10h) 15 LABEL TEMP_INT DEFAULT 0 DESCRIPTION Thermal Interrupt status (Read only) System Interrupts 0 = Thermal interrupt not set (Read only) This bit is latched when set; it is cleared when the register is Read. 1 = Thermal interrupt set 13 GP2_INT 0 GPIO2 Interrupt status (Read only) 0 = GPIO2 interrupt not set 1 = GPIO2 interrupt set This bit is latched when set; it is cleared when the register is Read. 12 GP1_INT 0 GPIO1 Interrupt status (Read only) 0 = GPIO1 interrupt not set 1 = GPIO1 interrupt set This bit is latched when set; it is cleared when the register is Read. 0 LDO_UV_INT 0 LDO Undervoltage Interrupt (Read only) 0 = LDO Undervoltage interrupt not set 1 = LDO Undervoltage interrupt set This bit is latched when set; it is cleared when the register is Read. R18 (12h) 0 IM_IRQ 1 IRQ Config IRQ (GPIO output) Mask 0 = Normal 1 = IRQ output is masked R19 (13h) System Interrupts Mask 15 IM_TEMP_INT 0 Interrupt mask for thermal status 0 = Not masked 1 = Masked 13 IM_GP2_INT 0 Interrupt mask for GPIO2 0 = Not masked 1 = Masked 12 IM_GP1_INT 0 Interrupt mask for GPIO1 0 = Not masked 1 = Masked 0 IM_LDO_UV_IN T 0 Interrupt mask for LDO Undervoltage status 0 = Not masked 1 = Masked Table 63 Interrupt Control Rev 4.2 91 WM8944B CONTROL INTERFACE The WM8944B is controlled by writing to its control registers. Readback is available for all registers. The Control Interface can operate as either a 2- or 3-wire interface: 2-wire (I2C) mode uses pins SCLK and SDA 3-wire (SPI) mode uses pins CS ¯¯ , SCLK and SDA Readback is provided on the bi-directional pin SDA in 2-/3-wire modes. The device address in 2-wire (I2C) mode is 34h. The WM8944B uses 15-bit register addresses and 16-bit data in all Control Interface modes. SELECTION OF CONTROL INTERFACE MODE The WM8944B Control Interface can be configured for I2C mode or SPI modes using the CIFMODE/GPIO2 pin at power-up. The mode selection is as described in Table 65. CIFMODE/GPIO2 INTERFACE FORMAT Low 2-wire High 3-wire Table 64 Control Interface Mode Selection After the Control Interface Mode has been configured, the MODE_GPIO register bit should be set in order to latch the selection and to allow GPIO functions to be supported on the CIFMODE/GPIO2 pin. After the MODE_GPIO register bit has been set, the Control Interface mode selection will remain latched until a Software Reset or Power On Reset occurs. See “General Purpose Input / Output” for details. In 2-wire (I2C) Control Interface mode, Auto-Increment mode may be selected. This enables multiple write and multiple read operations to be scheduled faster than is possible with single register operations. The auto-increment option is enabled when the AUTO_INC register bit is set. This bit is defined in Table 65. Auto-increment is enabled by default. In 3-wire (SPI) Control Interface mode, register readback is provided using the bi-directional pin SDA. When the SDA pin is an output, it may be configured as CMOS or as Open Drain using the SPI_OD bit. An external pull-up resistor is required if using the Open Drain output. The Control Interface configuration bits are described in Table 65. REGISTER ADDRESS R20 (14h) BIT 2 LABEL SPI_OD DEFAULT 0 Control Interface DESCRIPTION SDA pin output configuration 0 = SDA output is CMOS 1 = SDA output is Open-Drain 0 AUTO_INC 1 Enables address auto-increment (applies to 2-wire / I2C mode only) 0 = Disabled 1 = Enabled Table 65 Control Interface Configuration 92 Rev 4.2 WM8944B 2-WIRE (I2C) CONTROL MODE In 2-wire mode, the WM8944B is a slave device on the control interface; SCLK is a clock input, while SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8944B transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by the master. In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 8-bit device ID (this is not the same as the 15-bit address of each register in the WM8944B). The WM8944B device ID is 0011 0100 (34h). The LSB of the device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”. The WM8944B operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDA while SCLK remains high. This indicates that a device ID, register address and data will follow. The WM8944B responds to the start condition and shifts in the next eight bits on SDA (8-bit device ID including Read/Write bit, MSB first). If the device ID received matches the device ID of the WM8944B, then the WM8944B responds by pulling SDA low on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only mode, the WM8944B returns to the idle condition and waits for a new start condition and valid address. If the device ID matches the device ID of the WM8944B, the data transfer continues as described below. The controller indicates the end of data transfer with a low to high transition on SDA while SCLK remains high. After receiving a complete address and data sequence the WM8944B returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns to the idle condition. The WM8944B supports the following read and write operations: Single write Single read Multiple write using auto-increment Multiple read using auto-increment The sequence of signals associated with a single register write operation is illustrated in Figure 34. SCLK SDA D7 START D1 device ID A15 R/W (Write) ACK A9 A7 A8 register address A15 - A8 ACK A1 A0 register address A7 - A0 B15 ACK B9 data bits B15 – B8 B8 B7 ACK B1 data bits B7 – B0 B0 ACK STOP Note: The SDA pin is used as input for the control register address and data; SDA is pulled low by the receiving device to provide the acknowledge (ACK) response Figure 34 Control Interface 2-wire (I2C) Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 35. Rev 4.2 93 WM8944B SCLK SDA D1 D7 START device ID A15 R/W (Write) ACK A9 A8 A7 register address A15 – A8 A1 register address A7 – A0 D1 Rpt START ACK device ID B9 B15 R/W (Read) device ID D7 A0 B8 data bits B15 – B8 ACK B1 B7 ACK data bits B15 – B8 B0 ACK STOP Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses Figure 35 Control Interface 2-wire (I2C) Register Read The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in Table 66. Note that, for multiple write and multiple read operations, the auto-increment option must be enabled. This feature is enabled by default, as noted in Table 65. TERMINOLOGY DESCRIPTION S Start Condition Sr Repeated start A Acknowledge (SDA Low) ¯¯ A Not Acknowledge (SDA High) P Stop Condition R/W̄¯ ReadNotWrite 0 = Write 1 = Read [White field] Data flow from bus master to WM8944B [Grey field] Data flow from WM8944B to bus master Table 66 Control Interface Terminology 8 bit Device ID S Device ID 8 bits RW A MSByte Address 8 bits 8 bits A LSByte Address A 8 bits MSByte Data A LSByte Data A P (0) Figure 36 Single Register Write to Specified Address S Device ID RW A MSByte Address A LSByte Address (0) A Sr Device ID RW A MSByte Data A LSByte Data A P (1) Figure 37 Single Register Read from Specified Address 94 Rev 4.2 WM8944B Written to 'Register Address' S Device ID RW A MSByte Address LSByte Address A A MSByte Data 0 A LSByte Data 0 A MSByte Data 1 (0) Written to 'Register Address+N-1' MSByte Data N-2 A MSByte Data N-1 A Written to 'Register Address+N' LSByte Data N-1 A MSByte Data N A LSByte Data N A P Figure 38 Multiple Register Write to Specified Address using Auto-increment Read from 'Register Address' S Device ID RW A MSByte Address A LSByte Address A Sr Device ID (0) MSByte Data 0 A LSByte Data 0 A (1) Read from 'Last Register Address+N-1' A A RW MSByte Data N-1 A Read from 'Last Register Address+N' LSByte Data N-1 A MSByte Data N A LSByte Data N A P Figure 39 Multiple Register Read from Specified Address using Auto-increment Read from 'Last Register Address' S Device ID RW A MSByte Data 0 A LSByte Data 0 Read from 'Last Register Address+1' A MSByte Data 1 A LSByte Data 1 A (1) Read from 'Last Register Address+N-1' A MSByte Data N-1 A LSByte Data N-1 Read from 'Last Register Address+N' A MSByte Data N A LSByte Data N A P Figure 40 Multiple Register Read from Last Address using Auto-increment Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of the data in the WM8944B register map faster than is possible with single register operations. The auto-increment option is enabled when the AUTO_INC register bit is set. This bit is defined in Table 65. Auto-increment is disabled by default. 3-WIRE (SPI) CONTROL MODE The 3-wire control interface uses the CS ¯¯ , SCLK and SDA pins. In 3-wire control mode, a control word consists of 32 bits. The first bit is the read/write bit (R/W), which is followed by 15 address bits (A14 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDA pin. The data is latched on the 32nd falling edge of SCLK after 32 bits of data have been clocked into the device. In Write operations (R/W=0), all SDA bits are driven by the controlling device. In Read operations (R/W=1), the SDA pin is driven by the controlling device to clock in the register address, after which the WM8944B drives the SDA pin to output the applicable data bits. When the SPI_OD register bit is set, the WM8944B transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by the master. The 3-wire control mode timing is illustrated in Figure 41. Rev 4.2 95 WM8944B CS SCLK SDA R/W A14 A13 A12 A2 A1 A0 B15 15-bit control register address B14 B13 B2 B1 B0 16-bit control register data Figure 41 3-Wire Serial Control Interface POWER MANAGEMENT The WM8944B has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise, it is important to enable or disable these functions in the correct order, and to use the signal mute registers as part of a carefully structured control sequence. The power management control registers are described in Table 67. REGISTER ADDRESS R2 (02h) Power management 1 BIT 12 LABEL INPGA_ENA DEFAULT 0 DESCRIPTION Input PGA Enable 0 = Disabled 1 = Enabled 11 ADCR_ENA 0 Right ADC Enable 0 = Disabled 1 = Enabled ADCR_ENA must be set to 1 when processing right channel data from the Digital Microphone. 10 ADCL_ENA 0 Left ADC Enable 0 = Disabled 1 = Enabled ADCL_ENA must be set to 1 when processing data from the ADC or from the Left Digital Microphone. 4 MICB_ENA 0 Microphone Bias Enable 0 = Disabled 1 = Enabled 3 BIAS_ENA 0 Master Bias Enable 0 = Disabled 1 = Enabled R3 (03h) Power management 2 14 OUT_ENA 0 LINEOUT enable 0 = Disabled 1 = Enabled 12 SPK_PGA_ENA 0 Speaker PGA enable 0 = Disabled 1 = Enabled 96 Rev 4.2 WM8944B REGISTER ADDRESS BIT LABEL DEFAULT 11 SPKN_SPKVDD _ENA 0 DESCRIPTION SPKOUTN enable 0 = Disabled 1 = Enabled Note that SPKOUTN is also controlled by SPKN_OP_ENA. When powering down SPKOUTN, the SPKN_SPKVDD_ENA bit should be reset first. 10 SPKP_SPKVDD _ENA 0 SPKOUTP enable 0 = Disabled 1 = Enabled Note that SPKOUTP is also controlled by SPKP_OP_ENA. When powering down SPKOUTP, the SPKP_SPKVDD_ENA bit should be reset first 7 SPKN_OP_ENA 0 SPKOUTN enable 0 = Disabled 1 = Enabled Note that SPKOUTN is also controlled by SPKN_SPKVDD_ENA. When powering up SPKOUTN, the SPKN_OP_ENA bit should be enabled first. 6 SPKP_OP_ENA 0 SPKOUTP enable 0 = Disabled 1 = Enabled Note that SPKOUTP is also controlled by SPKP_SPKVDD_ENA. When powering up SPKOUTP, the SPKP_OP_ENA bit should be enabled first 2 SPK_MIX_ENA 0 Speaker output mixer enable 0 = Disabled 1 = Enabled 0 DAC_ENA 0 DAC Enable 0 = Disabled 1 = Enabled DAC_ENA must be set to 1 when processing data from the DAC or Digital Beep Generator. Table 67 Power Management Control Note: In 2-wire mode in order to achieve the minimum power down current from DBVDD the CIF_MODE pin should be configured as a GPIO pin by setting register R11 (0Bh) bit 0 high and configured as an input in register R14 (0Eh) bit 0 set high. Pull-up and pull-down resistors should be disabled in register R14 (0Eh) bits 14:13 set to 00. Rev 4.2 97 WM8944B THERMAL SHUTDOWN The WM8944B incorporates a temperature sensor which detects when the device temperature is within normal limits. The temperature status can be read at any time from the TEMP_STS bit, as described in Table 68. This bit can be polled at any time, or may output directly on a GPIO pin, or may be used to generate Interrupt events. The temperature sensor can be configured to shut down the speaker outputs in the event of an overtemperature condition. This is configured using the THERR_ACT register field. REGISTER ADDRESS BIT R17 (11h) LABEL TEMP_STS 15 DEFAULT 0 Status Flags DESCRIPTION Thermal Sensor status (Read only) 0 = Normal 1 = Overtemperature R42 (2Ah) THERR_ACT 15 1 Output ctrl Thermal Shutdown enable 0 = Disabled 1 = Enabled When THERR_ACT = 1, then an over temperature condition will cause the speaker outputs to be disabled. Table 68 Thermal Shutdown Control Note: For minimum power down current the thermal shutdown should be disabled by setting the THERR_ACT bit in register R42 (2Ah) bit 15 low. POWER ON RESET The WM8944B includes a Power-On Reset (POR) circuit, which is used to reset the digital logic into a default state after power up. The POR circuit derives its output from LDOVDD and DCVDD. The internal POR ¯¯¯ signal is asserted low when either LDOVDD or DCVDD are below minimum thresholds. The specific behaviour of the circuit will vary, depending on relative timing of the supply voltages. Typical scenarios are illustrated in Figure 42 and Figure 43. LDOVDD Vpora Vpora_off 0V DCVDD Vpord_on 0V HI Internal POR LO Internal POR active POR Undefined Internal POR active Device Ready Figure 42 Power On Reset Timing – LDOVDD Enabled First 98 Rev 4.2 WM8944B LDOVDD Vpora Vpora_on 0V DCVDD Vpord_off 0V HI Internal POR Internal POR active LO POR Undefined Internal POR active Device Ready Figure 43 Power On Reset Timing - DCVDD Enabled First The POR ¯¯¯ signal is undefined until LDOVDD has exceeded the minimum threshold, Vpora Once this threshold has been exceeded, POR ¯¯¯ is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Once LDOVDD and DCVDD have both reached their respective power on thresholds, POR ¯¯¯ is released high, all registers are in their default state, and writes to the control interface may take place. Note that a minimum power-on reset period, TPOR, applies even if LDOVDD and DCVDD have zero rise time. (This specification is guaranteed by design rather than test.) On power down, POR ¯¯¯ is asserted low when LDOVDD or DCVDD falls below their respective powerdown thresholds. Typical Power-On Reset parameters for the WM8944B are defined in Table 69. SYMBOL DESCRIPTION MIN TYP MAX UNIT Power-On undefined threshold (LDOVDD) 0.5 V Vpora_on Power-On threshold (LDOVDD/DBVDD) 1.17 V Vpora_off Power-Off threshold (LDOVDD/DBVDD) 1.13 V Vpord_on Power-On threshold (DCVDD) 0.66 V Vpord_off Power-Off threshold (DCVDD) 0.64 V Minimum Power-On Reset period 10.6 s Vpora TPOR Table 69 Typical Power-On Reset Parameters Separate Power-On Reset circuits are also implemented on the DBVDD and SPKVDD domains. These circuits ensure correct device behaviour whenever these supplies are enabled or disabled. Rev 4.2 99 WM8944B SOFTWARE RESET AND DEVICE ID The WM8944B can be reset by writing to Register R0. This is a read-only register, and the contents of R0 will not be affected by writing to this Register. The Device ID can be read back from Register R0. The Chip Revision ID can be read back from Register 1, as described in Table 70. REGISTER ADDRESS BIT LABEL R0 (00h) 15:0 SW_RESET [15:0] Software Reset/Chip ID 1 R1 (01h) DEFAULT DESCRIPTION 6264h Writing to this register resets all registers to their default state. Reading from this register will indicate device family ID 6264h. 3:0 CHIP_REV [3:0] Revision Number 0h Reading from this register will indicate the Revision ID. (Read only) Table 70 Chip Reset and ID 100 Rev 4.2 WM8944B RECOMMENDED POWER UP / POWER-DOWN SEQUENCES In order to minimise output pop and click noise, it is recommended that the WM8944B device is powered-up and powered-down using the control sequences described in Table 71 and Table 72 respectively. The power-up sequence described here includes enabling the DACs and output drivers; note that additional configuration will be required to enable the required internal signal paths. The sequences noted here are provided as guidance only; each sequence will require to be adjusted to the particular application requirements. DESCRIPTION LABEL REGISTER [BITS] Turn on external supplies and wait for the supply voltages to settle. Reset registers to default state (software reset). SW_RESET R0 (00h) [15:0] Enable speaker and line discharge bits. SPKP_DISCH = 1 SPKN_DISCH = 1 LINE_DISCH = 1 SPKP_VMID_OP_ENA = 1 SPKN_VMID_OP_ENA = 1 LINE_VMID_OP_ENA = 1 R42 (2Ah) [6] R42 (2Ah) [7] R42 (2Ah) [4] R42 (2Ah) [12] R42 (2Ah) [13] R42 (2Ah) [10] Enable VMID Fast Start and Start up Bias. Select Start-Up Bias and set VMID soft start for start-up ramp. VMID_FAST_START = 1 STARTUP_BIAS_ENA = 1 BIAS_SRC = 1 VMID_RAMP[1:0] = 01 R7 (07h) [11] R7 (07h) [8] R7 (07h) [7] R7 (07h) [6:5] If using VMID as the reference voltage for the LDO then select VMID fast start or set to 0 if using the Bandgap as the reference voltage for LDO. Select LDO Start-Up Bias and enable LDO. LDO_ENA = 1 LDO_REF_SEL_FAST = 1 LDO_BIAS_SRC = 1 R53 (35h) [15] R53 (35h) [14] R53 (35h) [5] BIAS_ENA = 1 VMID_BUF_ENA = 1 VMID_SEL[1:0] = 11 R2 (02h) [3] R2 (02h) [2] R2 (02h) [1:0] Disable speaker and line discharge bits. SPKP_DISCH = 0 SPKN_DISCH = 0 LINE_DISCH = 0 R42 (2Ah) [6] R42 (2Ah) [7] R42 (2Ah) [4] Enable speaker outputs and speaker PGA and lineout output as required. SPK_MIX_ENA = 1 DAC_ENA = 1 SPKN_OP_ENA = 1 SPKP_OP_ENA = 1 SPK_PGA_ENA = 1 OUT_ENA = 1 R3 (03h) [2] R3 (03h) [0] R3 (03h) [7] R3 (03h) [6] R3 (03h) [12] R3 (03h) [14] Enable power to speaker driver (must be done after enabling the speaker outputs). SPKN_SPKVDD_ENA = 1 SPKP_SPKVDD_ENA = 1 R3 (03h) [11] R3 (03h) [10] Enable VMID. Delay 50ms to allow VMID to settle. VMID_ENA = 1 R7 (07h) [4] Set LDO and VMID for normal operation. LDO_REF_SEL_FAST = 0 LDO_BIAS_SRC = 0 VMID_FAST_START = 0 STARTUP_BIAS_ENA = 0 VMID_SEL = 01 R53 (35h) [14] R53 (35h) [5] R7 (07h) [11] R7 (07h) [8] R2 (02h) [1:0] Enable VMID to speaker and line outputs. Delay 300ms for LDO to settle. Enable VMID Buffer and Master Bias. Set VMID_SEL[1:0] for fast start-up. Un-mute outputs as required. Table 71 Recommended Power-Up Sequence Rev 4.2 101 WM8944B DESCRIPTION LABEL REGISTER [BITS] Mute speaker PGA and DAC. SPK_PGA_MUTE = 1 SPK_VOL = 00h DAC_MUTE = 1 DAC_VOL = 0 R47 (2Fh) [6] R47 (2Fh) [5:0] R23 (17h) [8] R23 (17h) [7:0] Select LDO for fast start-up. LDO_REF_SEL_FAST = 1 LDO_BIAS_SRC = 1 R53 (35h) [14] R53 (35h) [5] Select VMID for fast start-up. VMID_SEL = 11 VMID_FAST_START =1 BIAS_SRC = 1 VMID_RAMP = 01 R2 (02h) [1:0] R7 (07h) [11] R7 (07h) [7] R7 (07h) [6:5] Disable VMID. VMID_ENA = 0 R7 (07h) [4] SPKP_DISCH = 1 SPKN_DISCH = 1 LINE_DISCH = 1 R42 (2Ah) [7] R42 (2Ah) [6] R42 (2Ah) [4] Mute the speaker and line outputs. LINEOUT_MUTE = 1 SPKN_OP_MUTE = 1 SPKP_OP_MUTE = 1 R42 (2Ah) [8] R03 (03h) [9] R03 (03h) [8] Disable power to speaker drivers (must be done before disabling the speaker outputs). SPKN_SPKVDD_ENA = 0 SPKP_SPKVDD_ENA = 0 R3 (03h) [11] R3 (03h) [10] Disable speaker outputs. SPKN_OP_ENA = 0 SPKP_OP_ENA = 0 R3 (03h) [7] R3 (03h) [6] Reset registers to default state (software reset). SW_RESET R0 (00h) [15:0] Delay 500ms for VMID to discharge. Discharge the speaker and line outputs. Delay 50ms for outputs to discharge. Turn off external power supply voltages. Table 72 Recommended Power-Down Sequence 102 Rev 4.2 WM8944B REGISTER MAP REG NAME 15 14 13 12 11 10 9 8 7 6 R0 (0h) Software Reset/Chip ID 1 R1 (1h) Chip ID 2 (Read only) 0 0 0 R2 (2h) Power management 1 0 0 0 INP ADCR_ ADCL PGA_E ENA _ENA NA R3 (3h) Power management 2 0 OUT_E NA 0 SPK_P SPKN_ SPKP_ SPKN_ SPKP_ SPKN_ SPKP_ GA_EN SPKVD SPKVD OP_MU OP_MU OP_EN OP_EN A D_ENA D_ENA TE TE A A R4 (4h) Audio Interface DACDATA_PUL FRAME_PULL L [1:0] [1:0] R5 (5h) Companding control ADC_D AC_LO OP R6 (6h) Clock Gen control OSC_C LK_EN A R7 (7h) Additional control SYSCL K_RAT E 0 0 R8 (8h) FLL Control 1 0 0 0 R9 (9h) FLL Control 2 R10 (Ah) FLL Control 3 0 R11 (Bh) GPIO Config 0 R13 (Dh) GPIO1 Control R14 (Eh) 5 4 3 2 1 0 SW_RESET[15:0] 0 0 MCLK_PULL [1:0] 0 0 CLK OUT_S EL 0 0 0 BCLK_PULL [1:0] 0 0 CLKOUT_DIV [1:0] 0 0 0 0 0 DMIC_ ENA 0 0 0 SYS SYS CLK_E CLK_S NA RC 0 0 FLL_OUTDIV [2:0] 0 0 0 SPK_M IX_MU TE DAC_S BCLK_I LRCLK RC NV _INV 0 CHIP_REV[3:0] 0000h SPK_L MICB_ BIAS_E VMID_ VMID_SEL[1:0] OW ENA NA BUF_E VMID_ NA ENA LOOPB ACK SYSCLK_DIV [2:0] VMID_ VMID_ VMID_ START BIAS_S FAST_ REF_S CTRL UP_BIA RC START EL S_ENA FLL_CLK_REF_ DIV [1:0] 6264h 0 ADCR_ ADCL SRC _SRC VMID_RAMP [1:0] FLL_CTRL_RATE [2:0] 0 0 SPK_M IX_ENA 0 WL [1:0] DAC_E NA FMT [1:0] DAC_C DAC_C ADC_C ADC_C OMP OMPM OMP OMPM ODE ODE TOCLK _ENA BCLK_DIV [2:0] VMID_ ENA SR [3:0] FLL_FRATIO [2:0] MSTR 0 0310h 020Ah 0000h 0106h FLL_F FLL_E RAC NA 0102h 3127h 0 FLL_GAIN [3:0] 0 0 0 0 0 0 0 GP1_DI GP1_PULL [1:0] GP1_IN R T_MOD E 0 GP1_P OL 0 0 0 0 GP1_L VL 0 GP1_FN [3:0] 8000h GPIO2 Control GP2_DI GP2_PULL [1:0] GP2_IN R T_MOD E 0 GP2_P OL 0 0 0 0 GP2_L VL 0 GP2_FN [3:0] C000h R16 (10h) System Interrupts (Read only) TEMP_ INT 0 0 0 0 0 0 0 0 0 0 0 0 LDO_U V_INT 0000h R17 (11h) Status Flags (Read only) TEMP_ STS 0 R18 (12h) IRQ Config 0 0 R19 (13h) System Interrupts Mask IM_TE MP_IN T 0 R20 (14h) Control Interface 0 0 0 R21 (15h) DAC Control 1 0 0 R22 (16h) DAC Control 2 0 R23 (17h) DAC digital Vol R25 (19h) ADC Control 1 GP2_IN GP1_IN T T 0 0 0 0100h 0 Rev 4.2 0 0000h 800Dh FLL_K [15:0] FLL_N [9:0] 0 DEFAULT MODE_ GPIO 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO_U V_STS 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 IM_IRQ 0001h 0 0 0 0 0 0 0 0 0 0 0 IM_LD O_UV_I NT 0000h 0 0 0 0 0 0 0 0 0 0 SPI_O D 0 AUTO_ INC 0001h 0 0 0 0 0 0 0 0 0 DAC_A UTOM UTE 0 0 0 DAC_D AT INV 0010h 0 0 0 0 0 0 0 0 0 0 DAC_V OL_RA MP 0 0 0 DAC_S B_FLT 0010h 0 0 0 0 0 0 0 DAC_M UTE 0 0 0 0 0 0 0 ADC_M UTEAL L IM_GP IM_GP 2_INT 1_INT DAC_VOL [7:0] 0 0 0 0 0 01C0h 0 ADCR_ ADCL DAT _DAT INV INV 103 0100h WM8944B REG NAME 15 14 13 12 11 10 9 8 7 0 6 5 4 3 2 1 0 DEFAULT ADC_H PF 0021h R26 (1Ah) ADC Control 2 0 0 0 0 0 0 0 0 R27 (1Bh) Left ADC Digital Vol 0 0 0 ADC_V U 0 0 0 ADCL_ MUTE ADCL_VOL [7:0] 00C0h R28 (1Ch) Right ADC Digital Vol 0 0 0 ADC_V U 0 0 0 ADCR_ MUTE ADCR_VOL [7:0] 00C0h R29 (1Dh) DRC Control 1 0 0 0 0 0 0 0 DRC_N DRC_E G_ENA NA R30 (1Eh) DRC Control 2 0 0 0 R31 (1Fh) DRC Control 3 0 0 0 R32 (20h) DRC Control 4 0 0 0 DRC_KNEE2_IP [4:0] R33 (21h) DRC Control 5 0 0 DRC_K NEE2_ OP_EN A DRC_KNEE2_OP [4:0] R34 (22h) DRC Control 6 0 0 0 0 0 0 R35 (23h) DRC Control 7 0 0 0 0 0 0 R36 (24h) DRC Status (Read only) R37 (25h) Beep Control 1 0 0 0 0 0 0 0 0 R38 (26h) Video Buffer 0 0 0 0 0 0 0 0 R39 (27h) Input ctrl 0 0 0 0 0 0 AUX_T O_N_I NPGA 0 R40 (28h) Input PGA gain ctrl 0 0 0 0 0 0 0 0 R42 (2Ah) Output ctrl THERR _ACT 0 0 LINE_V MID_O P_ENA 0 R43 (2Bh) SPK mixer control1 0 0 0 0 0 AUX IN1_TO AUX_T PGA_T BYP_T MDAC_ DIFF_T _PGA O_SPK O_SPK O_PGA TO_PG O_PGA P P A R44 (2Ch) SPK mixer control2 0 0 0 0 0 R45 (2Dh) SPK mixer control3 0 0 0 0 0 R46 (2Eh) SPK mixer control4 0 0 0 0 0 0 IN1_TO _SPKN _ATTE N 0 PGA_T O_SPK N_ATT EN R47 (2Fh) SPK volume ctrl 0 0 0 0 0 0 0 0 SPK_Z SPK_P C GA_MU TE R49 (31h) Line mixer control 1 0 0 0 0 0 104 DRC_NG_MINGAIN [3:0] 0 0 0 0 1 0 0 1 ADC_H ADC_HPF_SR PF_MO [1:0] DE ADC_HPF_CUT [2:0] 0 0 0 1 DRC_Q DRC_A R NTI CLIP 0 1 DRC_MINGAIN [2:0] DRC_ATK [3:0] DRC_MAX GAIN [1:0] DRC_DCY [3:0] DRC_KNEE_IP [5:0] 0 DRC_KNEE_OP [4:0] 0 DRC_NG_ EXP [1:0] 0 0 0 1 0 DRC_LO_COMP [2:0] DRC_QR_DCY [1:0] DRC_INIT [4:0] SPKN_ SPKP_ VMID_ VMID_ OP_EN OP_EN A A 0 IN1_TO _SPKN 0 BEEP_GAIN [3:0] VB_EN VB_QB VB_GA A OOST IN MICB_ LVL 0 AUX IN1_TO AUX_T PGA_T BYP_T DIFF_T _PGA_ O_SPK O_SPK O_PGA O_PGA ATTEN P_ATT P_ATT _ATTE _ATTE EN EN N N AUX IN1_TO DIFF_T _OUT O_OUT 0 0 0 0 BEEP_RATE [1:0] VB_DISOFF [2:0] 0 INPGA INPGA _ZC _MUTE PGA_T O_SPK N 0003h 0000h 0000h LINE_ SPKN_ SPKP_ MUTE DISCH DISCH 0 0000h 0000h DRC_GAIN [15:0] 0 0C25h 0342h 0 DRC_HI_COMP [2:0] DRC_QR_THR [1:0] 000Fh 0 0 BEEP_ ENA 0002h VB_PD VB_CL AMP 001Ch P_PGA_SEL [1:0] 0001h INPGA_VOL [5:0] 0 0050h LINE_D ISCH 0 0 0 DAC_T O_PGA 0 0 AUX_T O_PGA 0000h 0 0 0 0 0 0 0000h 0 0 DAC_T O_PGA _ATTE N 0 0 AUX_T O_PGA _ATTE N 0000h 0 0 0 0 0 0 0000h BYP_T MDAC_ O_OUT TO_OU T SPK_V LINE_V ROI ROI SPK_VOL [5:0] 0 DAC_T O_OUT 0 8100h 0079h 0 AUX_T O_OUT Rev 4.2 0000h WM8944B REG NAME 15 14 13 12 11 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 DEFAULT 0 0 BYP_T O_OUT _ATTE N 0 0 DAC_T O_OUT _ATTE N 0 0 AUX_T O_OUT _ATTE N 0000h R51 (33h) Line L mixer control 2 R53 (35h) LDO LDO_E LDO_R LDO_R LDO_O NA EF_SE EF_SE PFLT L_FAS L T 0 0 0 0 0 0 LDO_BI AS_SR C LDO_VSEL [4:0] 0007h R54 (36h) Bandgap BG_EN A 0 0 0 0 0 0 0 0 0 0 BG_VSEL [4:0] 000Ah R64 (40h) SE Config Selection 0 0 0 0 0 0 0 0 0 0 R65 (41h) SE1_LHPF_CONFIG 0 0 0 0 0 0 0 0 0 0 R66 (42h) SE1_LHPF_L R67 (43h) SE1_LHPF_R R68 (44h) SE1_3D_CONFIG 0 0 R69 (45h) SE1_3D_L 0 0 SE1_3D_L_ DELAY [2:0] SE1_3D_L_CUTOFF [2:0] SE1_3D_L_CGAIN [3:0] SE1_3D_L_FGAIN [3:0] 0408h R70 (46h) SE1_3D_R 0 0 SE1_3D_R_ DELAY [2:0] SE1_3D_R_CUTOFF [2:0] SE1_3D_R_CGAIN [3:0] SE1_3D_R_FGAIN [3:0] 0408h R71 (47h) SE1_NOTCH_CONFI G 0 0 R72 (48h) SE1_NOTCH_A10 SE1_NOTCH_A10 [15:0] 0000h R73 (49h) SE1_NOTCH_A11 SE1_NOTCH_A11 [15:0] 0000h R74 (4Ah) SE1_NOTCH_A20 SE1_NOTCH_A20 [15:0] 0000h R75 (4Bh) SE1_NOTCH_A21 SE1_NOTCH_A21 [15:0] 0000h R76 (4Ch) SE1_NOTCH_A30 SE1_NOTCH_A30 [15:0] 0000h R77 (4Dh) SE1_NOTCH_A31 SE1_NOTCH_A31 [15:0] 0000h R78 (4Eh) SE1_NOTCH_A40 SE1_NOTCH_A40 [15:0] 0000h R79 (4Fh) SE1_NOTCH_A41 SE1_NOTCH_A41 [15:0] 0000h R80 (50h) SE1_NOTCH_A50 SE1_NOTCH_A50 [15:0] 0000h R81 (51h) SE1_NOTCH_A51 SE1_NOTCH_A51 [15:0] 0000h R82 (52h) SE1_NOTCH_M10 SE1_NOTCH_M10 [15:0] 0000h R83 (53h) SE1_NOTCH_M11 SE1_NOTCH_M11 [15:0] 1000h R84 (54h) SE1_NOTCH_M20 SE1_NOTCH_M20 [15:0] 0000h R85 (55h) SE1_NOTCH_M21 SE1_NOTCH_M21 [15:0] 1000h R86 (56h) SE1_NOTCH_M30 SE1_NOTCH_M30 [15:0] 0000h R87 (57h) SE1_NOTCH_M31 SE1_NOTCH_M31 [15:0] 1000h R88 (58h) SE1_NOTCH_M40 SE1_NOTCH_M40 [15:0] 0000h R89 (59h) SE1_NOTCH_M41 SE1_NOTCH_M41 [15:0] 1000h R90 (5Ah) SE1_NOTCH_M50 SE1_NOTCH_M50 [15:0] 0000h R91 (5Bh) SE1_NOTCH_M51 SE1_NOTCH_M51 [15:0] R92 (5Ch) SE1_DF1_CONFIG R93 (5Dh) SE1_DF1_L0 SE1_DF1_L0 [15:0] 1000h R94 (5Eh) SE1_DF1_L1 SE1_DF1_L1 [15:0] 0000h R95 (5Fh) SE1_DF1_L2 SE1_DF1_L2 [15:0] 0000h R96 (60h) SE1_DF1_R0 SE1_DF1_R0 [15:0] 1000h R97 (61h) SE1_DF1_R1 SE1_DF1_R1 [15:0] 0000h Rev 4.2 AUX IN1_TO DIFF_T _OUT_ O_OUT ATTEN _ATTE N 0 0 SE1_L SE1_L HPF_R HPF_L _SIGN _SIGN SE_CONFIG [3:0] 0 0 0000h SE1_L SE1_L HPF_R HPF_L _ENA _ENA SE1_LHPF_L [15:0] 0000h SE1_LHPF_R [15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h SE1_3 SE1_3 SE1_3 SE1_3 SE1_3 SE1_3 D_R_SI D_L_SI D_LHP D_LHP D_R_L D_L_L GN GN F_R_E F_L_E HPF_SI HPF_SI NA NA GN GN 0 0 0 0 0 0 0000h 0 0 0 0 0 0 0 SE1_3 SE1_3 D_R_E D_L_E NA NA SE1_N SE1_N OTCH_ OTCH_ R_ENA L_ENA 0000h 0000h 1000h 0 0 0 0 0 SE1_D SE1_D F1_R_ F1_L_E ENA NA 105 0000h WM8944B REG NAME R98 (62h) SE1_DF1_R2 R99 (63h) SE2_HPF_CONFIG R100 (64h) SE2_RETUNE_CONFI G 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SE2_H SE2_H PF_R_ PF_L_ ENA ENA 0000h 0 0 0 0 0 0 SE2_R ETUNE _R_EN A 0000h SE1_DF1_R2 [15:0] DEFAULT 0000h SE2_R ETUNE _L_EN A R101 (65h) SE2_RETUNE_C0 SE2_RETUNE_C0 [15:0] 1000h R102 (66h) SE2_RETUNE_C1 SE2_RETUNE_C1 [15:0] 0000h R103 (67h) SE2_RETUNE_C2 SE2_RETUNE_C2 [15:0] 0000h R104 (68h) SE2_RETUNE_C3 SE2_RETUNE_C3 [15:0] 0000h R105 (69h) SE2_RETUNE_C4 SE2_RETUNE_C4 [15:0] 0000h R106 (6Ah) SE2_RETUNE_C5 SE2_RETUNE_C5 [15:0] 0000h R107 (6Bh) SE2_RETUNE_C6 SE2_RETUNE_C6 [15:0] 0000h R108 (6Ch) SE2_RETUNE_C7 SE2_RETUNE_C7 [15:0] 0000h R109 (6Dh) SE2_RETUNE_C8 SE2_RETUNE_C8 [15:0] 0000h R110 (6Eh) SE2_RETUNE_C9 SE2_RETUNE_C9 [15:0] 0000h R111 (6Fh) SE2_RETUNE_C10 SE2_RETUNE_C10 [15:0] 0000h R112 (70h) SE2_RETUNE_C11 SE2_RETUNE_C11 [15:0] 0000h R113 (71h) SE2_RETUNE_C12 SE2_RETUNE_C12 [15:0] 0000h R114 (72h) SE2_RETUNE_C13 SE2_RETUNE_C13 [15:0] 0000h R115 (73h) SE2_RETUNE_C14 SE2_RETUNE_C14 [15:0] 0000h R116 (74h) SE2_RETUNE_C15 SE2_RETUNE_C15 [15:0] 0000h R117 (75h) SE2_RETUNE_C16 SE2_RETUNE_C16 [15:0] 0000h R118 (76h) SE2_RETUNE_C17 SE2_RETUNE_C17 [15:0] 0000h R119 (77h) SE2_RETUNE_C18 SE2_RETUNE_C18 [15:0] 0000h R120 (78h) SE2_RETUNE_C19 SE2_RETUNE_C19 [15:0] 0000h R121 (79h) SE2_RETUNE_C20 SE2_RETUNE_C20 [15:0] 0000h R122 (7Ah) SE2_RETUNE_C21 SE2_RETUNE_C21 [15:0] 0000h R123 (7Bh) SE2_RETUNE_C22 SE2_RETUNE_C22 [15:0] 0000h R124 (7Ch) SE2_RETUNE_C23 SE2_RETUNE_C23 [15:0] 0000h R125 (7Dh) SE2_RETUNE_C24 SE2_RETUNE_C24 [15:0] 0000h R126 (7Eh) SE2_RETUNE_C25 SE2_RETUNE_C25 [15:0] 0000h R127 (7Fh) SE2_RETUNE_C26 SE2_RETUNE_C26 [15:0] 0000h R128 (80h) SE2_RETUNE_C27 SE2_RETUNE_C27 [15:0] 0000h R129 (81h) SE2_RETUNE_C28 SE2_RETUNE_C28 [15:0] 0000h R130 (82h) SE2_RETUNE_C29 SE2_RETUNE_C29 [15:0] 0000h R131 (83h) SE2_RETUNE_C30 SE2_RETUNE_C30 [15:0] 0000h R132 (84h) SE2_RETUNE_C31 SE2_RETUNE_C31 [15:0] R133 (85h) SE2_5BEQ_CONFIG 0 0 0 R134 (86h) SE2_5BEQ_L10G 0 0 0 R135 (87h) SE2_5BEQ_L32G 0 0 0 R136 (88h) SE2_5BEQ_L4G 0 0 0 0 0 0 0 0 SE2_5BEQ_L1G [4:0] 0 0 0 SE2_5BEQ_L0G [4:0] 0C0Ch SE2_5BEQ_L3G [4:0] 0 0 0 SE2_5BEQ_L2G [4:0] 0C0Ch 0 0 0 SE2_5BEQ_L4G [4:0] 000Ch 0 0 0 0 0000h 0 0 0 0 0 0 0 0 SE2_5 BEQ_L _ENA 0000h R137 (89h) SE2_5BEQ_L0P SE2_5BEQ_L0P [15:0] 00D8h R138 (8Ah) SE2_5BEQ_L0A SE2_5BEQ_L0A [15:0] 0FCAh R139 (8Bh) SE2_5BEQ_L0B SE2_5BEQ_L0B [15:0] 0400h R140 (8Ch) SE2_5BEQ_L1P SE2_5BEQ_L1P [15:0] 01C5h R141 (8Dh) SE2_5BEQ_L1A SE2_5BEQ_L1A [15:0] 1EB5h R142 (8Eh) SE2_5BEQ_L1B SE2_5BEQ_L1B [15:0] F145h R143 (8Fh) SE2_5BEQ_L1C SE2_5BEQ_L1C [15:0] 0B75h 106 Rev 4.2 WM8944B REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R144 (90h) SE2_5BEQ_L2P SE2_5BEQ_L2P [15:0] 0558h R145 (91h) SE2_5BEQ_L2A SE2_5BEQ_L2A [15:0] 1C58h R146 (92h) SE2_5BEQ_L2B SE2_5BEQ_L2B [15:0] F373h R147 (93h) SE2_5BEQ_L2C SE2_5BEQ_L2C [15:0] 0A54h R148 (94h) SE2_5BEQ_L3P SE2_5BEQ_L3P [15:0] 1103h R149 (95h) SE2_5BEQ_L3A SE2_5BEQ_L3A [15:0] 168Eh R150 (96h) SE2_5BEQ_L3B SE2_5BEQ_L3B [15:0] F829h R151 (97h) SE2_5BEQ_L3C SE2_5BEQ_L3C [15:0] 07ADh R152 (98h) SE2_5BEQ_L4P SE2_5BEQ_L4P [15:0] 4000h R153 (99h) SE2_5BEQ_L4A SE2_5BEQ_L4A [15:0] 0564h R154 (9Ah) SE2_5BEQ_L4B SE2_5BEQ_L4B [15:0] R155 (9Bh) SE2_5BEQ_R10G 0 0 0 R156 (9Ch) SE2_5BEQ_R32G 0 0 0 R157 (9Dh) SE2_5BEQ_R4G 0 0 0 SE2_5BEQ_R1G [4:0] SE2_5BEQ_R3G [4:0] 0 0 0 0 0 0559h 0 0 0 SE2_5BEQ_R0G [4:0] 0C0Ch 0 0 0 SE2_5BEQ_R2G [4:0] 0C0Ch 0 0 0 SE2_5BEQ_R4G [4:0] 000Ch R158 (9Eh) SE2_5BEQ_R0P SE2_5BEQ_R0P [15:0] 00D8h R159 (9Fh) SE2_5BEQ_R0A SE2_5BEQ_R0A [15:0] 0FCAh R160 (A0h) SE2_5BEQ_R0B SE2_5BEQ_R0B [15:0] 0400h R161 (A1h) SE2_5BEQ_R1P SE2_5BEQ_R1P [15:0] 01C5h R162 (A2h) SE2_5BEQ_R1A SE2_5BEQ_R1A [15:0] 1EB5h R163 (A3h) SE2_5BEQ_R1B SE2_5BEQ_R1B [15:0] F145h R164 (A4h) SE2_5BEQ_R1C SE2_5BEQ_R1C [15:0] 0B75h R165 (A5h) SE2_5BEQ_R2P SE2_5BEQ_R2P [15:0] 0558h R166 (A6h) SE2_5BEQ_R2A SE2_5BEQ_R2A [15:0] 1C58h R167 (A7h) SE2_5BEQ_R2B SE2_5BEQ_R2B [15:0] F373h R168 (A8h) SE2_5BEQ_R2C SE2_5BEQ_R2C [15:0] 0A54h R169 (A9h) SE2_5BEQ_R3P SE2_5BEQ_R3P [15:0] 1103h R170 (AAh) SE2_5BEQ_R3A SE2_5BEQ_R3A [15:0] 168Eh R171 (ABh) SE2_5BEQ_R3B SE2_5BEQ_R3B [15:0] F829h R172 (ACh) SE2_5BEQ_R3C SE2_5BEQ_R3C [15:0] 07ADh R173 (ADh) SE2_5BEQ_R4P SE2_5BEQ_R4P [15:0] 4000h R174 (AEh) SE2_5BEQ_R4A SE2_5BEQ_R4A [15:0] 0564h R175 (AFh) SE2_5BEQ_R4B SE2_5BEQ_R4B [15:0] 0559h Rev 4.2 107 WM8944B REGISTER BITS BY ADDRESS The complete register map is shown below. The detailed description can be found in the relevant text of the device description. REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R0 (00h) Software Reset/Chip ID 1 15:0 SW_RESET [15:0] 0110_0010 Writing to this register resets all registers to their default _0110_010 state. 0 Reading from this register will indicate device family ID 6264h. Register 00h Software Reset/Chip ID 1 REGISTER BIT LABEL DEFAULT 3:0 CHIP_REV [3:0] 0000 BIT LABEL DEFAULT 12 INPGA_ENA 0 DESCRIPTION REFER TO ADDRESS R1 (01h) Chip ID 2 (Read only) Reading from this register will indicate the Revision ID (Read only). Register 01h Chip ID 2 REGISTER DESCRIPTION REFER TO ADDRESS R2 (02h) Power manage-ment 1 Input PGA Enable 0 = Disabled 1 = Enabled 11 ADCR_ENA 0 Right ADC Enable 0 = Disabled 1 = Enabled ADCR_ENA must be set to 1 when processing right channel data from the Digital Microphone. 10 ADCL_ENA 0 Left ADC Enable 0 = Disabled 1 = Enabled ADCL_ENA must be set to 1 when processing data from the ADC or Digital Microphone. 7 DMIC_ENA 0 Enables Digital Microphone mode 0 = Audio DSP input is from ADC 1 = Audio DSP input is from digital microphone interface When DMIC_ENA = 0, the Digital microphone clock (DMICCLK) is held low. 5 SPK_ 0 Selects 0.9V midrail voltage for speaker output drivers LOWVMID_ 0 = Disabled ENA 1 = Enabled This bit should be enabled if SPKVDD = 1.8V 4 MICB_ENA 0 Microphone Bias Enable 0 = Disabled 1 = Enabled 3 BIAS_ENA 0 Master Bias Enable 0 = Disabled 1 = Enabled 2 VMID_BUF_ 0 VMID Buffer Enable. (The buffered VMID may be applied to disabled input and output pins.) ENA 0 = Disabled 1 = Enabled 1:0 108 VMID_SEL [1:0] 00 VMID Divider Enable and Select Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) Register 02h Power management 1 REGISTER BIT LABEL DEFAULT 14 OUT_ENA 0 DESCRIPTION REFER TO ADDRESS R3 (03h) Power manage-ment 2 LINEOUT enable 0 = Disabled 1 = Enabled 12 SPK_PGA_ 0 Speaker PGA enable 0 = Disabled ENA 1 = Enabled 11 SPKN_ 0 SPKOUTN enable 0 = Disabled SPKVDD_ENA 1 = Enabled Note that SPKOUTN is also controlled by SPKN_OP_ENA. When powering down SPKOUTN, the SPKN_SPKVDD_ENA bit should be reset first. 10 SPKP_ 0 SPKOUTP enable 0 = Disabled SPKVDD_ENA 1 = Enabled Note that SPKOUTP is also controlled by SPKP_OP_ENA. When powering down SPKOUTP, the SPKP_SPKVDD_ENA bit should be reset first 9 SPKN_OP_ 1 SPKOUTN Output Mute 0 = Disable Mute MUTE 1 = Enable Mute 8 SPKP_OP_ 1 SPKOUTP Output Mute 0 = Disable Mute MUTE 1 = Enable Mute 7 SPKN_OP_ 0 SPKOUTN enable 0 = Disabled ENA 1 = Enabled Note that SPKOUTN is also controlled by SPKN_SPKVDD_ENA. When powering up SPKOUTN, the SPKN_OP_ENA bit should be enabled first. 6 SPKP_OP_ 0 SPKOUTP enable 0 = Disabled ENA 1 = Enabled Note that SPKOUTP is also controlled by SPKP_SPKVDD_ENA. When powering up SPKOUTP, the SPKP_OP_ENA bit should be enabled first 4 SPK_MIX_ 1 Speaker PGA Mixer Mute 0 = Disable Mute MUTE 1 = Enable Mute 2 SPK_MIX_ENA 0 Speaker output mixer enable 0 = Disabled 1 = Enabled 0 DAC_ENA 0 DAC Enable 0 = Disabled 1 = Enabled Rev 4.2 109 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS DAC_ENA must be set to 1 when processing data from the DAC or Digital Beep Generator. Register 03h Power management 2 REGISTER BIT LABEL DEFAULT 15:14 DACDATA_ 00 DESCRIPTION REFER TO ADDRESS R4 (04h) Audio Interface DACDAT pull-up / pull-down Enable 00 = no pull-up or pull-down PULL [1:0] 01 = pull-down 10 = pull-up 11 = reserved 13:12 FRAME_PULL [1:0] 00 LRCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 BCLK_PULL [1:0] 00 BCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 9 ADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 8 ADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 6 DAC_SRC 0 DAC Data Source Select 0 = DAC outputs left channel interface data 1 = DAC outputs right channel interface data 5 BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 4 LRCLK_INV 0 LRCLK Polarity / DSP Mode A-B select. Left and I2S modes – LRCLK polarity 0 = Not Inverted 1 = Inverted DSP Mode – Mode A-B select 0 = MSB is available on 2nd BCLK rising edge after LRCLK rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRCLK rising edge (mode B) 3:2 WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - see “Companding” for the selection of 8-bit mode. 1:0 FMT [1:0] 10 Digital Audio Interface Format 00 = Reserved 110 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO DESCRIPTION REFER TO ADDRESS 01 = Left Justified 10 = I2S format 11 = DSP/PCM mode Register 04h Audio Interface REGISTER BIT LABEL DEFAULT ADDRESS R5 (05h) Companding control 15 ADC_DAC_ Digital Audio Interface Loopback Function LOOPBACK 0 = No loopback 1 = Loopback enabled (ADC data is fed directly into DAC data input). 5 LOOPBACK 0 Digital Loopback Function 0 = No loopback 1 = Loopback enabled (DACDAT input is fed through the DSP Core to the ADCDAT output). 3 DAC_COMP 0 DAC Companding Enable 0 = Disabled 1 = Enabled 2 DAC_ 0 DAC Companding Mode 0 = µ-law COMPMODE 1 = A-law 1 ADC_COMP 0 ADC Companding Enable 0 = Disabled 1 = Enabled 0 ADC_ 0 ADC Companding Mode 0 = µ-law COMPMODE 1 = A-law Register 05h Companding control REGISTER BIT LABEL DEFAULT 15 OSC_CLK_ 0 DESCRIPTION REFER TO ADDRESS R6 (06h) Clock Gen control Oscillator Enable 0 = Disabled ENA 1 = Enabled This needs to be set when a timeout clock is required for GPIO input detection 14:13 MCLK_PULL [1:0] 00 MCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 CLKOUT_SEL 0 CLKOUT Source Select 0 = SYSCLK 1 = FLL or MCLK (set by SYSCLK_SRC register) 11:10 CLKOUT_DIV [1:0] 00 CLKOUT Clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 Rev 4.2 111 WM8944B REGISTER BIT LABEL DEFAULT 9 SYSCLK_ENA 0 DESCRIPTION REFER TO ADDRESS SYSCLK Enable 0 = Disabled 1 = Enabled 8 SYSCLK_SRC 1 SYSCLK Source Select 0 = MCLK 1 = FLL output 7:5 SYSCLK_DIV [2:0] 000 SYSCLK Clock divider (Sets the scaling for either the MCLK or FLL clock output, depending on SYSCLK_SRC) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 4 TOCLK_ENA 0 TOCLK Enabled (Enables timeout clock for GPIO level detection) 0 = Disabled 1 = Enabled 3:1 BCLK_DIV [2:0] 011 BCLK Frequency (Master mode) 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 4 011 = SYSCLK / 8 100 = SYSCLK / 16 101 = SYSCLK / 32 110 = reserved 111 = reserved 0 MSTR 0 Digital Audio Interface Mode select 0 = Slave mode 1 = Master mode Register 06h Clock Gen control REGISTER BIT LABEL DEFAULT 15 SYSCLK_ 1 DESCRIPTION REFER TO ADDRESS .R7 (07h) Additional control Selects the SYSCLK / fs ratio 0 = SYSCLK = 256 x fs RATE 1 = SYSCLK = 512 x fs 11 VMID_FAST_ 0 VMID (fast-start) Enable 0 = Disabled START 1 = Enabled 10 VMID_REF_ 0 VMID Source Select 0 = LDO supply (LDOVDD) SEL 1 = LDO output (LDOVOUT) 9 VMID_CTRL 0 VMID Ratio control Sets the ratio of VMID to the source selected by VMID_REF_SEL 0 = 5/11 1 = 1/2 8 112 STARTUP_ 0 Start-Up Bias Enable Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 0 = Disabled BIAS_ENA 1 = Enabled 7 BIAS_SRC 0 Bias Source select 0 = Master bias 1 = Start-Up bias 6:5 VMID_RAMP [1:0] 00 VMID soft start enable / slew rate control 00 = Disabled 01 = Fast soft start 10 = Normal soft start 11 = Slow soft start 4 VMID_ENA 0 VMID Enable 0 = Disabled 1 = Enabled 3:0 SR [3:0] 1101 Audio Sample Rate select 0011 = 8kHz 0100 = 11.025kHz 0101 = 12kHz 0111 = 16kHz 1000 = 22.05kHz 1001 = 24kHz 1011 = 32kHz 1100 = 44.1kHz 1101 = 48kHz Register 07h Additional control REGISTER BIT LABEL DEFAULT 12:11 FLL_CLK_REF_ DIV [1:0] 00 DESCRIPTION REFER TO ADDRESS R8 (08h) FLL Control 1 FLL Clock Reference Divider 00 = MCLK / 1 01 = MCLK / 2 10 = MCLK / 4 11 = MCLK / 8 MCLK (or other input reference) must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired. 10:8 FLL_OUTDIV [2:0] 001 FOUT clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 6 111 = 12 (FOUT = FVCO / FLL_OUTDIV) 7:5 FLL_CTRL_ RATE [2:0] 000 Frequency of the FLL control block 000 = FVCO / 1 (Recommended value) 001 = FVCO / 2 010 = FVCO / 3 Rev 4.2 113 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 011 = FVCO / 4 100 = FVCO / 5 101 = FVCO / 6 110 = FVCO / 7 111 = FVCO / 8 Recommended that this register is not changed from default. 4:2 FLL_FRATIO [2:0] 000 FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 000 recommended for FREF > 1MHz 100 recommended for FREF < 16kHz 011 recommended for all other cases 1 FLL_FRAC 1 Fractional enable 0 = Integer Mode 1 = Fractional Mode Integer mode offers reduced power consumption. Fractional mode offers best FLL performance, provided also that N.K is a non-integer value. 0 FLL_ENA 0 FLL Enable 0 = Disabled 1 = Enabled Register 08h FLL Control 1 REGISTER BIT LABEL 15:0 FLL_K [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R9 (09h) FLL Control 2 0011_0001 Fractional multiply for FREF _0010_011 (MSB = 0.5) 1 Register 09h FLL Control 2 REGISTER BIT LABEL R10 (0Ah) FLL 14:5 FLL_N [9:0] Control 3 3:0 FLL_GAIN [3:0] DEFAULT DESCRIPTION REFER TO ADDRESS 00_0000_1 Integer multiply for FREF 000 (LSB = 1) 0000 Gain applied to error 0000 = x 1 (Recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 114 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS Recommended that this register is not changed from default. Register 0Ah FLL Control 3 REGISTER BIT LABEL DEFAULT 0 MODE_GPIO 0 DESCRIPTION REFER TO ADDRESS R11 (0Bh) GPIO Config CIFMODE/GPIO2 pin configuration 0 = Pin configured as CIFMODE 1 = Pin configured as GPIO2 Note - when this bit is set to 1, it is latched and cannot be reset until Power-Off or Software Reset. Register 0Bh GPIO Config REGISTER BIT LABEL DEFAULT 15 GP1_DIR 1 DESCRIPTION REFER TO ADDRESS R13 (0Dh) GPIO1 Control GPIO1 Pin Direction 0 = Output 1 = Input 14:13 GP1_PULL [1:0] 00 GPIO1 pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 GP1_INT_ 0 GPIO1 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP1_POL=0) or falling edge triggered (if GP1_POL =1) MODE 1 = GPIO interrupt is triggered on rising and falling edges 10 GP1_POL 0 GPIO1 Polarity Select 0 = Non-inverted 1 = Inverted 5 GP1_LVL 0 GPIO1 level. Write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP1_POL is set, the register contains the opposite logic level to the external pin. 3:0 GP1_FN [3:0] 0000 GPIO1 Pin Function Table 62 0000 = Logic Level Input 0001 = Edge Detection Input 0010 = CLKOUT output 0011 = Interupt (IRQ) output 0100 = Reserved 0101 = Reserved 0110 = Reserved 0111 = Temperature flag output 1000 = Reserved 1001 = DMICCLK output 1010 = Logic Level output 1011 = LDO_UV output 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved Rev 4.2 115 WM8944B Register 0Dh GPIO1 Control REGISTER BIT LABEL DEFAULT 15 GP2_DIR 1 DESCRIPTION REFER TO ADDRESS R14 (0Eh) GPIO2 Control GPIO2 Pin Direction 0 = Output 1 = Input 14:13 GP2_PULL [1:0] 10 GPIO2 pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 GP2_INT_ 0 GPIO2 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP2_POL=0) or falling edge triggered (if GP2_POL =1) MODE 1 = GPIO interrupt is triggered on rising and falling edges 10 GP2_POL 0 GPIO2 Polarity Select 0 = Non-inverted 1 = Inverted 5 GP2_LVL 0 GPIO2 level. Write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP2_POL is set, the register contains the opposite logic level to the external pin. 3:0 GP2_FN [3:0] 0000 GPIO2 Pin Function Table 62 0000 = Logic Level Input 0001 = Edge Detection Input 0010 = CLKOUT output 0011 = Interupt (IRQ) output 0100 = Reserved 0101 = Reserved 0110 = Reserved 0111 = Temperature flag output 1000 = Reserved 1001 = DMICCLK output 1010 = Logic Level output 1011 = LDO_UV output 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved Register 0Eh GPIO2 Control REGISTER BIT LABEL DEFAULT 15 TEMP_INT 0 DESCRIPTION REFER TO ADDRESS R16 (10h) System Interrupts (Read only) Thermal Interrupt status (Read only) 0 = Thermal interrupt not set 1 = Thermal interrupt set This bit is latched when set; it is cleared when the register is Read. 13 GP2_INT 0 GPIO2 Interrupt status (Read only) 0 = GPIO2 interrupt not set 1 = GPIO2 interrupt set This bit is latched when set; it is cleared when the register 116 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS is Read. 12 GP1_INT 0 GPIO1 Interrupt status (Read only) 0 = GPIO1 interrupt not set 1 = GPIO1 interrupt set This bit is latched when set; it is cleared when the register is Read. 0 LDO_UV_INT 0 LDO Undervoltage Interrupt (Read only) 0 = LDO Undervoltage interrupt not set 1 = LDO Undervoltage interrupt set This bit is latched when set; it is cleared when the register is Read. Register 10h System Interrupts REGISTER BIT LABEL DEFAULT 15 TEMP_STS 0 DESCRIPTION REFER TO ADDRESS R17 (11h) Status Flags Thermal Sensor status (Read only) 0 = Normal (Read only) 1 = Overtemperature 0 LDO_UV_STS 0 LDO Undervoltage status (Read only) 0 = Normal 1 = Undervoltage Register 11h Status Flags REGISTER BIT LABEL DEFAULT 0 IM_IRQ 1 DESCRIPTION REFER TO ADDRESS R18 (12h) IRQ Config IRQ (GPIO output) Mask 0 = Normal 1 = IRQ output is masked Register 12h IRQ Config REGISTER BIT LABEL DEFAULT 15 IM_TEMP_INT 0 DESCRIPTION REFER TO ADDRESS R19 (13h) System Interrupts Mask Interrupt mask for thermal status 0 = Not masked 1 = Masked 13 IM_GP2_INT 0 Interrupt mask for GPIO2 0 = Not masked 1 = Masked 12 IM_GP1_INT 0 Interrupt mask for GPIO1 0 = Not masked 1 = Masked 0 IM_LDO_UV_ 0 Interrupt mask for LDO Undervoltage status 0 = Not masked INT 1 = Masked Register 13h System Interrupts Mask REGISTER BIT LABEL DEFAULT 2 SPI_OD 0 DESCRIPTION REFER TO ADDRESS R20 (14h) Rev 4.2 Selects CMOS or Open-Drain output (in 3-wire mode only) 117 WM8944B REGISTER BIT LABEL DEFAULT ADDRESS Control Interface DESCRIPTION REFER TO 0 = SDA is normal push CMOS 1 = SDA is Open-Drain 0 AUTO_INC 1 Enables address auto-increment (applies to 2-wire / I2C mode only) 0 = Disabled 1 = Enabled Register 14h Control Interface REGISTER BIT LABEL DEFAULT DAC_ 1 DESCRIPTION REFER TO ADDRESS R21 (15h) DAC 4 DAC Auto-Mute Control 0 = Disabled AUTOMUTE Control 1 1 = Enabled 0 DAC_DATINV 0 DAC Data Invert 0 = DAC output not inverted 1 = DAC output inverted Register 15h DAC Control 1 REGISTER BIT LABEL DEFAULT 4 DAC_VOL_ 1 DESCRIPTION REFER TO ADDRESS R22 (16h) DAC DAC Volume Ramp control 0 = Disabled RAMP Control 2 1 = Enabled 0 DAC_SB_FLT 0 Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode Register 16h DAC Control 2 REGISTER BIT LABEL DEFAULT 8 DAC_MUTE 1 DESCRIPTION REFER TO ADDRESS R23 (17h) DAC digital Vol DAC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 DAC_VOL [7:0] 1100_0000 DAC Digital Volume 0000_0000 = mute Table 27 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB Register 17h Left DAC digital Vol REGISTER BIT LABEL DEFAULT ADC_ 1 DESCRIPTION REFER TO ADDRESS R25 (19h) ADC Control 1 118 8 MUTEALL ADC Digital Mute for All Channels 0 = Disable Mute 1 = Enable Mute on all channels Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT ADCR_ 0 DESCRIPTION REFER TO ADDRESS 1 Right ADC Data Invert 0 = Right ADC output not inverted DATINV 1 = Right ADC output inverted 0 ADCL_DATINV 0 Left ADC Data Invert 0 = ADC output not inverted 1 = ADC output inverted Register 19h ADC Control 1 REGISTER BIT LABEL DEFAULT 6 ADC_HPF_ 0 DESCRIPTION REFER TO ADDRESS R26 (1Ah) ADC Sets the ADC HPF response (1st or 2nd order). 0 = Audio mode (1st order) MODE Control 2 1 = Application mode (2nd order) 5:4 ADC_HPF_SR [1:0] 10 ADC HPF sample frequency range 00 = 8kHz to 12kHz 01 = 16kHz to 24kHz 10 = 32kHz to 48kHz 11 = 88kHz to 96kHz 3:1 ADC_HPF_ 000 High pass filter configuration. Table 11 CUT [2:0] See Table 11 for cut-off frequencies at all supported sample rates. 0 ADC_HPF 1 ADC Digital High Pass Filter Enable 0 = Disabled 1 = Enabled Register 1Ah ADC Control 2 REGISTER BIT LABEL DEFAULT 12 ADC_VU 0 DESCRIPTION REFER TO ADDRESS R27 (1Bh) Left ADC Digital Vol ADC Volume Update Writing a 1 to this bit enables the Left ADC volume to be updated 8 ADCL_MUTE 0 Left ADC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 ADCL_VOL [7:0] 1100_0000 Left ADC Digital Volume 0000_0000 = mute Table 9 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB Register 1Bh Left ADC Digital Vol REGISTER BIT LABEL DEFAULT 12 ADC_VU 0 DESCRIPTION REFER TO ADDRESS R28 (1Ch) Right ADC Rev 4.2 ADC Volume Update Writing a 1 to this bit will cause Left and Right ADC volume 119 WM8944B REGISTER BIT LABEL DEFAULT ADDRESS Digital Vol DESCRIPTION REFER TO to be updated simultaneously 8 ADCR_MUTE 0 Right ADC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 ADCR_VOL [7:0] 1100_0000 Right ADC Digital Volume 0000_0000 = mute Table 9 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB Register 1Ch Right ADC Digital Vol REGISTER BIT LABEL DEFAULT 8 DRC_NG_ENA 0 DESCRIPTION REFER TO ADDRESS R29 (1Dh) DRC DRC Noise Gate Enable 0 = Disabled Control 1 1 = Enabled 7 DRC_ENA 0 DRC Enable 0 = Disabled 1 = Enabled 2 DRC_QR 1 DRC Quick-release Enable 0 = Disabled 1 = Enabled 1 DRC_ 1 DRC Anti-clip Enable 0 = Disabled ANTICLIP 1 = Enabled Register 1Dh DRC Control 1 REGISTER BIT LABEL DEFAULT DRC_NG_ 0110 DESCRIPTION REFER TO ADDRESS R30 (1Eh) DRC Control 2 12:9 MINGAIN [3:0] Minimum gain the DRC can use to attenuate audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 = 36dB 1101 to 1111 = Reserved 120 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT 4:2 DRC_MINGAIN [2:0] 001 DESCRIPTION REFER TO ADDRESS Minimum gain the DRC can use to attenuate audio signals 000 = 0dB 001 = -12dB (default) 010 = -18dB 011 = -24dB 100 = -36dB 101 = Reserved 11X = Reserved 1:0 DRC_ 01 MAXGAIN [1:0] Maximum gain the DRC can use to boost audio signals (dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 36dB Register 1Eh DRC Control 2 REGISTER BIT LABEL DEFAULT 7:4 DRC_ATK [3:0] 0100 DESCRIPTION REFER TO ADDRESS R31 (1Fh) DRC Attack rate relative to the input signal (seconds/6dB) 0000 = Reserved Control 3 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100-1111 = Reserved 3:0 DRC_DCY [3:0] 0010 Decay rate relative to the input signal (seconds/6dB) 0000 = 186ms 0001 = 372ms 0010 = 743ms 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = Reserved Register 1Fh DRC Control 3 REGISTER BIT LABEL DEFAULT 12:8 DRC_KNEE2_ 0_0000 DESCRIPTION REFER TO ADDRESS R32 (20h) DRC Control 4 IP [4:0] Input signal level at the Noise Gate threshold ‘Knee2’. Table 18 00000 = -36dB 00001 = -37.5dB 00010 = -39dB Rev 4.2 121 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC_NG_ENA = 1. 7:2 DRC_KNEE_IP [5:0] 00_0000 Input signal level at the Compressor ‘Knee’. Table 18 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved Register 20h DRC Control 4 REGISTER BIT LABEL DEFAULT 13 DRC_KNEE2_O P_ENA 0 DRC_KNEE2_O P [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS R33 (21h) DRC DRC_KNEE2_OP Enable 0 = Disabled Control 5 1 = Enabled 12:8 Output signal at the Noise Gate threshold ‘Knee2’. Table 18 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC_KNEE2_OP_ENA = 1. 7:3 DRC_KNEE_ 0_0000 Output signal at the Compressor ‘Knee’. Table 18 00000 = 0dB OP [4:0] 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved 2:0 DRC_HI_ 011 Compressor slope (upper region) 000 = 1 (no compression) COMP [2:0] 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved Register 21h DRC Control 5 REGISTER BIT LABEL DEFAULT 3:2 DRC_QR_THR [1:0] 00 DESCRIPTION REFER TO ADDRESS R34 (22h) DRC Control 6 122 DRC Quick-release threshold (crest factor in dB) 00 = 12dB 01 = 18dB Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 10 = 24dB 11 = 30dB 1:0 DRC_QR_DCY [1:0] 00 DRC Quick-release decay rate (seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved Register 22h DRC Control 6 REGISTER BIT LABEL DEFAULT 9:8 DRC_NG_EXP [1:0] 00 DESCRIPTION REFER TO ADDRESS R35 (23h) DRC Noise Gate slope 00 = 1 (no expansion) Control 7 01 = 2 10 = 4 11 = 8 7:5 DRC_LO_COM P [2:0] 000 Compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved 4:0 DRC_INIT 00000 IInitial value at DRC startup 00000 = 0dB 00001 = -3.75dB … (-3.75dB steps) 11111 = -116.25dB Register 23h DRC Control 7 REGISTER BIT LABEL 15:0 DRC_GAIN [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R36 (24h) DRC Status (Read only) 0000_0000 DRC Gain value (Read only). _0000_000 This is the DRC gain, expressed as a voltage multiplier. 0 Fixed point coding, MSB = 64. The first 7 bits are the integer portion; the remaining bits are the fractional part. Register 24h DRC Status REGISTER BIT LABEL DEFAULT 6:3 BEEP_GAIN [3:0] 0000 DESCRIPTION REFER TO ADDRESS R37 (25h) Beep Control 1 Digital Beep Volume Control 0000 = mute 0001 = -83dB 0010 = -77dB … (6dB steps) 1111 = +1dB Rev 4.2 123 WM8944B REGISTER BIT LABEL DEFAULT 2:1 BEEP_RATE [1:0] 01 DESCRIPTION REFER TO ADDRESS Beep Waveform Control 00 = Reserved 01 = 1kHz 10 = 2kHz 11 = 4kHz 0 BEEP_ENA 0 Digital Beep Enable 0 = Disabled 1 = Enabled Note that the DAC and associated signal path needs to be enabled when using the digital beep. Register 25h Beep Control 1 REGISTER BIT LABEL DEFAULT 7 VB_ENA 0 DESCRIPTION REFER TO ADDRESS R38 (26h) Video Buffer Video buffer enable 0 = Disabled 1 = Enabled 6 VB_QBOOST 0 Video buffer filter Q-Boost control 0 = Disabled 1 = Enabled 5 VB_GAIN 0 Video buffer gain 0 = 0dB (=6dB unloaded) 1 = 6dB (=12dB unloaded) 4:2 VB_DISOFF [2:0] 111 Video buffer DC offset control 000 = Reserved 001 = 40mV offset 010 = Reserved 011 = 20mV offset 100 = Reserved 101 = Reserved 110 = Reserved 111 = 0mV offset Note - the specified offset applies to the 0dB gain setting (VB_GAIN=0). When 6dB gain is selected, the DC offset is doubled. 1 VB_PD 0 Video buffer pull-down 0 = pull-down disabled 1 = pull-down enabled 0 VB_CLAMP 0 Enable the clamp between the video input and ground 0 = no clamp 1 = Video buffer input is clamped to ground Register 26h Video Buffer REGISTER BIT LABEL DEFAULT 9 AUX_TO_N_ 0 DESCRIPTION REFER TO ADDRESS R39 (27h) Input ctrl INPGA Input PGA Inverting Input Select 0 = Connected to VMID 1 = Connected to AUX 124 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT 6 MICB_LVL 0 DESCRIPTION REFER TO ADDRESS Microphone Bias Voltage control 0 = 0.9 x LDOVOUT 1 = 0.65 x LDOVOUT 1:0 P_PGA_SEL [1:0] 01 Input PGA Non-Inverting Input Select 00 = Reserved 01 = Connected to IN1/DMICDAT 10 = Connected to AUX 11 = Reserved Register 27h Input ctrl REGISTER BIT LABEL DEFAULT 7 INPGA_ZC 0 DESCRIPTION REFER TO ADDRESS R40 (28h) Input PGA gain ctrl Input PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 6 INPGA_MUTE 1 Input PGA Mute 0 = Disable Mute 1 = Enable Mute 5:0 INPGA_VOL [5:0] 01_0000 Input PGA Volume Table 5 00_0000 = -12dB 00_0001 = -11.25dB … 01_0000 = 0dB ... 11_1111 = +35.25 Register 28h Input PGA gain ctrl REGISTER BIT LABEL DEFAULT 15 THERR_ACT 1 DESCRIPTION REFER TO ADDRESS R42 (2Ah) Output ctrl Thermal Shutdown enable 0 = Disabled 1 = Enabled When THERR_ACT = 1, then an over temperature condition will cause the speaker outputs to be disabled. 13 SPKN_VMID_O P_ENA 0 SPKP_VMID_O P_ENA 0 LINE_VMID_ 0 Buffered VMID to SPKOUTN Enable 0 = Disabled 1 = Enabled 12 Buffered VMID to SPKOUTP Enable 0 = Disabled 1 = Enabled 10 Buffered VMID to LINEOUT Enable 0 = Disabled OP_ENA 1 = Enabled 8 LINE_MUTE 1 LINEOUT Output Mute 0 = Disable Mute 1 = Enable Mute 7 SPKN_DISCH 0 Discharges SPKOUTN output via approx 550 ohm resistor 0 = Not active 1 = Actively discharging SPKOUTN Rev 4.2 125 WM8944B REGISTER BIT LABEL DEFAULT 6 SPKP_DISCH 0 DESCRIPTION REFER TO ADDRESS Discharges SPKOUTP output via approx 550 ohm resistor 0 = Not active 1 = Actively discharging SPKOUTP 4 LINE_DISCH 0 Discharges LINEOUT output via approx 550 ohm resistor 0 = Not active 1 = Actively discharging LINEOUT 1 SPK_VROI 0 Buffered VREF to SPKOUTP / SPKOUTN resistance (Disabled outputs) 0 = approx 20k ohms 1 = approx 1k4 ohms 0 LINE_VROI 0 Buffered VREF to LINEOUT resistance (Disabled output) 0 = approx 20k ohms 1 = approx 1k1 ohms Register 2Ah Output ctrl REGISTER BIT LABEL DEFAULT 10 AUXDIFF_TO_P GA 0 IN1_TO_PGA 0 DESCRIPTION REFER TO ADDRESS R43 (2Bh) SPK mixer control1 Differential AUX/IN1 to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 9 IN1 to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 8 AUX_TO_ 0 AUX to SPKOUTP select 0 = Disabled SPKP 1 = Enabled 7 PGA_TO_ 0 Speaker PGA Mixer to SPKOUTP select 0 = Disabled SPKP 1 = Enabled 6 BYP_TO_PGA 0 Input PGA (ADC bypass) to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 5 MDAC_TO_ 0 Inverted DAC to Speaker PGA Mixer select 0 = Disabled PGA 1 = Enabled 3 DAC_TO_PGA 0 DAC to Speaker PGA Mixer select 0 = Disabled 1 = Enabled 0 AUX_TO_PGA 0 AUX to Speaker PGA Mixer select 0 = Disabled 1 = Enabled Register 2Bh SPK mixer control1 126 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT 9 IN1_TO_SPKN 0 DESCRIPTION REFER TO ADDRESS R44 (2Ch) SPK mixer control2 IN1 to SPKOUTN select 0 = Disabled 1 = Enabled 7 PGA_TO_ 0 Speaker PGA Mixer to SPKOUTN select 0 = Disabled SPKN 1 = Enabled Register 2Ch SPK mixer control2 REGISTER BIT LABEL DEFAULT 10 AUXDIFF_TO_P GA_ATTEN 0 IN1_TO_PGA_A TTEN 0 AUX_TO_ 0 DESCRIPTION REFER TO ADDRESS R45 (2Dh) SPK mixer control3 Differential AUX/IN1 to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation 9 IN1 to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation 8 AUX to SPKOUTP attenuation 0 = 0dB SPKP_ATTEN 1 = -6dB attenuation 7 PGA_TO_ 0 Speaker PGA Mixer to SPKOUTP attenuation 0 = 0dB SPKP_ATTEN 1 = -6dB attenuation 6 BYP_TO_PGA_ ATTEN 0 Input PGA (ADC bypass) to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation 3 DAC_TO_PGA_ ATTEN 0 AUX_TO_PGA_ ATTEN 0 DAC to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation 0 AUX to Speaker PGA Mixer attenuation 0 = 0dB 1 = -6dB attenuation Register 2Dh SPK mixer control3 REGISTER BIT LABEL DEFAULT 9 IN1_TO_SPKN_ ATTEN 0 PGA_TO_ 0 DESCRIPTION REFER TO ADDRESS R46 (2Eh) SPK mixer control4 IN1 to SPKOUTN attenuation 0 = 0dB 1 = -6dB attenuation 7 Speaker PGA Mixer to SPKOUTN attenuation 0 = 0dB SPKN_ATTEN 1 = -6dB attenuation Register 2Eh SPK mixer control4 REGISTER BIT LABEL DEFAULT 7 SPK_ZC 0 DESCRIPTION REFER TO ADDRESS R47 (2Fh) SPK volume ctrl Rev 4.2 Speaker PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 127 WM8944B REGISTER BIT LABEL DEFAULT 6 SPK_PGA_ 1 DESCRIPTION REFER TO ADDRESS Speaker PGA Mute 0 = Disable Mute MUTE 1 = Enable Mute 5:0 SPK_VOL [5:0] 11_1001 Speaker PGA Volume Table 35 00_0000 = -57dB gain 00_0001 = -56dB … 11_1001 = 0dB ... 11_1111 = +6dB Register 2Fh SPK volume ctrl REGISTER BIT LABEL DEFAULT 10 AUXDIFF_TO_O UT 0 IN1_TO_OUT 0 DESCRIPTION REFER TO ADDRESS R49 (31h) Line mixer control 1 Differential AUX/IN1 to Line Output Mixer select 0 = Disabled 1 = Enabled 9 IN1 to Line Output Mixer select 0 = Disabled 1 = Enabled 6 BYP_TO_OUT 0 Input PGA (ADC bypass) to Line Output Mixer select 0 = Disabled 1 = Enabled 5 MDAC_TO_ 0 Inverted DAC to Line Output Mixer select 0 = Disabled OUT 1 = Enabled 3 DAC_TO_OUT 0 DAC to Line Output Mixer select 0 = Disabled 1 = Enabled 0 AUX_TO_OUT 0 AUX to Line Output Mixer select 0 = Disabled 1 = Enabled Register 31h Line mixer control 1 REGISTER BIT LABEL DEFAULT 10 AUXDIFF_TO_O UT_ATTEN 0 IN1_TO_OUT_A TTEN 0 BYP_TO_OUT_ ATTEN 0 DAC_TO_OUT_ ATTEN 0 AUX_TO_OUT_ ATTEN 0 DESCRIPTION REFER TO ADDRESS R51 (33h) Line mixer control 2 Differential AUX/IN1 to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 9 IN1 to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 6 Input PGA (ADC bypass) to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 3 DAC to Line Output Mixer attenuation 0 = 0dB 1 = -6dB attenuation 0 128 AUX to Line Output Mixer attenuation 0 = 0dB Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO DESCRIPTION REFER TO ADDRESS 1 = -6dB attenuation Register 33h Line mixer control 2 REGISTER BIT LABEL DEFAULT 15 LDO_ENA 0 ADDRESS R53 (35h) LDO LDO Enable 0 = Disabled 1 = Enabled 14 LDO_REF_ 0 LDO Voltage reference select 0 = VMID (normal) SEL_FAST 1 = VMID (fast start) This field is only effective when LDO_REF_SEL = 0 13 LDO_REF_ 0 LDO Voltage reference select 0 = VMID SEL 1 = Bandgap 12 LDO_OPFLT 0 LDO Output float 0 = Disabled (Output discharged when disabled) 1 = Enabled (Output floats when disabled) 5 LDO_BIAS_ 0 Bias Source select 0 = Master Bias SRC 1 = Start-Up Bias (Fast) 4:0 LDO_VSEL [4:0] 0_0111 LDO Voltage select Table 38 (Sets the LDO output as a ratio of the selected voltage reference. The voltage reference is set by LDO_REF_SEL.) 00111 = Vref x 1.97 (default) Register 35h LDO REGISTER BIT LABEL DEFAULT 15 BG_ENA 0 DESCRIPTION REFER TO ADDRESS R54 (36h) Bandgap Bandgap Reference Control 0 = Disabled 1 = Enabled 4:0 BG_VSEL [4:0] 0_1010 Bandgap Voltage select Table 38 (Sets the Bnadgap voltage) 00000 = 1.200V … 26.7mV steps 01010 = 1.467V (default) … 01111 = 1.600V 10000 to 11111 = reserved Register 36h Bandgap REGISTER BIT LABEL DEFAULT 3:0 SE_CONFIG [3:0] 0000 DESCRIPTION REFER TO ADDRESS R64 (40h) SE Config Selection DSP Configuration Mode select 0000 = Record mode 0001 = Playback mode 0010 = DSP General mode 1 0011 = DSP General mode 2 Rev 4.2 129 WM8944B Register 40h SE Config Selection REGISTER BIT LABEL DEFAULT 5 SE1_LHPF_R_S IGN 0 SE1_LHPF_L_S IGN 0 SE1_LHPF_R_E NA 0 SE1_LHPF_L_E NA 0 DESCRIPTION REFER TO ADDRESS R65 (41h) SE1_LHPF_ CONFIG SE1_LHPF_R_SIGN 0 : sum internal result (LPF) 1 : sub internal result (HPF) 4 SE1_LHPF_L_SIGN 0 : sum internal result (LPF) 1 : sub internal result (HPF) 1 SE1 Right channel low-pass / high-pass filter enable 0 = Disabled 1 = Enabled 0 SE1 Left channel low-pass / high-pass filter enable 0 = Disabled 1 = Enabled Register 41h SE1_LHPF_CONFIG REGISTER BIT LABEL 15:0 SE1_LHPF_L [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R66 (42h) SE1_LHPF 0000_0000 SE1_LHPF left coefficent _0000_000 0 Register 42h SE1_LHPF REGISTER BIT LABEL 15:0 SE1_LHPF_R [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R67 (43h) SE1_LHPF_ R 0000_0000 SE1_LHPF right channel coefficent _0000_000 0 Register 43h SE1_LHPF_R REGISTER BIT LABEL DEFAULT 9 SE1_3D_R 0 DESCRIPTION REFER TO ADDRESS R68 (44h) SE1_3DCON FIG SE1_3D_R_SIGN 0 : add cross path values _SIGN 1 : sub cross path values 8 SE1_3D_L 0 SE1_3D_L_SIGN 0 : add cross path values _SIGN 1 : sub cross path values 7 SE1_3D_LHPF_ R_ENA 0 SE1_3D_LHPF_ L_ENA 0 SE1_3D_LHPF_R_ENA : 0 : R channel disabled (bypass coeffs applied) 1 : R channel enabled (bank coeffs applied) 6 SE1_3D_LHPF_L_ENA : 0 : L channel disabled (bypass coeffs applied) 1 : L channel enabled (bank coeffs applied) 5 SE1_3D_R_ 0 SE1_3D_R_LHPF_SIGN 0 : sum internal result (LPF) LHPF_SIGN 1 : sub internal result (HPF) 4 SE1_3D_L_ LHPF_SIGN 130 0 SE1_3D_L_LHPF_SIGN 0 : sum internal result (LPF) Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT 1 SE1_3D_R_ 0 DESCRIPTION REFER TO ADDRESS 1 : sub internal result (HPF) SE1 Right channel 3D stereo enhancement filter enable 0 = Disabled ENA 1 = Enabled 0 SE1_3D_L_ 0 SE1 Left channel 3D stereo enhancement filter enable 0 = Disabled ENA 1 = Enabled Register 44h SE1_3D_CONFIG REGISTER BIT LABEL DEFAULT SE1_3D_L_ 000 DESCRIPTION REFER TO ADDRESS R69 (45h) SE1_3D_L 13:11 Sets the number of delay samples: 0000 = 0 DELAY [2:0] 0001 = 1 0010 = 2 0011 = 3 0100 = 4 10:8 SE1_3D_L_ 100 Cut Off Frequency 0000 = 50Hz CUTOFF [2:0] 0001 = 100Hz 0010 = 200Hz 0011 = 400 Hz 0100 = 1KHz 0101 = 2KHz 0110 = 4KHz 0111 = 10KHz 1000 to 1111 = reserved 7:4 SE1_3D_L_ 0000 SE1 3D Left Channel cross gain setting 0000 = -12dB CGAIN [3:0] 0001 = -10.5db ……. 1000= 0dB 1001 to 1111 = reserved 3:0 SE1_3D_L_ 1000 SE1 3D Left Channel forward gain setting 0000 = -12dB FGAIN [3:0] 0001 = -10.5db ……. 1000= 0dB 1001 to 1111 = reserved Register 45h SE1_3D_L REGISTER BIT LABEL DEFAULT 13:11 SE1_3D_R_ 000 DESCRIPTION REFER TO ADDRESS R70 (46h) SE1_3D_R Sets the number of delay samples: 0000 = 0 DELAY [2:0] 0001 = 1 0010 = 2 0011 = 3 0100 = 4 10:8 Rev 4.2 SE1_3D_R_ 100 Cut Off Frequency 131 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 0000 = 50Hz CUTOFF [2:0] 0001 = 100Hz 0010 = 200Hz 0011 = 400 Hz 0100 = 1KHz 0101 = 2KHz 0110 = 4KHz 0111 = 10KHz 1000 to 1111 = reserved 7:4 SE1_3D_R_ 0000 SE1 3D Right Channel cross gain setting 0000 = -12dB CGAIN [3:0] 0001 = -10.5db ……. 1000= 0dB 1001 to 1111 = reserved 3:0 SE1_3D_R_ 1000 SE1 3D Right Channel forward gain setting 0000 = -12dB FGAIN [3:0] 0001 = -10.5db ……. 1000= 0dB 1001 to 1111 = reserved Register 46h SE1_3D_R REGISTER BIT LABEL DEFAULT 1 SE1_NOTCH_R _ENA 0 SE1_NOTCH_L _ENA 0 DESCRIPTION REFER TO ADDRESS R71 (47h) SE1_ 0 = Disabled NOTCH_ CONFIG SE1 Right channel notch filters enable 1 = Enabled 0 SE1 notch filters enable 0 = Disabled 1 = Enabled Register 47h SE1_NOTCH_CONFIG REGISTER BIT LABEL 15:0 SE1_NOTCH_A 10 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R72 (48h) SE1_NOTCH _A10 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 48h SE1_NOTCH_A10 REGISTER BIT LABEL 15:0 SE1_NOTCH_A 11 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R73 (49h) SE1_NOTCH _A11 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 49h SE1_NOTCH_A11 132 Rev 4.2 WM8944B REGISTER BIT LABEL 15:0 SE1_NOTCH_A 20 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R74 (4Ah) SE1_NOTCH _A20 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 4Ah SE1_NOTCH_A20 REGISTER BIT LABEL 15:0 SE1_NOTCH_A 21 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R75 (4Bh) SE1_NOTCH _A21 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 4Bh SE1_NOTCH_A21 REGISTER BIT LABEL 15:0 SE1_NOTCH_A 30 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R76 (4Ch) SE1_NOTCH _A30 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 4Ch SE1_NOTCH_A30 REGISTER BIT LABEL 15:0 SE1_NOTCH_A 31 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R77 (4Dh) SE1_NOTCH _A31 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 4Dh SE1_NOTCH_A31 REGISTER BIT LABEL 15:0 SE1_NOTCH_A 40 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R78 (4Eh) SE1_NOTCH _A40 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 4Eh SE1_NOTCH_A40 REGISTER BIT LABEL 15:0 SE1_NOTCH_A 41 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R79 (4Fh) SE1_NOTCH _A41 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 4Fh SE1_NOTCH_A41 REGISTER BIT LABEL 15:0 SE1_NOTCH_A 50 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R80 (50h) SE1_NOTCH _A50 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 50h SE1_NOTCH_A50 Rev 4.2 133 WM8944B REGISTER BIT LABEL 15:0 SE1_NOTCH_A 51 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R81 (51h) SE1_NOTCH _A51 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 51h SE1_NOTCH_A51 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 10 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R82 (52h) SE1_NOTCH _M10 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 52h SE1_NOTCH_M10 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 11 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R83 (53h) SE1_NOTCH _M11 0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 53h SE1_NOTCH_M11 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 20 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R84 (54h) SE1_NOTCH _M20 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 54h SE1_NOTCH_M20 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 21 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R85 (55h) SE1_NOTCH _M21 0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 55h SE1_NOTCH_M21 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 30 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R86 (56h) SE1_NOTCH _M30 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 56h SE1_NOTCH_M30 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 31 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R87 (57h) SE1_NOTCH _M31 0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 57h SE1_NOTCH_M31 134 Rev 4.2 WM8944B REGISTER BIT LABEL 15:0 SE1_NOTCH_M 40 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R88 (58h) SE1_NOTCH _M40 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 58h SE1_NOTCH_M40 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 41 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R89 (59h) SE1_NOTCH _M41 0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 59h SE1_NOTCH_M41 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 50 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R90 (5Ah) SE1_NOTCH _M50 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 5Ah SE1_NOTCH_M50 REGISTER BIT LABEL 15:0 SE1_NOTCH_M 51 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R91 (5Bh) SE1_NOTCH _M51 0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) notch _0000_000 filter 0 Register 5Bh SE1_NOTCH_M51 REGISTER BIT LABEL DEFAULT 1 SE1_DF1_R 0 DESCRIPTION REFER TO ADDRESS R92 (5Ch) SE1_DF1_ SE1 Right channel DF1 filter enable 0 = Disabled _ENA CONFIG 1 = Enabled 0 SE1_DF1_L 0 SE1 Left channel DF1 filter enable 0 = Disabled _ENA 1 = Enabled Register 5Ch SE1_DF1_CONFIG REGISTER BIT LABEL 15:0 SE1_DF1_L0 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R93 (5Dh) SE1_DF1_ L0 0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) channel _0000_000 DF1 filter 0 Register 5Dh SE1_DF1_L0 REGISTER BIT LABEL 15:0 SE1_DF1_L1 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R94 (5Eh) SE1_DF1_ Rev 4.2 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) channel _0000_000 DF1 filter 135 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO DESCRIPTION REFER TO ADDRESS 0 L1 Register 5Eh SE1_DF1_L1 REGISTER BIT LABEL 15:0 SE1_DF1_L2 [15:0] DEFAULT ADDRESS R95 (5Fh) SE1_DF1_ L2 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) channel _0000_000 DF1 filter 0 Register 5Fh SE1_DF1_L2 REGISTER BIT LABEL 15:0 SE1_DF1_R0 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R96 (60h) SE1_DF1_ R0 0001_0000 Filter coefficients for Signal Enhancement 1 (SE1) right _0000_000 channel DF1 filter 0 Register 60h SE1_DF1_R0 REGISTER BIT LABEL 15:0 SE1_DF1_R1 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R97 (61h) SE1_DF1_ R1 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) right _0000_000 channel DF1 filter 0 Register 61h SE1_DF1_R1 REGISTER BIT LABEL 15:0 SE1_DF1_R2 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R98 (62h) SE1_DF1_ R2 0000_0000 Filter coefficients for Signal Enhancement 1 (SE1) right _0000_000 channel DF1 filter 0 Register 62h SE1_DF1_R2 REGISTER BIT LABEL DEFAULT 1 SE2_HPF_R 0 DESCRIPTION REFER TO ADDRESS R99 (63h) SE2_HPF_ SE2 Right channel High-pass filter enable 0 = Disabled _ENA CONFIG 1 = Enabled 0 SE2_HPF_L 0 SE2 Left channel High-pass filter enable 0 = Disabled _ENA 1 = Enabled Register 63h SE2_HPF_CONFIG REGISTER BIT LABEL DEFAULT 1 SE2_RETUNER __ENA 0 DESCRIPTION REFER TO ADDRESS R100 (64h) SE2_RETUN E_CONFIG 136 SE2 Right channel ReTune filter enable 0 = Disabled 1 = Enabled Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT 0 SE2_RETUNEL __ENA 0 DESCRIPTION REFER TO ADDRESS SE2 Left channel ReTune filter enable 0 = Disabled 1 = Enabled Register 64h SE2_RETUNE_CONFIG REGISTER BIT LABEL 15:0 SE2_RETUNE_ C0 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R101 (65h) SE2_RETUN E_C0 0001_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 65h SE2_RETUNE_C0 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C1 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R102 (66h) SE2_RETUN E_C1 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 66h SE2_RETUNE_C1 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C2 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R103 (67h) SE2_RETUN E_C2 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 67h SE2_RETUNE_C2 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C3 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R104 (68h) SE2_RETUN E_C3 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 68h SE2_RETUNE_C3 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C4 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R105 (69h) SE2_RETUN E_C4 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 69h SE2_RETUNE_C4 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C5 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R106 (6Ah) SE2_RETUN E_C5 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 6Ah SE2_RETUNE_C5 Rev 4.2 137 WM8944B REGISTER BIT LABEL 15:0 SE2_RETUNE_ C6 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R107 (6Bh) SE2_RETUN E_C6 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 6Bh SE2_RETUNE_C6 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C7 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R108 (6Ch) SE2_RETUN E_C7 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 6Ch SE2_RETUNE_C7 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C8 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R109 (6Dh) SE2_RETUN E_C8 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 6Dh SE2_RETUNE_C8 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C9 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R110 (6Eh) SE2_RETUN E_C9 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 6Eh SE2_RETUNE_C9 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C10 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R111 (6Fh) SE2_RETUN E_C10 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 6Fh SE2_RETUNE_C10 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C11 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R112 (70h) SE2_RETUN E_C11 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 70h SE2_RETUNE_C11 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C12 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R113 (71h) SE2_RETUN E_C12 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 71h SE2_RETUNE_C12 138 Rev 4.2 WM8944B REGISTER BIT LABEL 15:0 SE2_RETUNE_ C13 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R114 (72h) SE2_RETUN E_C13 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 72h SE2_RETUNE_C13 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C14 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R115 (73h) SE2_RETUN E_C14 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 73h SE2_RETUNE_C14 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C15 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R116 (74h) SE2_RETUN E_C15 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 74h SE2_RETUNE_C15 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C16 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R117 (75h) SE2_RETUN E_C16 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 75h SE2_RETUNE_C16 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C17 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R118 (76h) SE2_RETUN E_C17 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 76h SE2_RETUNE_C17 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C18 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R119 (77h) SE2_RETUN E_C18 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 77h SE2_RETUNE_C18 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C19 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R120 (78h) SE2_RETUN E_C19 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 78h SE2_RETUNE_C19 Rev 4.2 139 WM8944B REGISTER BIT LABEL 15:0 SE2_RETUNE_ C20 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R121 (79h) SE2_RETUN E_C20 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 79h SE2_RETUNE_C20 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C21 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R122 (7Ah) SE2_RETUN E_C21 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 7Ah SE2_RETUNE_C21 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C22 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R123 (7Bh) SE2_RETUN E_C22 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 7Bh SE2_RETUNE_C22 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C23 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R124 (7Ch) SE2_RETUN E_C23 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 7Ch SE2_RETUNE_C23 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C24 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R125 (7Dh) SE2_RETUN E_C24 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 7Dh SE2_RETUNE_C24 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C25 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R126 (7Eh) SE2_RETUN E_C25 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 7Eh SE2_RETUNE_C25 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C26 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R127 (7Fh) SE2_RETUN E_C26 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 7Fh SE2_RETUNE_C26 140 Rev 4.2 WM8944B REGISTER BIT LABEL 15:0 SE2_RETUNE_ C27 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R128 (80h) SE2_RETUN E_C27 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 80h SE2_RETUNE_C27 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C28 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R129 (81h) SE2_RETUN E_C28 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 81h SE2_RETUNE_C28 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C29 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R130 (82h) SE2_RETUN E_C29 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 82h SE2_RETUNE_C29 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C30 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R131 (83h) SE2_RETUN E_C30 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 83h SE2_RETUNE_C30 REGISTER BIT LABEL 15:0 SE2_RETUNE_ C31 [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R132 (84h) SE2_RETUN E_C31 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) ReTune _0000_000 filter 0 Register 84h SE2_RETUNE_C31 REGISTER BIT LABEL DEFAULT 0 SE2_5BEQ_L_E NA 0 DESCRIPTION REFER TO ADDRESS R133 (85h) SE2_5BEQ_ CONFIG SE2 Left channel 5-band EQ enable 0 = Disabled 1 = Enabled Register 85h SE2_5BEQ_CONFIG REGISTER BIT LABEL DEFAULT 12:8 SE2_5BEQ_ 0_1100 DESCRIPTION REFER TO ADDRESS R134 (86h) SE2_5BEQ_ L10G L1G [4:0] Left Channel Filter Gain1 00000 : -12dB 00001 : -12dB 00010 : -10dB Rev 4.2 141 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved 4:0 SE2_5BEQ_ L0G [4:0] 0_1100 Left Channel Filter Gain0 00000 : -12dB 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved Register 86h SE2_5BEQ_L10G 142 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION 12:8 SE2_5BEQ_ 0_1100 Left Channel Filter Gain3 00000 : -12dB 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved 0_1100 Left Channel Filter Gain2 00000 : -12dB 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved REFER TO ADDRESS R135 (87h) SE2_5BEQ_ L32G L3G [4:0] 4:0 SE2_5BEQ_ L2G [4:0] Register 87h SE2_5BEQ_L32G Rev 4.2 143 WM8944B REGISTER BIT LABEL DEFAULT 4:0 SE2_5BEQ_ 0_1100 DESCRIPTION REFER TO ADDRESS R136 (88h) SE2_5BEQ_ L4G Left Channel Filter Gain4 00000 : -12dB L4G [4:0] 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved Register 88h SE2_5BEQ_L4G REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R137 (89h) SE2_5BEQ_ L0P L0P [15:0] 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) left _1101_100 channel 5-band EQ filter 0 Register 89h SE2_5BEQ_L0P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R138 (8Ah) SE2_5BEQ_ L0A L0A [15:0] 0000_1111 Filter coefficients for Signal Enhancement 2 (SE2) left _1100_101 channel 5-band EQ filter 0 Register 8Ah SE2_5BEQ_L0A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R139 (8Bh) SE2_5BEQ_ L0B L0B [15:0] 0000_0100 Filter coefficients for Signal Enhancement 2 (SE2) left _0000_000 channel 5-band EQ filter 0 Register 8Bh SE2_5BEQ_L0B 144 Rev 4.2 WM8944B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R140 (8Ch) SE2_5BEQ_ L1P L1P [15:0] 0000_0001 Filter coefficients for Signal Enhancement 2 (SE2) left _1100_010 channel 5-band EQ filter 1 Register 8Ch SE2_5BEQ_L1P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R141 (8Dh) SE2_5BEQ_ L1A L1A [15:0] 0001_1110 Filter coefficients for Signal Enhancement 2 (SE2) left _1011_010 channel 5-band EQ filter 1 Register 8Dh SE2_5BEQ_L1A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R142 (8Eh) SE2_5BEQ_ L1B L1B [15:0] 1111_0001 Filter coefficients for Signal Enhancement 2 (SE2) left _0100_010 channel 5-band EQ filter 1 Register 8Eh SE2_5BEQ_L1B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R143 (8Fh) SE2_5BEQ_ L1C L1C [15:0] 0000_1011 Filter coefficients for Signal Enhancement 2 (SE2) left _0111_010 channel 5-band EQ filter 1 Register 8Fh SE2_5BEQ_L1C REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R144 (90h) SE2_5BEQ_ L2P L2P [15:0] 0000_0101 Filter coefficients for Signal Enhancement 2 (SE2) left _0101_100 channel 5-band EQ filter 0 Register 90h SE2_5BEQ_L2P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R145 (91h) SE2_5BEQ_ L2A L2A [15:0] 0001_1100 Filter coefficients for Signal Enhancement 2 (SE2) left _0101_100 channel 5-band EQ filter 0 Register 91h SE2_5BEQ_L2A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R146 (92h) SE2_5BEQ_ L2B L2B [15:0] 1111_0011 Filter coefficients for Signal Enhancement 2 (SE2) left _0111_001 channel 5-band EQ filter 1 Register 92h SE2_5BEQ_L2B Rev 4.2 145 WM8944B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R147 (93h) SE2_5BEQ_ L2C L2C [15:0] 0000_1010 Filter coefficients for Signal Enhancement 2 (SE2) left _0101_010 channel 5-band EQ filter 0 Register 93h SE2_5BEQ_L2C REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R148 (94h) SE2_5BEQ_ L3P L3P [15:0] 0001_0001 Filter coefficients for Signal Enhancement 2 (SE2) left _0000_001 channel 5-band EQ filter 1 Register 94h SE2_5BEQ_L3P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R149 (95h) SE2_5BEQ_ L3A L3A [15:0] 0001_0110 Filter coefficients for Signal Enhancement 2 (SE2) left _1000_111 channel 5-band EQ filter 0 Register 95h SE2_5BEQ_L3A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R150 (96h) SE2_5BEQ_ L3B L3B [15:0] 1111_1000 Filter coefficients for Signal Enhancement 2 (SE2) left _0010_100 channel 5-band EQ filter 1 Register 96h SE2_5BEQ_L3B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R151 (97h) SE2_5BEQ_ L3C L3C [15:0] 0000_0111 Filter coefficients for Signal Enhancement 2 (SE2) left _1010_110 channel 5-band EQ filter 1 Register 97h SE2_5BEQ_L3C REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R152 (98h) SE2_5BEQ_ L4P L4P [15:0] 0100_0000 Filter coefficients for Signal Enhancement 2 (SE2) left _0000_000 channel 5-band EQ filter 0 Register 98h SE2_5BEQ_L4P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R153 (99h) SE2_5BEQ_ L4A L4A [15:0] 0000_0101 Filter coefficients for Signal Enhancement 2 (SE2) left _0110_010 channel 5-band EQ filter 0 Register 99h SE2_5BEQ_L4A 146 Rev 4.2 WM8944B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R154 (9Ah) SE2_5BEQ_ L4B L4B [15:0] 0000_0101 Filter coefficients for Signal Enhancement 2 (SE2) left _0101_100 channel 5-band EQ filter 1 Register 9Ah SE2_5BEQ_L4B REGISTER BIT LABEL DEFAULT 12:8 SE2_5BEQ_ 0_1100 DESCRIPTION REFER TO ADDRESS R155 (9Bh) SE2_5BEQ_ R10G Right Channel Filter Gain1 00000 : -12dB R1G [4:0] 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved When the right channel 5BEQ filter is disabled the gains for each of the frequency bands must be set to 0dB. 4:0 SE2_5BEQ_ R0G [4:0] 0_1100 Right Channel Filter Gain0 00000 : -12dB 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB Rev 4.2 147 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved When the right channel 5BEQ filter is disabled the gains for each of the frequency bands must be set to 0dB. Register 9Bh SE2_5BEQ_R10G REGISTER BIT LABEL DEFAULT 12:8 SE2_5BEQ_ 0_1100 DESCRIPTION REFER TO ADDRESS R156 (9Ch) SE2_5BEQ_ R32G Right Channel Filter Gain3 00000 : -12dB R3G [4:0] 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : ReservedWhen the right channel 5BEQ filter is disabled the gains for each of the frequency bands must be set to 0dB. 4:0 SE2_5BEQ_ R2G [4:0] 0_1100 Right Channel Filter Gain2 00000 : -12dB 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 148 Rev 4.2 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB 11000 : 12dB 11001 to 11111 : Reserved When the right channel 5BEQ filter is disabled the gains for each of the frequency bands must be set to 0dB. Register 9Ch SE2_5BEQ_R32G REGISTER BIT LABEL DEFAULT 4:0 SE2_5BEQ_ 0_1100 DESCRIPTION REFER TO ADDRESS R157 (9Dh) SE2_5BEQ_ R4G R4G [4:0] Right Channel Filter Gain4 00000 : -12dB 00001 : -12dB 00010 : -10dB 00011 : -9dB 00100 : -8dB 00101 : -7dB 00110 : -6dB 00111 : -5dB 01000 : -4dB 01001 : -3dB 01010 : -2dB 01011 : -1dB 01100 : 0dB 01101 : 1dB 01110 : 2dB 01111 : 3dB 10000 : 4dB 10001 : 5dB 10010 : 6dB 10011 : 7dB 10100 : 8dB 10101 : 9dB 10110 : 10dB 10111 : 11dB Rev 4.2 149 WM8944B REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 11000 : 12dB 11001 to 11111 : Reserved When the right channel 5BEQ filter is disabled the gains for each of the frequency bands must be set to 0dB. Register 9Dh SE2_5BEQ_R4G REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R158 (9Eh) SE2_5BEQ_ R0P R0P [15:0] 0000_0000 Filter coefficients for Signal Enhancement 2 (SE2) right _1101_100 channel 5-band EQ filter 0 Register 9Eh SE2_5BEQ_R0P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R159 (9Fh) SE2_5BEQ_ R0A R0A [15:0] 0000_1111 Filter coefficients for Signal Enhancement 2 (SE2) right _1100_101 channel 5-band EQ filter 0 Register 9Fh SE2_5BEQ_R0A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R160 (A0h) SE2_5BEQ_ R0B R0B [15:0] 0000_0100 Filter coefficients for Signal Enhancement 2 (SE2) right _0000_000 channel 5-band EQ filter 0 Register A0h SE2_5BEQ_R0B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R161 (A1h) SE2_5BEQ_ R1P R1P [15:0] 0000_0001 Filter coefficients for Signal Enhancement 2 (SE2) right _1100_010 channel 5-band EQ filter 1 Register A1h SE2_5BEQ_R1P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R162 (A2h) SE2_5BEQ_ R1A R1A [15:0] 0001_1110 Filter coefficients for Signal Enhancement 2 (SE2) right _1011_010 channel 5-band EQ filter 1 Register A2h SE2_5BEQ_R1A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R163 (A3h) SE2_5BEQ_ R1B R1B [15:0] 1111_0001 Filter coefficients for Signal Enhancement 2 (SE2) right _0100_010 channel 5-band EQ filter 1 Register A3h SE2_5BEQ_R1B 150 Rev 4.2 WM8944B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R164 (A4h) SE2_5BEQ_ R1C R1C [15:0] 0000_1011 Filter coefficients for Signal Enhancement 2 (SE2) right _0111_010 channel 5-band EQ filter 1 Register A4h SE2_5BEQ_R1C REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R165 (A5h) SE2_5BEQ_ R2P R2P [15:0] 0000_0101 Filter coefficients for Signal Enhancement 2 (SE2) right _0101_100 channel 5-band EQ filter 0 Register A5h SE2_5BEQ_R2P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R166 (A6h) SE2_5BEQ_ R2A R2A [15:0] 0001_1100 Filter coefficients for Signal Enhancement 2 (SE2) right _0101_100 channel 5-band EQ filter 0 Register A6h SE2_5BEQ_R2A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R167 (A7h) SE2_5BEQ_ R2B R2B [15:0] 1111_0011 Filter coefficients for Signal Enhancement 2 (SE2) right _0111_001 channel 5-band EQ filter 1 Register A7h SE2_5BEQ_R2B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R168 (A8h) SE2_5BEQ_ R2C R2C [15:0] 0000_1010 Filter coefficients for Signal Enhancement 2 (SE2) right _0101_010 channel 5-band EQ filter 0 Register A8h SE2_5BEQ_R2C REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R169 (A9h) SE2_5BEQ_ R3P R3P [15:0] 0001_0001 Filter coefficients for Signal Enhancement 2 (SE2) right _0000_001 channel 5-band EQ filter 1 Register A9h SE2_5BEQ_R3P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R170 (Aah) SE2_5BEQ_ R3A R3A [15:0] 0001_0110 Filter coefficients for Signal Enhancement 2 (SE2) right _1000_111 channel 5-band EQ filter 0 Register Aah SE2_5BEQ_R3A Rev 4.2 151 WM8944B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R171 (Abh) SE2_5BEQ_ R3B R3B [15:0] 1111_1000 Filter coefficients for Signal Enhancement 2 (SE2) right _0010_100 channel 5-band EQ filter 1 Register Abh SE2_5BEQ_R3B REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R172 (Ach) SE2_5BEQ_ R3C R3C [15:0] 0000_0111 Filter coefficients for Signal Enhancement 2 (SE2) right _1010_110 channel 5-band EQ filter 1 Register Ach SE2_5BEQ_R3C REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R173 (Adh) SE2_5BEQ_ R4P R4P [15:0] 0100_0000 Filter coefficients for Signal Enhancement 2 (SE2) right _0000_000 channel 5-band EQ filter 0 Register Adh SE2_5BEQ_R4P REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R174 (Aeh) SE2_5BEQ_ R4A R4A [15:0] 0000_0101 Filter coefficients for Signal Enhancement 2 (SE2) right _0110_010 channel 5-band EQ filter 0 Register Aeh SE2_5BEQ_R4A REGISTER BIT LABEL 15:0 SE2_5BEQ_ DEFAULT DESCRIPTION REFER TO ADDRESS R175 (Afh) SE2_5BEQ_ R4B R4B [15:0] 0000_0101 Filter coefficients for Signal Enhancement 2 (SE2) right _0101_100 channel 5-band EQ filter 1 Register Afh SE2_5BEQ_R4B 152 Rev 4.2 WM8944B DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN +/- 0.05dB 0 TYP MAX UNIT ADC Filter Passband 0.454 fs -6dB 0.5fs Passband Ripple +/- 0.05 Stopband dB 0.546s Stopband Attenuation f > 0.546 fs -60 +/- 0.06dB 0 dB DAC Normal Filter Passband 0.454 fs -6dB Passband Ripple 0.5 fs 0.454 fs +/- 0.06 Stopband dB 0.546 fs Stopband Attenuation F > 0.546 fs -50 dB DAC Sloping Stopband Filter Passband +/- 0.06dB 0 0.25 fs +/- 1dB 0.25 fs 0.454 fs -6dB Passband Ripple 0.5 fs 0.25 fs +/- 0.06 Stopband 1 0.546 fs Stopband 1 Attenuation f > 0.546 fs -60 Stopband 2 dB 0.7 fs Stopband 2 Attenuation f > 0.7 fs 1.4 fs -85 Stopband 3 dB 0.7 fs dB 1.4 fs Stopband 3 Attenuation F > 1.4 fs -55 DAC FILTERS dB ADC FILTERS Mode Group Delay Mode Group Delay Normal 16.5 / fs Normal 16.5 / fs Sloping Stopband 18 / fs TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region Notes: 1. The Group Delays are quoted with the DSP SE1, SE2, and SE3 filters disabled. Enabling the DSP SE1, SE2, and SE3 filters will increase the Group Delay Rev 4.2 153 WM8944B ADC FILTER RESPONSE ADC 0 -50 -100 -150 -200 0 20k 40k 60k 80k 100k 120k 140k 160k 180k Figure 44 ADC Frequency Response up to 4 x fs. (Sample rate, fs = 48kHz) ADC 30m 20m 10m 0m -10m -20m -30m -40m 0 5k 10k 15k 20k Figure 45 ADC Pass Band Frequency Response up to fs/2. (Sample rate, fs = 48kHz) 154 Rev 4.2 WM8944B ADC HIGHPASS FILTER RESPONSE 0 Audio -5 -10 -15 -20 1 10 0.1K Figure 46 ADC High Pass Filter Frequency Response for the Hi-Fi Mode (Sample rate, fs = 48kHz) Apps0 0 Apps1 Apps2 Apps3 Apps4 -5 Apps5 Apps6 Apps7 -10 -15 -20 10 0.1K 1K Figure 47 ADC High Pass Filter Frequency Response for the Application Mode (Sample rate, fs = 48kHz) Rev 4.2 155 WM8944B DAC FILTER RESPONSE 48k 0 -50 -100 -150 -200 0 20k 40k 60k 80k 100k 120k 140k 160k 180k Figure 48 DAC Frequency Response up to 4 x fs (Sample rate, fs = 32k to 48kHz) 24k 0 -50 -100 -150 -200 0 10k 20k 30k 40k 50k 60k 70k 80k 90k Figure 49 DAC Frequency Response up to 4 x fs (Sample rate, fs = 16k to 24kHz) 156 Rev 4.2 WM8944B 12k 0 -50 -100 -150 -200 0 10k 20k 30k 40k Figure 50 DAC Frequency Response up to 4 x fs (Sample rate, fs = 8k to 12kHz) 12k 24k 40m 48k 20m 0m -20m -40m -60m 0 5k 10k 15k 20k Figure 51 DAC Pass Band Frequency Response up to fs/2 (Sample rate, fs = 8k to 12kHz, 16k to 24kHz, 32k to 48kHz) Rev 4.2 157 WM8944B VIDEO BUFFER LOWPASS FILTER RESPONSE Figure 52 Video Buffer Lowpass Filter Frequency Response Gain=0dB 158 Rev 4.2 WM8944B APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS AUDIO INPUT PATHS The WM8944B provides up to 2 analogue audio inputs (including the auxiliary input AUX). Each of these inputs is referenced to the internal DC reference, VMID. A DC blocking capacitor is required for each input pin used in the target application. The choice of capacitor is determined by the filter that is formed between that capacitor and the input impedance of the input pin. The circuit is illustrated in Figure 53. (Note that capacitors are not required on any unused audio input.) AUX IN1/ DMICDAT Fc = 1 2 p RC + PGA - Fc = high pass 3dB cut-off frequency Figure 53 Audio Input Path DC Blocking Capacitor When the input impedance is known, and the cut-off frequency is known, then the minimum capacitor value may be derived easily. For practical use, a 1F capacitance for all audio inputs can be recommended for most cases. Tantalum electrolytic capacitors are particularly suitable as they offer high stability in a small package size. Ceramic equivalents are a cost effective alternative to the superior tantalum packages, but care must be taken to ensure the desired capacitance is maintained at the LDOVOUT operating voltage. Also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to electrical signals. This is particularly problematic for microphone input paths where a large signal gain is required. A single capacitor is required for a line input or single-ended microphone connection. In the case of a differential microphone connection, a DC blocking capacitor is required on both input pins. LINE OUTPUT PATHS The WM8944B provides three outputs (LINEOUT, SPKOUTP and SPKOUTN). Each of these outputs is referenced to the internal DC reference, VMID. In any case where a line output is used in a singleended configuration (i.e. referenced to GND), a DC blocking capacitor is required in order to remove the DC bias. In the case where a pair of line outputs is configured as a BTL differential pair, then the DC blocking capacitor should be omitted. The choice of capacitor is determined from the filter that is formed between the capacitor and the load impedance. A 1F capacitance would be a suitable choice for a line load. Tantalum electrolytic capacitors are again particularly suitable but ceramic equivalents are a cost effective alternative. Care must be taken to ensure the desired capacitance is maintained at the appropriate operating voltage. WM8944B LINEOUT SPKOUTP SPKOUTN 1 uF 1 uF 1 uF GND GND = 0V Figure 54 DC-blocking Components for Line Output Rev 4.2 159 WM8944B BTL SPEAKER OUTPUT CONNECTION The BTL speaker output connection is a differential mode of operation. The loudspeaker may be connected directly across the SPKOUTP and SPKOUTN pins. No additional external components are required in this case. POWER SUPPLY DECOUPLING Electrical coupling exists particularly in digital logic systems where switching in one sub-system causes fluctuations on the power supply. This effect occurs because the inductance of the power supply acts in opposition to the changes in current flow that are caused by the logic switching. The resultant variations (or ‘spikes’) in the power supply voltage can cause malfunctions and unintentional behavior in other components. A decoupling (or ‘bypass’) capacitor can be used as an energy storage component which will provide power to the decoupled circuit for the duration of these power supply variations, protecting it from malfunctions that could otherwise arise. Coupling also occurs in a lower frequency form when ripple is present on the power supply rail caused by changes in the load current or by limitations of the power supply regulation method. In audio components such as the WM8944B, these variations can alter the performance of the signal path, leading to degradation in signal quality. A decoupling (or ‘bypass’) capacitor can be used to filter these effects, by presenting the ripple voltage with a low impedance path that does not affect the circuit to be decoupled. These coupling effects are addressed by placing a capacitor between the supply rail and the corresponding ground reference. In the case of systems comprising multiple power supply rails, decoupling should be provided on each rail. The recommended power supply decoupling capacitors for WM8944B are listed below in Table 73. POWER SUPPLY DECOUPLING CAPACITOR DCVDD, DBVDD, LDOVDD, SPKVDD 4.7F ceramic LDOVOUT 2.2F ceramic VMIDC 4.7F ceramic Table 73 Power Supply Decoupling Capacitors All decoupling capacitors should be placed as close as possible to the WM8944B device. The connection between GND, the LDOVOUT decoupling capacitor and the main system ground should be made at a single point as close as possible to the GND ball of the WM8944B. The VMIDC capacitor is not, technically, a decoupling capacitor. However, it does serve a similar purpose in filtering noise on the VMID reference. The connection between GND, the VMID decoupling capacitor and the main system ground should be made at a single point as close as possible to the GND ball of the WM8944B. Due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. For most application the use of ceramic capacitors with capacitor dielectric X5R is recommended. 160 Rev 4.2 WM8944B MICROPHONE BIAS CIRCUIT The WM8944B is designed to interface easily with electret microphones. These may be connected in single-ended or differential configurations. The single-ended method allows greater capability for the connection of multiple audio sources simultaneously, whilst the differential method provides better performance due to its rejection of common-mode noise. In either configuration, the microphone requires a bias current (electret condenser microphones) or voltage supply (silicon microphones), which can be provided by MICBIAS. This reference is generated by an output-compensated amplifier, which requires an external capacitor in order to guarantee accuracy and stability. The recommended capacitance is 4.7F, although it may be possible to reduce this to 1F if the analogue supply (LDOVOUT) is not too noisy. A ceramic type is a suitable choice here, providing that care is taken to choose a component that exhibits this capacitance at the intended MICBIAS voltage. Note that the MICBIAS voltage may be adjusted using register control to suit the requirements of the microphone. Also note the WM8944B supports a maximum current of 3mA. If more than one microphone is connected to the MICBIAS, then combined current must not exceed 3mA. A current-limiting resistor is also required when using an electret condenser microphone (ECM). The resistance should be chosen according to the minimum operating impedance of the microphone and MICBIAS voltage so that the maximum bias current of the WM8944B is not exceeded. Cirrus Logic recommends a 2.2k current limiting resistor as it provides compatibility with a wide range of microphone models. The recommended connections for single-ended and differential microphone modes are illustrated in Figure 55 and Figure 56. MICBIAS 2k2 1uF AUX - IN1/ DMICDAT + 4.7uF PGA MIC GND Figure 55 Single-Ended Microphone Connection MICBIAS 2k2 1uF AUX MIC 1uF - IN1/ DMICDAT + 4.7uF PGA GND Figure 56 Pseudo-Differential Microphone Connection Rev 4.2 161 WM8944B VIDEO BUFFER COMPONENTS External components are required for the Video Buffer. In a typical application, RLOAD = 75, RSOURCE = 75, RREF = 187. See “Video Buffer” for details of alternative components under different load impedance conditions. LDOVDD VIDEO BUFFER 6dB / 12dB (unloaded) 0dB / 6dB (fully loaded) TV in VBIN LPF VBOUT clamp RLOAD VBREF RSOURCE RREF RREF = 187 ohms RSOURCE = 75 ohms RLOAD = 75 ohms Figure 57 Typical Components for Video Buffer 162 Rev 4.2 WM8944B RECOMMENDED EXTERNAL COMPONENTS DIAGRAM Figure 58 provides a summary of recommended external components for WM8944B. Note that the actual requirements may differ according to the specific target application. Figure 58 WM8944B Recommended External Components Diagram PCB LAYOUT CONSIDERATIONS Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce and resistive voltage losses. All external components should be placed as close to the WM8944B device as possible, with current loop areas kept as small as possible. Rev 4.2 163 WM8944B PACKAGE DIMENSIONS B: 25 BALL W-CSP PACKAGE 2.410 X 2.410 X 0.7mm BODY, 0.50 mm BALL PITCH 2 g DM080.A 6 D A DETAIL 1 A2 5 3 4 2 1 3 A1 CORNER A B C E1 e E 5 D E 2X A1 4 e D1 Z 2X 0.10 Z 0.10 Z TOP VIEW BOTTOM VIEW 1 f1 SOLDER BALL f2 h DETAIL 1 Symbols A A1 A2 D D1 E E1 e f1 MIN 0.615 0.219 0.361 2.380 2.380 Dimensions (mm) NOM MAX 0.7 0.785 0.244 0.269 0.411 0.386 2.440 2.410 2.00 BSC 2.440 2.410 2.00 BSC 0.500 BSC NOTE 5 Bump centre to die edge Bump centre to die edge f2 0.190 min 0.190 min g 0.035 0.070 0.105 h 0.267 0.314 0.361 NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING. 3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. 164 Rev 4.2 WM8944B IMPORTANT NOTICE Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. 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Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, SoundClear, WISCE, and ReTune are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners. Copyright © 2010–2016 Cirrus Logic, Inc. All rights reserved. Rev 4.2 165 WM8944B REVISION HISTORY DATE REV 08/10/10 4.0 DESCRIPTION OF CHANGES PAGE Product Status updated to Production Data Added comment about ADC volume being in digital filter block Added comment about DAC volume being in digital filter block Updated Notch Filter plots CHANGED BY BC 28 48 34-35 Added note about DAC_VOL_RAMP rate 48 Input PGA to ADC THD max changed from -75dB 10 24/06/11 4.1 Updated Input resistance for Analogue inputs (IN1, AUX) 10 JJ 06/09/11 4.2 Default value (0) corrected in Register R42 (2Ah) bit [9]. 100 PH 26/06/12 4.2 Noted the notch filter is not usable below 120Hz 01/03/16 4.2 Correction to recommended power-up / power-down sequences 166 PH 102-103 PH Rev 4.2