NSC MM74HC283N

MM54HC283/MM74HC283
4-Bit Binary Adder with Fast Carry
General Description
Features
This full adder performs the addition of two 4-bit binary numbers utilizing advanced silicon-gate CMOS technology. The
sum (R) outputs are provided for each bit and the resultant
carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation.
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion. All inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Y
Y
Y
Y
Y
Full-carry look-ahead across the four bits
Systems achieve partial look-ahead performance
with the economy of ripple carry
Wide supply range: 2V to 6V
Low quiescent power consumption: 8 mA at 25§ C
Low input current: 1 mA maximum
Connection Diagram
Dual-In-Line Package
TL/F/5332 – 1
Top View
Order Number MM54HC283 or MM74HC283
C1995 National Semiconductor Corporation
TL/F/5332
RRD-B30M105/Printed in U. S. A.
MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry
January 1988
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
b 1.5 to VCC a 1.5V
Operating Temp. Range (TA)
MM74HC
MM54HC
b 0.5 to VCC a 1.5V
g 20 mA
g 25 mA
Min
2
Max
6
Units
V
0
VCC
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr, tf)
VCC e 2.0V
VCC e 4.5V
VCC e 6.0V
g 50 mA
b 65§ C to a 150§ C
600 mW
500 mW
(Soldering 10 seconds)
260§ C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay From C0 to R1 or R2
18
27
ns
tPHL, tPLH
Maximum Propagation
Delay From C0 to R3
18
27
ns
tPHL, tPLH
Maximum Propagation
Delay From C0 to R4
20
30
ns
tPHL, tPLH
Maximum Propagation
Delay From A1 or B1 to R1
17
26
ns
tPHL, tPLH
Maximum Propagation
Delay From C0 to C4
22
32
ns
tPHL, tPLH
Maximum Propagation
Delay From A1 or B1 to C4
22
32
ns
Symbol
Parameter
tPHL, tPLH
Conditions
AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
Typ
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
tPHL, tPLH
Maximum Propagation
Delay From C0 to R1 or R2
2.0V
4.5V
6.0V
60
21
18
150
30
26
188
37
32
225
45
39
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay From C0 to R3
2.0V
4.5V
6.0V
60
21
18
150
30
26
188
37
32
225
45
39
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay From C0 to R4
2.0V
4.5V
6.0V
65
24
19
162
34
28
202
43
35
243
51
42
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay From A1 or B1 to R1
2.0V
4.5V
6.0V
60
22
18
150
33
27
188
41
34
225
50
41
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay From C0 to C4
2.0V
4.5V
6.0V
70
26
21
175
39
32
219
49
40
263
59
46
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay From A1 or B1 to C4
2.0V
4.5V
6.0V
70
26
21
175
39
32
219
49
40
263
59
46
ns
ns
ns
tTHL, tTLH
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
28
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CIN
Maximum Input
Capacitance
6
10
10
10
pF
CPD
Power Dissipation
Capacitance (Note 5)
150
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption,
IS e CPD VCC f a ICC.
3
pF
Truth Table
Output
When
C0 e L
Input
When
C0 e H
When
C2 e L
When
C2 e H
A1 A3 B1 B3 A2 A4 B2 B4 R1 R3 R2 R4 C2 C4 R1 R3 R2 R4 C2 C4
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
L
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
H e high level, L e low level
Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs R1 and R2 and the value of the
internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs R3, R4, and C4
4
Logic Diagram
’HC283
TL/F/5332 – 2
5
MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry
Physical Dimensions inches (millimeters)
Order Number MM54HC283J or MM74HC283J
NS Package J16A
Order Number MM74HC283N
NS Package N16E
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