LP5552 PWI 2.0 and PowerWise® Technology Compliant Energy Management Unit General Description Features The LP5552 is a PWI™ 2.0 compliant Energy Management Unit (EMU) for reducing power consumption in low-power, portable applications. The LP5552 contains 2 advanced, digitally controlled switching regulators for supplying variable voltages to a SoC or processor. The device also incorporates 5 programmable low-dropout, low-noise linear regulators for powering I/O, peripheral logic blocks, auxiliary system functions, and maintaining memory retention (dual-domains) in shutdown-mode. The device is controlled via the high-speed serial PWI 2.0 open-standard interface. The LP5552 operates cooperatively with PowerWise® technology-compatible processors to optimize supply voltages adaptively (AVS - Adaptive Voltage Scaling) over process and temperature variations. It also supports dynamic voltage scaling (DVS) using frequency/voltage pairs from pre-characterized lookup tables. ■ High-efficiency PowerWise Technology Adaptive Voltage Key Specifications • 2.7V to 4.8V Input Voltage Range • ±2% (typical) Output Voltage Accuracy Programmable DC/DC Buck Converters • 800mA Output Current per Switcher • Up to 88% Switcher Efficiency • Digitally programmable from 0.6V — 1.235V Programmable LDOs • Five digitally programmable LDOs © 2008 National Semiconductor Corporation 202103 ■ ■ ■ ■ ■ Scaling for intelligent energy management in AVS and DVS environments PWI 2.0 open standard interface for system-level power management Two digitally programmable 3.6MHz buck regulators to power dual-voltage domains Five programmable LDOs for system functions such as: — PLL/Clock Generation — I/O — Memory Retention Internal soft start Variable regulator power up sequencing Applications ■ ■ ■ ■ ■ GSM/GPRS/EDGE & UMTS cellular handsets Hand-held radios PDAs Battery-powered devices Portable instruments www.national.com LP5552 PWI 2.0 and PowerWise® Technology Compliant Energy Management Unit May 20, 2008 LP5552 System Diagram 20210301 www.national.com 2 LP5552 Connection Diagrams and Package Mark Information 20210302 LP5552 Pinout — Top View Note: The actual physical placement of the package marking will vary from part to part. The package markings “XYTT” designate assembly and manufacturing information. "XY" is a date code and "TT" is a NSC internal code for die traceability. Both will vary considerably. "SLKB" is an internal code that identifies the LP5552. 20210307 LP5552 Package Marking (The diamond denotes pin A1.) Ordering Information Order Number Package marking Supplied As LP5552TL/NOPB SLKB 250 units Tape and Reel LP5552TLX/NOPB SLKB 3000 units Tape and Reel 3 www.national.com LP5552 Pin Descriptions Pin # Pin Name I/O Type Function E2 DVDD1 P P Power supply voltage input for digital. Connect to VIN. E6 DVDD2 P P Power supply voltage input for digital, LDO2, and LDO5. Connect to VIN. B6 AVDD1 P P Power supply voltage input for analog, switching regulator #1, and LDO3. Connect to VIN. B1 AVDD2 P P Power supply voltage input for analog, switching regulator #2, and LDO4. Connect to VIN. D1 AVDD3 P P Power supply voltage input for analog, and LDO1. Connect to VIN. A6 PVDD1 P P Power supply voltage input to internal PFET of switching regulator #1. Connect to VIN. A1 PVDD2 P P Power supply voltage input to internal PFET of switching regulator #2. Connect to VIN. E4 DGND1 G G Digital Ground. Connect to system Ground. F4 DGND2 G G Digital Ground. Connect to system Ground. B4 AGND1 G G Analog Ground. Connect to system Ground. B3 AGND2 G G Analog Ground. Connect to system Ground. A4 PGND1 G G Power Ground. Connect to system Ground. A3 PGND2 G G Power Ground. Connect to system Ground. F3 SUB G G Substrate Ground. Connect to system Ground. C3 RGND G G Reference/sense Ground. Should connect to the Ground node of the switching regulators output capacitors. D5 ENABLE I D Enable input. Set this digital input high for normal operation. F2 SCLK I D PowerWise Interface (PWI) clock input F1 SPWI I/O D PowerWise Interface (PWI) bi-directional data E5 RESETN I D Active low Reset input. Set this digital input high for normal operation. F5 PWROK O D Power OK indicator. This is a digital, active high output signal. E1 VO1 P P LDO1 output voltage. F6 VO2 P P LDO2 output voltage. PWI signals SCLK and SPWI reference voltage. C6 VO3 P P LDO3 output voltage. Can be programmed to track VCORE1 voltage. C1 VO4 P P LDO4 output voltage. Can be programmed to track VCORE2 voltage. D6 VO5 P P LDO5 output voltage. A5 SW1 P P VCORE1 Switching node; connected to filter inductor. A2 SW2 P P VCORE2 Switching node; connected to filter inductor. B5 VFB1 I A VCORE1 Switcher analog feedback input. Connect to the VCORE1 output voltage. VCORE2 Switcher analog feedback input. Connect to the VCORE2 output voltage. B2 VFB2 I A C4 GPO0 O D/OD General Purpose Output 0. Can be programmed as a CMOS output referenced to VO2 or as an open-drain output to a user selected voltage. D4 GPO1 O D/OD General Purpose Output 1. Can be programmed as a CMOS output referenced to VO2 or as an open-drain output to a user selected voltage. D3 GPO2 O D/OD General Purpose Output 2. Can be programmed as a CMOS output referenced to VO2 or as an open-drain output to a user selected voltage. C2 SA1 I D PWI Slave Address Bit 1. Tie to Ground or VIN for 0 or 1, respectively. (Note: SA0 is internal. '0' = Slave(N) = VCORE1; '1' = Slave(N+1) = VCORE2) D2 SA2 I D PWI Slave Address Bit 2. Tie to Ground or VIN for 0 or 1, respectively. E3 SA3 I D PWI Slave Address Bit 3 (MSB). Tie to Ground or VIN for 0 or 1, respectively. C5 Reserved G G Must be tied to Ground. Failure to do so may result in undefined behavior. A: Analog Pin I: Input Pin www.national.com D: Digital Pin I/O: Input/Output Pin G: Ground Pin O: Output Pin 4 P: Power Pin OD: Open Drain Output Pin Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input voltage range VIN ENABLE, RESETN, PWROK VIN pins (All VDD pins) SW1, SW2, V01, V02, V03, V04, V05 to GND ENABLE, RESETN, SCLK, SA1, SA2, SA3 SPWI, PWROK, VFB1, VFB2, GPO0, GPO1, GPO2 Junction Temperature (TJ-MAX) Storage Temperature Range Max Continuous Power Dissipation PD-MAX (Notes 3, 4) Maximum Lead Temperature (Soldering, 10 seconds) ESD Ratings (Notes 1, 2) 2.7V to 4.8V 0V to VIN V 0V to VO2 V 0V to VIN V SPWI, SCLK SA1, SA2, SA3 −0.3V to +6.0V −0.3V to +(VIN+0.3)V Thermal Properties −0.3V to +(VIN+0.3)V Junction Temperature (TJ) −0.3V to +(VIN+0.3)V −40°C to +125°C Ambient Temperature (TA) (Note 6) Junction-to-Ambient Thermal Resistance (θJA) (Note 7) +150°C −65°C to +150°C Internally limited −40°C to +85°C 60°C/W +260°C (Note 5) All pins 2kV HBM 200V MM General Electrical Characteristics (Notes 2, 8, 9) Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C ≤ TJ≤+125°C. Symbol IQ Parameter Shutdown Supply Current Conditions Min All circuits off; -40ºC ≤TA= TJ≤ +125ºC Memory retention current in VCORE1 and VCORE2 in Sleep Deep Sleep (i.e., both slaves state; VO1, VO2, and VO5 on, but in Sleep state) unloaded; V03 and VO4 in low IQ No load supply current UVLO-high Under Voltage Lockout, high threshold UVLO-low Under Voltage Lockout, low threshold All regulators active and unloaded; switching regulators in Burst-PWM 2.5 Typ Max 1 75 130 350 735 930 2.6 2.7 2.6 Units µA V V Thermal Shutdown TSD Threshold (Note 10) Hysteresis (Note 10) 160 20 °C Logic and Control Inputs VIL Logic Input Low VIH-SIDEBAND Logic Input High VIH-PWI Logic Input High SPWI, SCLK 1.5V ≤ VO2 ≤ 3.3V IIL Input Leakage Current ENABLE, RESETN RPD-PWI ENABLE, RESETN, SPWI, 0.2 SCLK 2.7V ≤ VIN ≤ 4.8V ENABLE, RESETN 2.7V ≤ VIN ≤ 4.8V 2.0 V VO2-0.2 V -1 +1 Input Leakage Current (Note: SPWI, SCLK 1.5V ≤ VO2 ≤ 3.3V Largely due to pull-down resistors) -1 +5 Pull-down resistance for PWI SPWI, SCLK signals 0.5 2.7V ≤ VIN ≤ 4.8V 5 V µA 1 2 MΩ www.national.com LP5552 Absolute Maximum Ratings (Notes 1, 2) LP5552 Symbol Parameter Conditions Min Typ Max Units 0.4 V Logic and Control Outputs VOL Logic Output Low PWROK, SPWI, GPOx VOH-SIDEBAND Logic Output High VOH-PWI Logic Output High VOH-GPOx Logic Output High VOD-GPOx Maximum Open-Drain High Voltage IGPO GPO Source/Sink Current TENL Minimum ENABLE low pulse time 100 nS TRSTL Minimum RESETN low pulse time 100 nS ISINK ≤ 1mA PWROK ISOURCE ≤ 1mA SPWI ISOURCE ≤ 1mA GPOx, GPOs set for CMOS out ISOURCE ≤ 1mA Output Specification VIN-0.4 V VO2-0.4 V VO2-0.4 V GPOx VIN+0.3 1 V mA (Notes 2, 9) Supply Output Voltage Range (V) Default Output Voltage (V) Output Voltage Resolution (mV) IMAX Maximum Output Current (mA) VCORE1 0.6 to 1.235 1.235 5 800 Voltage Scaling Domain 1 VCORE2 0.6 to 1.235 1.235 5 800 Voltage Scaling Domain 2 LDO1 0.7 to 2.2 1.2 100 100 PLL/Fixed Logic LDO2 1.5 to 3.3 3.3 100-300 250 I/O Ring LDO3 0.6 to 1.35 1.25 50 50 Embedded Memory Domain 1 LDO4 0.6 to 1.35 1.25 50 50 Embedded Memory Domain 2 LDO5 1.2 to 3.3 3.3 100-300 250 Peripheral(s) www.national.com 6 Typical Application Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Notes 2, 8, 9) Symbol Parameter Conditions Min Typ Max Units Output voltage, Static accuracy 0.65V ≤ VOUT ≤ 1.235V IOUT = 0 - 800mA -2 +2 Output voltage, Static accuracy 0.60V ≤ VOUT ≤ 0.65V IOUT = 0 - 800mA -4 +4 VOUT Range Programmable Output Voltage Range 0mA ≤ IOUT ≤ 800mA 0.6 ΔVOUT Line regulation 2.7V ≤ VIN ≤ 4.8V, IOUT = 100mA 0.05 Load regulation 100mA ≤ IOUT ≤ 800mA 0.001 TSCALING VOUT Setting Time From min to max output voltage IOUT = 400mA IQ Quiescent current No Load, Burst-PWM Mode 325 µA RDS-ON(P) P-FET resistance VIN = VSG = 3.6V 255 mΩ RDS-ON(N) N-FET resistance VIN = VGS = 3.6V IOUT Continuous load current ILIM Peak switching current limit η Efficiency peak IOUT = 200mA, VIN = 2.7V, VCOREx = 1.235V fOSC Oscillator frequency PWM-mode COUT Output Filter Capacitance 0mA ≤ IOUT ≤ 800mA VOUT Accuracy 1.235 (default) 1200 mΩ mA 1560 mA % 3.45 3.6 3.75 MHz 7 10 13 µF 20 mΩ 1.3 µH L Output Filter Inductance tSS Soft start ramp time 120 tSTART-UP Start-Up Time from VCOREx enable VCOREx = 1.235V, unloaded to VOUT 200 7 µS 800 88 0 0mA ≤ IOUT ≤ 800mA %/mA 135 850 V %/V 30 0 Output Capacitor ESR 1.235 % 0.7 1.0 µs µs www.national.com LP5552 VCORE1/VCORE2 Switchers 1 and 2 Output Voltage Characteristics LP5552 VO1 LDO1 Output Voltage Characteristics Unless otherwise noted, VIN = 3.6V, VOUT = 1.2V (default). Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40° to +125°C. (Notes 2, 8, 9) Symbol Parameter Conditions Min Typ Max VOUT Output Voltage Accuracy 1mA ≤ IOUT ≤ 100mA, 2.7V ≤ VIN ≤ 4.8V -2 VOUT Range Programmable Output Voltage Range 0mA ≤ IOUT ≤ 100mA 16 steps of 100mV 0.7 IOUT Output Current 2.7V ≤ VIN ≤ 4.8V 100 Output Current Limit VO1 = 0V (i.e., tied to Ground) 400 IQ Quiescent Current (Note 12) IOUT = 50mA ΔVOUT Line Regulation 2.7V ≤ VIN ≤ 4.8V IOUT = 50mA Load Regulation 1mA ≤ IOUT ≤ 100mA Line Transient Regulation VIN = 3.9V→3.6V→ 3.9V TRISE = TFALL = 10µS 10 Load Transient Regulation VIN = 3.6V 60 2 1.2 (default) 2.2 19 0.1 -0.005 0.005 PSRR f = 1kHz Power Supply Ripple Rejection COUT = 2.2µF Ratio f = 10kHz COUT = 2.2µF COUT Output Capacitance Start-Up Time from LDO1 enable www.national.com mA %/V %/mA mV 100 µVRMS 50 dB 40 0mA ≤ IOUT ≤ 100mA Output Capacitor ESR tSTART-UP V mV 10Hz ≤ f ≤ 100kHz COUT = 2.2µF Output Noise Voltage % µA -0.1 IOUT = 10mA→90mA→10mA TRISE = TFALL = 10µS eN Units 1 2.2 5 COUT = 2.2µF, IOUT = 100mA 8 50 20 µF 500 mΩ µs Unless otherwise noted, VIN = 3.6V, IOUT = 125mA, VO2 = 3.3V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40 to +125°C. (Notes 2, 8, 9) Symbol Parameter Conditions Min Typ Max VOUT Output Voltage Accuracy 1mA ≤ IOUT ≤ 250mA, 3.6V ≤ VIN ≦ 4.8V -2 VOUT Range Programmable Output Voltage Range 1.5 through 2.3 in 100mV steps, 2.5, 2.8, 3.0V and 3.3V 1.5 IOUT Output Current (VO2 + 0.4)V ≤ VIN ≤ 4.8V 250 Output Current Limit VO2 = 0V (i.e., tied to Ground) 800 2 3.3 (default) VIN - VO2 Dropout Voltage (Note 11) IOUT = 125mA 70 IQ Quiescent Current (Note 12) IOUT = 125mA 19 ΔVOUT Line Regulation (VO2 + 0.4)V ≤ VIN ≤ 4.8V IOUT = 125mA Load Regulation VIN = 3.6V 3.3 260 0.1 -0.005 +0.005 1mA ≤ IOUT ≤ 250mA VIN = 4.0V→3.6V→4.0V VO2 = 3.3V TRISE = TFALL = 10µS 10 Load Transient Regulation VIN = 3.6V 125 % V mA mV µA -0.1 Line Transient Regulation (Note 13) Units %/V %/mA mV IOUT = 25mA→225mA→25mA mV TRISE = TFALL = 1μS PSRR COUT f = 1kHz Power Supply Ripple Rejection COUT = 4.7µF Ratio f = 10kHz COUT = 4.7µF Output Capacitance 55 0mA ≤ IOUT ≤ 250mA Output Capacitor ESR tSTART-UP Start-Up Time from LDO2 enable dB 40 2 4.7 5 COUT = 4.7µF, IOUT = 250mA 9 50 20 µF 500 mΩ µs www.national.com LP5552 VO2 LDO2 (I/O Supply) Output Voltage Characteristics LP5552 VO3/VO4 LDO3 and LDO4 Output Voltage Characteristics Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40 to +125°C. (Notes 2, 8, 9) Symbol Parameter VOUT Active/Independent, High IQ Accuracy Active/Independent, Low IQ VOFFSET Conditions Min IOUT ≤ 50mA, 2.7V ≤ VIN ≤ 4.8V Low IQ bit is cleared -2.5 2.5 IOUT ≤ 5mA, 2.7V ≤ VIN ≤ 4.8V Low IQ bit is cleared -2.5 2.5 Active state offset from tracked 0mA ≤ IOUT ≤ 50mA, VFB = 0.9V VCORE 2.7V ≤ VIN ≤ 4.8V Offset = VO3 — VFB1 Offset = VO4 — VFB2 0 Typ 25 Programmable Output Voltage Range 16 steps of 50mV IQ Quiescent Current (Note 12) Active state/Tracking mode IOUT = 10μA Low IQ bit is set 35 Sleep state or Active/Independent mode IOUT = 10μA Low IQ bit is set 10 Output Current Low IQ bit is cleared 2.7V ≤ VIN ≤ 4.8V 50 Output Current Limit Active state/Tracking 2.7V ≤ VIN ≤ 4.8V 50 Output Current Sleep state/Tracking, Low IQ bit is set 2.7V ≤ VIN ≤ 4.8V 5 Output Current, Independent, Low IQ bit is set 2.7V ≤ VIN ≤ 4.8V 0.6 70 1.25 (default) 1.35 V μA 5 Output Current Limit VO2 = 0V (i.e., tied to Ground) Power Supply Ripple Rejection Ratio f = 1kHz COUT = 1.0µF COUT Output Capacitance 0mA ≤ IOUT ≤ 5mA 420 37 Output Capacitor ESR www.national.com % mA PSRR tSTART-UP Start-Up Time from LDOx enable Units mV VOUT Range IOUT Max 0.75 1 5 COUT = 1.0µF, IOUT = 20mA 10 50 dB 2.2 µF 500 mΩ µs Unless otherwise noted, VIN = 3.6V, IOUT = 125mA, VO2 = 3.3V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40 to +125°C. (Notes 2, 8, 9) Symbol Parameter Conditions Min Typ Max VOUT Output Voltage Accuracy 1mA ≤ IOUT ≤ 250mA, VO2 = 3.3V -2 VOUT Range Programmable Output Voltage Range 1.2 through 2.3 in 100mV steps, 2.5, 2.8, 3.0V, and 3.3V 1.2 IOUT Output Current (VO5 + 0.4)V ≤ VIN ≤ 4.8V 250 Output Current Limit VO5 = 0V (i.e., tied to Ground) 800 % 3.6V ≤ VIN ≤ 4.8V VIN - VO5 Dropout Voltage (Note 11) IOUT = 125mA IQ Quiescent Current (Note 12) IOUT = 125mA ΔVOUT Line Regulation (VO5 + 0.4)V ≤ VIN ≤ 4.8V IOUT = 125mA Load Regulation VIN = 3.6V 3.3 (default) 70 3.3 260 19 VIN = 4.0V→3.6V→4.0V VO5 = 3.3V Load Transient Regulation VIN = 3.6V V mA mV µA -0.1 0.1 -0.005 0.005 1mA ≤ IOUT ≤ 250mA Line Transient Regulation (Note 13) Units 2 %/V %/mA 10 TRISE = TFALL = 10μS mV 125 IOUT = 25mA→225mA→25mA TRISE = TFALL = 1µS PSRR COUT f = 1kHz Power Supply Ripple Rejection COUT = 4.7µF Ratio f = 10kHz COUT = 4.7µF Output Capacitance 55 0mA ≤ IOUT ≤250mA Output Capacitor ESR tSTART-UP Start-Up Time from LDO5 enable dB 40 2 4.7 5 COUT = 4.7µF, IOUT = 250mA 11 50 20 µF 500 mΩ µs www.national.com LP5552 VO5 LDO5 Output Voltage Characteristics LP5552 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: P = (TJ – TA)/θJA where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=160ºC (typ.) and disengages at TJ = 140ºC (typ.). Note 5: The human-body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. MIL-STD-883 3015.7. Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 7: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51–3. The test board is a 4-layer FR-4 board. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1112: Micro SMD Wafer Level Chip Scale Package and Application Note 1610: LP5552 Evaluation Board. Note 8: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 9: Capacitors: Low-ESR Multi-Layer Ceramic Capacitors are (MLCCs) used in setting electrical characteristics. Note 10: Guaranteed specifically by design. Note 11: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. Other parameters are not guaranteed when the LDO is in dropout. This specification applies only when the output voltage is greater than 2.7V. Note 12: Quiescent currents for LDO1 through LDO5 do not include shared blocks such as the bandgap reference. Note 13: VIN for line transient is above the default 3.6V to allow for 400mV of headroom from VIN to VOUT. www.national.com 12 Unless otherwise specified: VIN = 3.6V, TA = 25ºC, output voltages and external components are default values specified in electrical characteristics table. Sleep IQ Curves Over Temperature Shutdown IQ Curves Over Temperature 20210304 20210305 LP5552 Startup Timing All Outputs at No Load VO3/VO4 Line Transient Response 20210306 20210309 13 www.national.com LP5552 LP5552 - Typical Performance Characteristics LP5552 Switcher Load Transient Response 20mA <--> 800mA / 3µS Switcher Load Transient Response 20mA <--> 575mA / 2µS 20210313 20210314 Switcher CVA 0x00 to 0x7F Tracking and Slew Limit Set Switcher CVA 0x7F to 0x00 Tracking and Slew Limit Set 20210317 20210316 Efficiency vs. Load, VCOREx VCOREx PWM Switching Waveform 20210320 20210319 www.national.com 14 LP5552 VCOREx Burst-PWM Switching Waveform VO1/VO2/VO5 Line Transient Response 20210321 20210353 VO2/VO5 Load Transient Response VO1 Load Transient Response 20210354 20210355 15 www.national.com LP5552 LP5552 PWI Register Map The PWI 2.0 standard defines 32 8-bit base registers, and up to 256 8-bit extended registers, on each PWI slave. The table below summarizes these registers and shows default register bit values after reset, as programmed by the factory. The following subsections provide additional details on the use of each individual register. Slave Address [N] Base Registers Register Address Register Register Usage Name Type 0x00 R0 Core Voltage 1 Switcher #1 0x01 R1 0x02 Reset Default Value 7 6 5 4 3 2 1 0 R/W 0* 1 1 1 1 1 1 1 Memory Voltage 1 Independent Mode R/W 0* 1 1 0 1 0* 0* 0* R2 LDO3 Memory Retention Voltage 1 Sleep State R/W 0* 1 1 0 1 0* 0* 0* 0x03 R3 Status Register 1 R/O 0* 0* 0* 0* 1* 1* 1* 1* 0x04 R4 Device Capability Register 1 R/O 0 0 0 0 0 0 1 0 0x05 R5 Not Implemented N/A - - - - - - - - 0x06 R6 Not Implemented N/A - - - - - - - - 0x07 R7 LDO2 voltage (I/O voltage) R/W 0* 1 1 1 1 0* 0* 0* 0x08 R8 LDO1 voltage R/W 0* 0 1 0 1 0* 0* 0* 0x09 R9 LDO5 voltage R/W 0* 1 1 1 1 0* 0* 0* 0x0A R10 Enable Control 1 R/W 0* 1 1 1 1 1 0* VCORE1 LDO3 LDO2 LDO1 LDO5 Enable Enable Enable Enable Enable 0 Force PWM Switcher #1 0x0B R11 Not Implemented N/A - - - - - - - - 0x0C R12 GPO Data Register R/W 0* 0* 0* 0* 0* 0 GP2 0 GP1 0 GP0 0x0D R13 Miscellaneous Control 1 R/W 0* 0* 0* 0* 1 GPO Open Drain Select 0 SW1 Slew Control 0 LDO3 Track Select 0 LDO3 Low IQ Bit 0x0E-0x1E R14-R30 Not Implemented N/A - - - - - - - - 0x1F Res. - - - - - - - - - - - - - R31 Reserved Do not write to Extended Registers 0x00-0xFF ER0ER255 www.national.com Extended Register Space Not Implemented N/A - - 16 - LP5552 Slave Address [N+1] Base Registers Register Address Register Register Usage Name Type 7 6 5 4 3 2 1 0 0x00 R0 Core Voltage 2 Switcher #2 R/W 0* 1 1 1 1 1 1 1 0x01 R1 Memory Voltage 2 Independent Mode R/W 0* 1 1 0 1 0* 0* 0* 0x02 R2 LDO4 Memory Retention Voltage 2 Sleep State R/W 0* 1 1 0 1 0* 0* 0* 0x03 R3 Status Register 2 R/O 0* 0* 0* 0* 1* 1* 1* 1* 0x04 R4 Device Capability Register 2 R/O 0 0 0 0 0 0 1 0 0x05-0x09 R5-R9 Not Implemented N/A - - - - - - - - 0x0A R10 Enable Control 2 R/W 0* 1 1 0* VCORE2 LDO4 Enable Enable 0* 0* 0* 0 Force PWM Switcher #2 0x0B-0x0 C R11-R12 Not Implemented N/A - - - - - - - - 0x0D R13 R/W 0* 0* 0* 0* 0* 0 SW2 Slew Control 0 LDO4 Track Select 0 LDO4 Low IQ Bit - - - - - - - - - - - - - Miscellaneous Control 2 0x0E-0x1F R14-R31 Not Implemented N/A Reset Default Value Extended Registers 0x00-0xFF ER0ER255 Extended Register Space Not Implemented N/A - - - Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. A bit with a hyphen ( - ) denotes a bit in an unimplemented register location. A write into unimplemented register(s) will be ignored. A read of an unimplemented register(s) will produce a “No response frame”. Please refer to PWI specification version 2.0 for further information. 17 www.national.com LP5552 Slave Address [N] - 1st Slave Device R0 - VCORE1 - Core Voltage 1 Address Slave Address Type Reset Default 0x00 N R/W 8h'7F Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:0 Voltage Programmed voltage value. Default value is in bold. Voltage Data Code [6:0] Voltage Value (V) 7h'00 0.60 7h'xx Linear scaling 7h'7F 1.235 (default) R1 - VO3 - LDO3 Memory Voltage 1 - Independent Mode Address Slave Address Type Reset Default 0x01 N R/W 8h'68 Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Programmed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 www.national.com Unused Voltage Data Code [6:3] Voltage Value (volts) 4h'0 0.60 4h'1 0.65 4h'2 0.70 4h'3 0.75 4h'4 0.80 4h'5 0.85 4h'6 0.90 4h'7 0.95 4h'8 1.00 4h'9 1.05 4h'A 1.10 4h'B 1.15 4h'C 1.20 4h'D 1.25 (default) 4h'E 1.30 4h'F 1.35 These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. 18 LP5552 R2 - VO3 - LDO3 Memory Retention Voltage 1 - Sleep State Value Address Slave Address Type Reset Default 0x02 N R/W 8h'68 Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Programmed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. Voltage Data Code [6:3] 2:0 Unused Voltage Value (volts) 4h'0 0.6 4h'1 0.65 4h'2 0.70 4h'3 0.75 4h'4 0.80 4h'5 0.85 4h'6 0.90 4h'7 0.95 4h'8 1.00 4h'9 1.05 4h'A 1.10 4h'B 1.15 4h'C 1.20 4h'D 1.25 (default) 4h'E 1.30 4h'F 1.35 These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. R3 - Status Register 1 Address Slave Address Type Reset Default 0x03 N Read Only 8h'0F Bit Field Name Description or Comment 7:4 Unused Unused, read returns 0. 3:0 Unused Unused, read returns 1. 19 www.national.com LP5552 R4 - Device Capability Register 1 Address Slave Address Type Reset Default 0x04 N Read Only 8h'02 Bit Field Name Description or Comment 7:3 Optional Function Extended Register Read and Write are not supported by LP5552, read returns '0'. Support 3:0 Version Read transaction will return 0x2 indicating PWI 2.0 specification. Write transactions to this register are ignored. R7 - VO2 - LDO2 Voltage Address Slave Address Type Reset Default 0x07 N R/W 8h'78 Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Programmed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 www.national.com Unused Voltage Data Code [6:3] Voltage Value (volts) 4h'0 1.5 4h'1 1.5 4h'2 1.5 4h'3 1.5 4h'4 1.6 4h'5 1.7 4h'6 1.8 4h'7 1.9 4h'8 2.0 4h'9 2.1 4h'A 2.2 4h'B 2.3 4h'C 2.5 4h'D 2.8 4h'E 3.0 4h'F 3.3 (default) These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. 20 LP5552 R8 - VO1 - LDO1 Voltage Address Slave Address Type Reset Default 0x08 N R/W 8h'28 Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Programmed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h'0 0.7 4h'1 0.8 4h'2 0.9 4h'3 1.0 4h'4 1.1 4h'5 1.2 (default) 4h'6 1.3 4h'7 1.4 4h'8 1.5 4h'9 1.6 4h'A 1.7 4h'B 1.8 4h'C 1.9 4h'D 2.0 4h'E 2.1 4h'F 2.2 These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. 21 www.national.com LP5552 R9 - VO5 - LDO5 Voltage Address Slave Address Type Reset Default 0x09 N R/W 8h'78 Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Programmed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 www.national.com Unused Voltage Data Code [6:3] Voltage Value (volts) 4h'0 1.2 4h'1 1.3 4h'2 1.4 4h'3 1.5 4h'4 1.6 4h'5 1.7 4h'6 1.8 4h'7 1.9 4h'8 2.0 4h'9 2.1 4h'A 2.2 4h'B 2.3 4h'C 2.5 4h'D 2.8 4h'E 3.0 4h'F 3.3 (default) These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. 22 LP5552 R10 - Enable Control Register 1 Address Slave Address Type Reset Default 0x0A N R/W 8h'7C Bit Field Name Description or Comment 7 Unused This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6 R0, Core Voltage 1 1 : regulator is enabled (default) Enable 0 : regulator is disabled 5 R2, LDO3 Voltage Enable 1 : regulator is enabled (default) 0 : regulator is disabled 4 R7, LDO2 Voltage Enable 1 : regulator is enabled (default) 0 : regulator is disabled 3 R8, LDO1 Voltage Enable 1 : regulator is enabled (default) 0 : regulator is disabled 2 R9, LDO5 Voltage Enable 1 : regulator is enabled (default) 0 : regulator is disabled 1 Unused This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 0 Forced PWM Mode 0 : Intelligent and Automatic PWM/Burst-PWM Transition - Most Energy Efficient (default) — Switcher #1 1 : Forced PWM - No Burst Mode Allowed - Smallest Voltage Ripple R12 - GPO Data Register Address Slave Address Type Reset Default 0x0C N R/W 8h'00 Bit Field Name Description or Comment 7:3 Unused These bits are fixed to ‘0’. Reading these bits will result in a ‘00000’. Any data written into these bits using the Register Write command is ignored. 2 GPO2 General purpose output - digital. This bit is drives the GP2 pin 1 GPO1 General purpose output - digital. This bit is drives the G1 pin 0 GPO0 General purpose output - digital. This bit is drives the GP0 pin 23 www.national.com LP5552 R13 - Misc Control Register 1 Address Slave Address Type Reset Default 0x0D N R/W 8h'08 Bit Field Name Description or Comment 7:4 Unused These bits are fixed to ‘0’. Reading these bits will result in a ‘0000’. Any data written into these bits using the Register Write command is ignored. 3 GPO Open Drain ‘0’: GPOs will behave as push-pull CMOS outputs referenced to VO2 Select ‘1’: GPOs will act as open-drain outputs (default) 2 SW1 Slew Control '0': No slew rate restriction on VCORE1 switcher output voltage (default) '1': Slew rate of VCORE1 switcher output voltage is reduced 1 LDO3 Tracking Select '0': LDO3 at R1 register value in Active mode. LDO3 does not track VCORE1 (default) '1': LDO3 tracks VCORE1 with offset 0 LDO3 Low IQ Bit '0': Selects the higher bias point for LDO3 which results in 50mA operation (default) '1': Selects the lower bias point for LDO3 which results in 5mA operation See Table 3 for a more detailed explanation of this bit R31 - Reserved Address Slave Address Type Reset Default 0x1F N Reserved 8h'00 Bit Field Name Description or Comment 7:0 Reserved This register is reserved. The user should avoid accessing this register to prevent undefined behavior of the LP5552. Slave Address [N+1] - 2nd Slave Device - R0 - VCORE2 - Core Voltage 2 Address Slave Address Type Reset Default 0x00 N+1 R/W 8h'7F Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:0 Voltage Programmed voltage value. Default value is in bold. Voltage Data Code [6:0] www.national.com Voltage Value (V) 7h'00 0.60 7h'xx Linear scaling 7h'7F 1.235 (default) 24 LP5552 R1 - VO4 - LDO4 Memory Voltage 2 - Independent Mode Address Slave Address Type Reset Default 0x01 N+1 R/W 8h'68 Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Programmed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h'0 0.60 4h'1 0.65 4h'2 0.70 4h'3 0.75 4h'4 0.80 4h'5 0.85 4h'6 0.90 4h'7 0.95 4h'8 1.00 4h'9 1.05 4h'A 1.10 4h'B 1.15 4h'C 1.20 4h'D 1.25 (default) 4h'E 1.30 4h'F 1.35 These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. 25 www.national.com LP5552 R2 - VO4 - LDO4 Memory Retention Voltage 2 - Sleep State Value Address Slave Address Type Reset Default 0x02 N+1 R/W 8h'68 Bit Field Name Description or Comment 7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. 6.3 Voltage Programmed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h'0 0.6 4h'1 0.65 4h'2 0.70 4h'3 0.75 4h'4 0.80 4h'5 0.85 4h'6 0.90 4h'7 0.95 4h'8 1.00 4h'9 1.05 4h'A 1.10 4h'B 1.15 4h'C 1.20 4h'D 1.25 (default) 4h'E 1.30 4h'F 1.35 These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. R3 - Status Register 2 Address Slave Address Type Reset Default 0x03 N+1 Read Only 8h'0F Bit Field Name Description or Comment 7:4 Unused Unused, read returns 0. 3:0 Unused Unused, read returns 1. www.national.com 26 LP5552 R4 - Device Capability Register 2 Address Slave Address Type Reset Default 0x04 N+1 Read Only 8h'02 Bit Field Name Description or Comment 7:3 Optional Function Extended Register Read and Write are not supported by LP5552, read returns '0'. Support 2:0 Version Read transaction will return 0x2 indicating PWI 2.0 specification. Write transactions to this register are ignored. R10 - Enable Control Register 2 Address Slave Address Type Reset Default 0x0A N+1 R/W 8h'60 Bit Field Name Description or Comment 7 Unused This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6 R0, Core Voltage 1 : regulator is enabled (default) 2 Enable 0 : regulator is disabled 5 R2, LDO4 Voltage Enable 1 : regulator is enabled (default) 0 : regulator is disabled 4:1 Unused These bits are fixed to '0'. Reading these bits will result in a '000'. Any data written into these bits using the Register Write command is ignored. 0 Forced PWM Mode - Switcher #2 0 : Intelligent and Automatic PWM/Burst-PWM Transition - Most Energy Efficient (default) 1 : Forced PWM - No Burst Mode Allowed - Smallest Voltage Ripple R13 - Misc Control Register 2 Address Slave Address Type Reset Default 0x0D N+1 R/W 8h'00 Bit Field Name Description or Comment 7:3 Unused These bits are fixed to ‘0’. Reading these bits will result in a ‘00000’. Any data written into these bits using the Register Write command is ignored. 2 SW2 Slew Control '0': No slew rate restriction on VCORE1 switcher output voltage (default) '1': Slew rate of VCORE1 switcher output voltage is reduced 1 LDO4 Tracking Select '0': LDO4 at R1 register value in Active mode. LDO4 does not track VCORE2 (default) '1': LDO4 tracks VCORE2 with offset 0 LDO4 Low IQ Bit '0': Selects the higher bias point for LDO4 which results in 50mA operation (default) '1': Selects the lower bias point for LDO4 which results in 5mA operation See Table 3 for a more detailed explanation of this bit 27 www.national.com GENERAL DESCRIPTION The LP5552 is a PowerWise Interface (PWI) 2.0 compliant energy management unit (EMU) for application or baseband processors in mobile phones and other portable equipment. It operates cooperatively with processors using National Semiconductor’s Advanced Power Controller (APC) to provide Adaptive Voltage Scaling (AVS) which drastically improves efficiencies compared to conventional power delivery methods. The LP5552 consists of two high-efficiency switching DC/DC buck converters to supply two voltage scaling domains, and five LDOs for supplying additional support circuitry. VOLTAGE SCALING The LP5552 is designed to be used in a voltage scaling system to lower the power dissipation of the system. By scaling supply voltage with the clock frequency of a processor, dramatic power savings can be achieved. Two types of voltage scaling are supported, dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS). Both Switcher 1 and Switcher 2 support AVS and DVS modes. DVS systems switch between pre-characterized voltages, which are paired to clock frequencies used for frequency scaling in the processor. AVS systems track the processor performance and optimize the supply voltage to the required performance. AVS is a closed loop system that provides process and temperature compensation such that for any given processor, temperature, or clock frequency, the minimum supply voltage is delivered. SLAVE ADDRESSING DESCRIPTION PWI 2.0 supports up to 16 logical slaves in the same system. Four slave address bits are included at the start of every PWI communications frame to identify which slave is being targeted by the PWI master. The LP5552 contains 2 logical slaves in its package. The 3 MSBs of the LP5552’s slave address are set by the SA1, SA2, and SA3 pins. They are actively decoded by the LP5552 on every transaction. The LSB of the slave address is hard-wired inside the LP5552. Slave ‘N’ will always be located at SA[0] = 0, and slave ‘N+1’ will always exist at SA[0] = 1. As an example, if we were to tie SA1 = SA3 = VDD and SA2 = GND in our system, then the LP5552’s slave ‘N’ would be located at SA[3:0] = 0xA and slave ‘N+1’ would be SA[3:0] = 0xB. POWERWISE INTERFACE What follows is only a brief description of the parts of the PWI 2.0 spec that are relevant to the LP5552. Please see the PWI 2.0 spec for a complete description. To support DVS and AVS, the LP5552 is programmable via the low-power, 2-wire PowerWise Interface (PWI). This serial interface controls the various voltages and states of all the regulators in the LP5552. CONTROL AND STATUS SIGNALS The LP5552 implements all 3 of the PWI 2.0 control and status signals. ENABLE and RESETN are inputs to the LP5552 that allow for power-up and power-down sequencing, as well as resetting the EMU to a known state. Both ENABLE and RESETN must be a logic ‘1’ during normal operation. PWROK is an indicator to the system that the LP5552 is in regulation and power is stable. Its output is dependent upon the state of the two slave devices. See Table 1, “PWROK Value Per Slave State,” below for details. All 3 signals are asynchronous signals. TABLE 1. PWROK Value Per Slave State SLAVE (N+1) SLAVE (N) LP5552 Both slaves in the LP5552 support the full PWI command set, other than the optional Extended Register Read and Write, as described in the PWI 2.0 specification: • Core Voltage Adjust • Reset • Sleep • Shutdown • Wakeup • Register Read • Register Write • Authenticate The 2-wire PWI interface is composed of the SCLK and SPWI pins on the LP5552. SCLK is always an input to the LP5552 and should be driven by a PowerWise master in the system. The SCLK clock rate can operate from 32kHz – 15MHz. SPWI is the bi-directional serial data line. It can drive a 50pF line and meet timing standards for a 15MHz PWI bus. Both signals are referenced to the voltage present at VO2, the LDO2 output voltage. Both signals contain an internal pull-down resistor of ~1MΩ, in accordance with the PWI 2.0 specification. LP5552 Operation STARTUP ACTIVE SLEEP SHUTDOWN STARTUP 0 1 1 0 ACTIVE 1 1 1 1 SLEEP 1 1 1 1 SHUTDOWN 0 1 1 0 R13[3]. In the open-drain configuration, they can be referenced to any voltage less than the VDD of the LP5552. The push-pull output mode will reference the high-side to the voltage of LDO2. General Purpose Outputs The LP5552 contains 3 digital output pins that can be used as the system designer sees fit. By default, they are configured as open-drain outputs, outputting a logic ‘0’. They can be changed to a push-pull CMOS output by clearing Slave ‘N’, www.national.com 28 LP5552 SLAVE OPERATING STATES Each slave in the LP5552 has four operating states: Startup, Active, Sleep, and Shutdown. (Figure 1.) 20210345 FIGURE 1. LP5552 Slave State Diagram The Startup state is the default state for both slaves after reset. All regulators are off and PWROK output is a ‘0’. The device will move to the Active state when the external ENABLE and RESETN signals are both pulled high. After the state transition completes, both slaves will be in the Active state, but each slave will maintain its own independent state thereafter. The default, factory-programmed power-up sequence of the LP5552 can be seen in Figure 2. From the global ENABLE of the chip, there is ~80uS of time for powering on and stabilizing internal support circuitry. Once this time has expired, the startup time slots begin. Table 2 shows the time slots that each regulator begins in. Note that for the switchers, there is an additional ~75uS of set-up time from the beginning of the time slot until the soft-start ramp begins. 20210306 FIGURE 2. LP5552 Startup Timing 29 www.national.com LP5552 TABLE 2. Factory Programmed Startup Time Slots Time slot Start time (µS) Regulator(s) 0 0 LDO2 1 32 LDO5/AVS1 2 64 LDO1/AVS2 3 96 LDO3 4 128 LDO4 In the Active state, all regulators that are enabled are on, and their outputs are defined by their programmed register values. If the Active state has been reached from the Startup state, the regulators will be programmed to their default value. In the Active state, the PWI master has complete control over the LP5552’s operation. The PWROK output is ‘1’ if either slave is in this state. The Sleep state is entered by issuing the Sleep command on the PWI bus. The core regulator of the addressed slave, and the associated memory LDO will both respond to the Sleep command. For the first 32uS after the command is decoded, the core regulator will transition to its zero-code value of 0.6V, and the LDO will move to its POR value of 1.25V. After the 32uS has expired, the core regulator will be turned off and the LDO will transition to its memory retention value as programmed in register R2. See Figure 3. LDO1, LDO2, and LDO5 are unaffected by the Sleep command and will maintain their programmed values. They may be turned off manually, if desired. The LP5552 will still respond to all PWI traffic as long as LDO2 remains active. 20210365 FIGURE 4. Wakeup Behavior of Core and Memory The Shutdown command will place the addressed slave in the Shutdown state. This command may be issued to any slave in either the Active or Sleep states. All regulators within that state will turn off. The LP5552 holds out one exception to this rule. LDO1, LDO2, and LDO5 act as a shared resource between the two slave devices in the EMU. Therefore, placing just slave ‘N’ into Shutdown will not turn off these regulators even though their registers exist within that space. Slave ‘N’ can be in the Shutdown state, but as long as Slave ‘N+1’ is still in either Active or Sleep states, these shared LDOs will remain on, and PWI traffic will be decoded. Once the Shutdown command has been sent to both slaves, all regulators on the LP5552 will be turned off. The PWROK signal will be ‘0’ if both slaves are in the Shutdown state. The only way to transition away from the Shutdown state is by disabling or resetting the LP5552. By taking the ENABLE pin or the RESETN pin low, the LP5552 will transition to the Startup state. Power-down sequencing is not actively managed by the LP5552 logic, but can be handled by turning off regulators in the desired order within the application, prior to Shutdown. PWM/BURST-PWM OPERATION The switching regulators in the LP5552 have two modes of operation, pulse width modulation (PWM) and “Burst”-PWM. In PWM, the converter switches at 3.6MHz. Each period can be split into two cycles. During the first cycle, the high-side switch is on and the low-side switch is off. During this cycle, the inductor current is rising. In the second cycle, the highside switch is off and the low-side switch is on causing the inductor current to decrease. The output ripple voltage is lowest in PWM mode. As the load current decreases, the converter efficiency becomes worse due to switching losses. The LP5552 will automatically transition to Burst mode at light load current levels. The exact transition point is dependent upon the present operating environment, and the mode assessment is constantly evaluated. The transition is approximately equal to: 20210364 FIGURE 3. Sleep Behavior of Core and Memory A slave may return to the Active state by issuing the Wakeup command. This will result in the core regulator turning on after a ~75uS delay and a soft-start ramp. It will wake up at its maximum value of 1.235V. The associated memory LDO will go to its default POR value of 1.25V until the core has reached the end of its soft-start period and then will transition to its programmed configuration (i.e., either tracking the core or to the value programmed in R1). See Figure 4. The PWROK output is ‘1’ if either slave is in this state. 20210366 In this mode, the output voltage will be allowed to coast with no switching action by the regulator. When the output voltage dips to 1% below nominal, the switches are enabled, the voltage is boosted back up to the programmed value, and the coast process repeats itself. If the user desires tighter control www.national.com 30 be possible. If it is not desirable to use this regulator in the system, the user can turn this regulator off by setting bit 4 of R10 in Slave ‘N’ during system initialization while back-driving the required I/O voltage onto the pin. CURRENT LIMITING A current limit feature exists for all regulators to help protect the LP5552 and external components during overload conditions. The switcher's current limit feature will trip around 1.2A (typ). Once the fault has occurred and current limit has been entered, the switcher will not resume operation until the output current has decreased to a hysteretic low-level set point. Normal operation will proceed after the fault has been cleared. Likewise, the LDOs all implement current limit and will turn off their pass element when their trip point is reached. Please refer to the Electrical Characteristics section for details. TRACKING, SLEW RATE LIMITING, AND LOW IQ BITS There are 3 bits in each slave’s R13 register that determine the performance and operational behavior of the VCOREx and VO3/VO4 outputs. Their significance and interaction is described below. The Low IQ bit setting in R13, bit 0, of each slave allows the selection of a lower IQ bias point at the expense of decreased output current capability for VO3 and VO4. At reset, the default setting is high IQ mode (i.e., bit 0 is cleared) which results in a 50mA output capability for the associated LDO. If bit 0 is set, the quiescent current draw of the part will decrease, but the output current capability of the associated LDO will drop to 5mA. Setting VO3 and VO4 up for low IQ mode is useful in situations where just a trickle of current is required, such as when maintaining some type of low-power memory. The Tracking bit, bit 1 in R13, determines whether or not the LDO3 voltage will track the VCORE1 voltage in Slave ‘N’. Slave ‘N+1’ has its own tracking bit which will determine whether LDO4 tracks VCORE2. Each slave device can be independently configured to tracking or independent mode. When set to operate independently, LDO3 and LDO4 will maintain a voltage output equal to the programmed value of R1 while in the Active state. When set to operate in tracking mode, LDO3 and LDO4 will track the output voltage of their associated switcher, attempting to maintain approximately a 25mV positive offset. There is some interaction between the Low IQ and Tracking bits based on the state of the slave device, and that is detailed in the following table: SOFT START Both switching regulators implement a digital soft-start feature to limit in-rush current during the Startup to Active state transition. The voltage output of the switchers will be gradually increased to the default value of 1.235V. An unloaded switcher output will reach its final value in 120µS (typ.) while a fully loaded switcher – 800mA -- will reach its output in 135µS (typ). Because the LP5552 uses voltage increments to handle softstart, its turn-on time is less dependent on output capacitance and load current than regulators that gradually increase current limit to implement soft-start. LDO2 The on-board LDO2 regulator has special significance to the LP5552. All digital data on the SCLK, SPWI, and the GPOx pins while in push-pull mode, is referenced to this voltage. This regulator is used internally to power the I/O drivers. As such, this regulator must be on in order to communicate with the LP5552. The user should ensure that this regulator does not go into dropout or PWI communication will most likely not TABLE 3. Tracking, IQ Bit, Slave State Truth Table Input Output Tracking, R13[1] Low IQ, R13[0] State LDO3/LDO4 Capability 0 0 Active 50mA 0 0 Sleep 50mA 0 1 Active 5mA 0 1 Sleep 5mA 1 0 Active 50mA 1 0 Sleep 50mA 1 1 Active 50mA 1 1 Sleep 5mA the Slew Rate Limiting bit while not in tracking mode. Setting all 3 bits will result in a system which has the following properties: 1. The tracking LDO will maintain positive offset from VCOREx in Active state. 2. Tracking LDO will be 50mA output capable in Active state, and 5mA capable in Sleep state. The final bit, the Slew Rate Limiting bit (R13[2]), places a limit on how fast the output voltage of the VCOREx regulators can change. If slew rate limiting is not enabled while in tracking mode (i.e., R13[2] is cleared), then the switcher will achieve its new programmed value faster than the tracking LDO can change its output. By setting the Slew Rate Limiting bit, the LP5552 will attempt to keep the positive offset of the tracking LDO in relation to the VCOREx output. For AVS systems, the expected configuration is to have all 3 bits, R13[2:0] set to ‘1’. It generally will not make sense to set 31 www.national.com LP5552 of the output voltage, at the expense of light-load efficiency, the switchers can be commanded to stay in PWM-only mode by setting bit 0 of R10 in the slave’s registers. LP5552 The power dissipated in the input capacitor is given by: Application Hints SWITCHERS Input Capacitors The input capacitor to a switching regulator supplies the AC switching current drawn from the switching action of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle this current: 20210349 The input capacitor must be rated to handle both the RMS current and the dissipated power. A 10µF ceramic capacitor, rated to handle at least 10V, is recommended for each PVDDx/PGNDx pair. Inductor A 1µH inductor should be used for the switchers' output filter. The inductor should be rated to handle the peak load current plus the ripple current: 20210348 20210350 Suggested Inductors and Their Suppliers Model Vendor Dimensions LxWxH (mm) LPS3010–102 Coilcraft 3.0 x 3.0 x 1.0 DCR (Typical) 85mΩ LQM31PN1R0MC0 muRata 3.2 x 1.6 x 0.5 140mΩ PCB interconnect, depending upon the frequency of the ripple current. Ceramic capacitors are predominantly used in portable systems and have very low ESR and should remain capacitive given good PCB layout practices. The switcher peak-to-peak output voltage ripple in steady state can be calculated as: Output Capacitors The switchers in the LP5552 are designed to be used with 10µF of capacitance in the output filter. It is recommended that a 10µF ceramic capacitor, rated to handle at least 10V, and comprised of X5R dielectric material, be chosen. The output capacitor of a switching regulator absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converters is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor or the 20210362 Suggested Switcher Output Capacitors and Their Suppliers Model Vendor Value Type Voltage Case Size (Height) GRM219R61A106KE44 muRata 10µF Ceramic, X5R 10V 0805 (0.85mm) LMK212BJ106KD Taiyo Yuden 10µF Ceramic, X5R 10V 0805 (0.85mm) insert the capacitor into the application circuit. Capacitance will decrease with increasing frequency and DC bias point, and will generally vary with temperature. A typical 6.3V, 10µF, 0603 capacitor may only be providing 4 - 5µF of capacitance when used as the output capacitor in the switching regulators’ loop filter. It is highly recommended that measurements be done on your selected capacitor(s) to ensure you have the proper amount of capacitance. A NOTE ABOUT CAPACITORS Capacitors are typically specified by their manufacturers as a particular value +/-X%. These specified values are only valid for a particular test condition that is often not applicable to the final application circuit. If you were to take a ceramic 10µF capacitor in 0805 package and measure it with an LCR meter, a typical result would be around 7µF. This is before you even www.national.com 32 Dropout Voltages All linear regulators are subject to dropout. Dropout Voltage is the minimum voltage required across the regulator (VIN VOUT) to maintain a constant, specified output voltage. The LP5552 has a VIN range of 2.7V – 4.8V. VO1, VO3, and VO4 cannot be programmed to a level that would make dropout a factor. However, VO2 and VO5 can reach as high as 3.3V on their outputs. Both of those regulators have a dropout voltage of 260mV (MAX). To ensure proper operation of those regulators, the user should ensure that VIN ≥ (VOx-PROGRAMMED + 260mV). If a regulator does go into dropout, the output voltage will start to track the input: VO = VIN - VDROPOUT. Also, the PSRR will go to zero, meaning any noise on the input will be seen at the output. BOARD LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. It is highly recommended that the user consult Application Note AN-1610 for detailed guidelines and best methods for PCB layout of the LP5552. It is also recommended that the user reference AN-1112 for information on the micro SMD package and its requirements. LDO Output Capacitor Selection Guide Output Capacitance Range (Recommended Typical Value) ESR Range LDO1 1.0µF — 20µF (2.2µF) 5mΩ - 500mΩ LDO2 2.0µF — 20µF (4.7µF) 5mΩ - 500mΩ LDO3 0.7µF — 2.2µF (1.0µF) 5mΩ - 500mΩ LDO4 0.7µF — 2.2µF (1.0µF) 5mΩ - 500mΩ LDO5 2.0µF — 20µF (4.7µF) 5mΩ - 500mΩ 33 www.national.com LP5552 LDOs Input Capacitors While not mandatory, it is highly recommended that some input capacitance be provided for the DVDDx and AVDDx pins. Typical values may be in the 0.1 - 1.0µF range. These capacitors will provide bypass for the LP5552 control electronics and LDOs. Output Capacitors The output capacitor of an LDO sets a low frequency pole and a high frequency zero in the control loop of an LDO, as well as providing the initial response for a load transient. The capacitance and the equivalent series resistance (ESR) of the capacitor must be within a specified range to meet stability requirements. The LDOs in the LP5552 are designed to be used with ceramic output capacitors. The following table can be used to select suitable output capacitors: LP5552 Physical Dimensions inches (millimeters) unless otherwise noted 36-Bump uSMD Package NS Package Number TLA36TTA www.national.com 34 LP5552 35 www.national.com LP5552 PWI 2.0 and PowerWise® Technology Compliant Energy Management Unit Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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