LP5551 PowerWise™ Technology Compliant Energy Management Unit General Description Features The LP5551 is a PWI 1.0 compliant Energy Management System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications processors. The LP5551 contains two advanced, digitally controlled switching regulators for supplying variable voltage to processor core and memory. Two regulators provide P- and N- well biasing for threshold scaling applications. The device also integrates 4 programmable LDO-regulators for powering I/O, PLLs and maintaining memory retention in shutdown-mode. The device is controlled via the PWI open-standard interface. The LP5551 operates cooperatively with PowerWise™ technology compatible processors to optimize supply voltages adaptively over process and temperature variations or dynamically using frequency/voltage pre-characterized look-up tables and provides P- and N-well biasing for threshold scaling. ■ 2 300 mA buck regulators operate 180 degrees out of phase for reduced EMI ■ 1 MHz PWM switching frequency ■ 4 programmable LDOs ideal for I/O (two of these), PLL, and memory retention supply generation. ■ Supports high-efficiency PowerWise Technology Adaptive Voltage Scaling ■ PWI open standard interface for system power ■ ■ ■ ■ ■ management Digitally controlled intelligent voltage scaling Auto or PWI controlled PFM mode transition Internal soft start/startup sequencing. Adjustable P- and N- well bias supply for threshold scaling Power OK output. Applications ■ ■ ■ ■ ■ ■ Dual core processors GSM/GPRS/EDGE & UMTS cellular handsets Hand-held radios PDAs Battery powered devices Portable instruments System Diagram 20172163 FIGURE 1. System Diagram © 2007 National Semiconductor Corporation 201721 www.national.com LP5551 PowerWise™ Technology Compliant Energy Management Unit December 2006 LP5551 Connection Diagrams and Package Mark Information 36 - Pin LLP NS Package Number SQA36A 20172102 FIGURE 2. LP5551 Pinout Package Mark 20172146 Note: The actual physical placement of the package marking will vary from part to part. FIGURE 3. Top View www.national.com 2 LP5551 Typical Application 20172130 FIGURE 4. Typical Application Circuit Pin Descriptions Pin # Name I/O Type Description 0 DAP G G Connect Die Attach Pad to ground 1 GP3 O D General purpose output pin 2 GP2 O D General purpose output pin 3 GP1 O D General purpose output pin 4 GP0 O D General purpose output pin 5 PWROK O D Power OK, active high output signal 3 www.national.com LP5551 Pin # Name I/O Type Description 6 RESETN I D Reset, active low 7 EN I D Enable, active high 8 SPWI I/O D PowerWise Interface (PWI) bi-directional data 9 SCLK I D PowerWise Interface (PWI) clock input 10 LDO2 P P LDO2 output, for supplying the I/O voltage on the SoC 11 LDO4 P P LDO4 output, for supplying a fixed voltage to a PLL etc. on the SoC 12 LDO1 P P LDO1 output, user defined 13 NC 14 LDO3 P P LDO3 output, on-chip memory supply voltage 15 NC 16 FB1 P P AVS switcher feedback 17 PGND1 G G Power ground for the AVS switcher 18 PGND1 G G Power ground for the AVS switcher 19 PGND1 G G Power ground for the AVS switcher 20 SW1 P P AVS Switcher switch node; connected to inductor 21 PVDD1 P P Battery supply voltage for the AVS switcher 22 VDD_D P P Battery supply voltage for digital 23 VDD_A P P Battery supply voltage for analog 24 NC 25 PVDD2 P P Battery supply voltage for the DVS switcher 26 SW2 P P DVS Switcher switch node; connected to inductor 27 PGND2 G G Power ground for the DVS switcher 28 PGND2 G G Power ground for the DVS switcher 29 PGND2 G G Power ground for the DVS switcher 30 FB2 P P DVS switcher feedback 31 NC 32 SCAN 33 VPWELL P P P-well bias voltage 34 NC 35 VNWELL P P N-well bias voltage 36 NC A: Analog Pin D: Digital Pin I: Input Pin O: Output Pin I/O: Input/Output Pin P: Power Pin G: Ground Pin Ordering Information Voltage Option Order Number Package Marking Supplied As LP5551SQ LP5551SQ 1000 units, Tape-and-Reel LP5551SQX LP5551SQ 4500 units, Tape-and-Reel *Released. Samples available. www.national.com 4 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD_A, VDD_D, PVDD1, and -0.3 to + 6.0V PVDD2 LDO1, LDO2, LDO3, LDO4, -0.3 to VDD_A + 0.3V VNWELL to GND, VPwell, ENABLE, RESETN, FB1, FB2, SW_AVS, SW_DVS,GP0, GP1, GP2, and GP3 SPWI, SCLK, PWROK -0.3 to VDD_D + 0.3V GND, PGND1, PGND2, to GND ±0.3V SLUG Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Continuous Power Dissipation (PD-MAX) (Note 5) Operating Ratings (Note 4) 2.0kV (Notes 1, 2) VDD_A, VDD_D, PVDD1, and PVDD2 Junction Temperature (TJ) Range Ambient Temperature (TA) Range(Note 5) Thermal Properties 2.7 V to 5.5 V −40°C to +125°C −40°C to +85°C (Note 6) Junction-to-Ambient Thermal Resistance (θJA) 150°C -65°C to 150°C TBD W 39.8°C/W General Electrical Characteristics Unless otherwise noted, VDD_A, _D , VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8, 9) Symbol Parameter Conditions Min IQ Shutdown Supply current VDD_A, _D, PVDD1,2 = 3.6 V, all circuits off. Typ Max Units 0.44 4 µA 1 12 µA -40°C ≤ TJ ≤ 125°C VDD_A, _D, PVDD1,2 = 3.6 V, all circuits off. -40°C ≤ TJ ≤ 85°C Sleep State Supply Current VDD_A, _D ,VPVDD1,2= 3.6 V, LDO3 on, LDO2 on (no load). All other circuits off. 135 186 µA Acitve State Supply Current VDD_A, _D, VPVDD1,2 = 3.6 V, all outputs on, no load 431 742 µA UVLO high Under Voltage Lockout, high threshold UVLO low Under Voltage Lockout, low threshold TSD Thermal Shutdown Threshold 160 Thermal Shutdown Hysteresis 10 2.7 2.5 °C LDO1 (PLL/Fixed Voltage) Characteristics Unless otherwise noted, VDD_A, _D, VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol VOUT Accuracy VOUT Range IOUT IQ Parameter Output Voltage Conditions IOUT = 50 mA, VOUT = 1.2 V, 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Programmable Output Voltage Programming Resolution=100 mV Range Rated Output Current 2.7 V ≤ VDD_A, _D ,PVDD1,2≤ 5.5 V Output Current Limit VOUT = 0 V Quiescent Current IOUT = 0 mA(Note 11) Min Typ Max Units -3.5% 1.2 3.1% V 0.7 1.2 2.2 V 100 mA 0 347 5 35 µA www.national.com LP5551 Maximum Lead Temperature (Soldering) ESD Rating (Note 3) Human Body Model: All pins Absolute Maximum Ratings (Notes 1, 2) LP5551 Symbol ΔVOUT Parameter Line Regulation Conditions Min 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V, Typ Max Units -0.083 0.316 %/V -0.013 0.013 %/mA IOUT = 50 mA Load Regulation VDD_A, _D, VPVDD1,2 = 3.6 V, 1 mA ≤ IOUT ≤ 100 mA Line Transient Regulation 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V, 27 mV Load Transient Regulation TRISE,FALL = 10 µs VDD_A, _D, VPVDD1,2= 3.6 V, 86 mV 10 mA ≤ IOUT ≤ 90 mA, TRISE,FALL = 100 ns eN PSRR Output Noise Voltage 10 Hz ≤ f ≤ 100 kHz, 0.103 COUT = 2.2 µF Power Supply Ripple Rejection f = 1 kHz, Ratio COUT = 2.2 µF f = 10 kHz, mVRM S 56 dB 36 dB COUT = 2.2 µF COUT Output Capacitance 0 mA ≤ IOUT ≤ 100 mA Output Capacitor ESR tSTART-UP 1 2.2 5 Start-Up Time from Shut-down COUT = 1 µF, 20 µF 500 mΩ 54 µs IOUT = 100 mA LDO2 (I/O Voltage) Characteristics Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6 V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol Parameter VOUT Accuracy Output Voltage VOUT Range IOUT Conditions IOUT = 125 mA, VOUT = 3.3 V, 3.6 V ≤ VDD_A, _D ≤ 5.5 V Programmable Output Voltage 1.5-2.3 V =100 mV step, 2.5 V, 2.8 V, Range 3.0 V and 3.3 V Rated Output Current 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Output Current Limit VOUT = 0V Min Typ Max Units -3.7% 3.3 2.8% V 1.5 3.3 3.3 V 250 mA 0 615 Dropout Voltage(Note 10) IOUT = 125 mA 65 IQ Quiescent Current IOUT = 0 mA (Note 11) 55 ΔVOUT Line Regulation 3.6 V ≤ VDD_A, _D ≤ 5.5 V, 192 mV µA -0.08 0.312 %/V -0.018 0.018 %/mA IOUT = 125 mA Load Regulation VDD_A, _D, VPVDD1,2 = 3.6 V, 1 mA ≤ IOUT ≤ 250 mA Line Transient Regulation 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V, 24 mV Load Transient Regulation TRISE,FALL = 10 us VDD_A, _D, VPVDD1,2 = 3.6 V, 246 mV 25 mA ≤ IOUT ≤ 225 mA, TRISE,FALL = 100 ns eN PSRR Output Noise Voltage 10 Hz ≤ f ≤ 100 kHz, COUT = 4.7 µF Power Supply Ripple Rejection f = 1 kHz, Ratio COUT = 4.7 µF f = 10 kHz, 46 34 COUT = 4.7 µF www.national.com 0.120 6 mVRM S dB Parameter Conditions COUT Output Capacitance 0 mA ≤ IOUT ≤ 250 mA Output Capacitor ESR tSTART-UP Min Typ 2 4.7 5 Start-Up Time from Shut-down COUT = 4.7 µF, IOUT = 250 mA Max Units 20 µF 500 mΩ 144 µs LDO3 (Memory Retention Voltage) Characteristics Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol Parameter Conditions VOFFSET Active State Buffer offset (= VO3-VFB) Output 25 mA≤IOUT ≤ 50 mA, Min Typ Max 0 12 82 Units -3.6% 1.2 3.6% V 0.6 1.2 1.35 V Active mode, 33 44 µA IOUT = 10 µA (Note 11) Sleep mode, 10 16 µA mA mV VDD_A, _D, VPVDD1,2 = 3.6V, AVS switcher VOUT = 1.2 V, 200 mA ≤ AVS switcher IOUT ≤ 300 mA VOUT Accuracy VOUT Range IQ Sleep state: Memory retention voltage regulation IOUT = 5 mA,VOUT = 1.2 V, 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Programmable Output Voltage Programming Resolution=50 mV Range (Sleep state) Quiescent Current IOUT = 10 µA (Note 11) Rated Output Current, Active state 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V 50 Rated Output Current, Sleep state 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V 5 Output Current Limit, Active state VOUT = 0 V eN Output Voltage Noise 10 Hz ≤ f ≤ 100 kHz, PSRR COUT = 1µF Power Supply Ripple Rejection f = 217 Hz, COUT = 1.0 µF Ratio COUT Output Capacitance IOUT 397 0 mA ≤ IOUT ≤ 5 mA Output Capacitor ESR 0.0158 mVRMS 36 0.7 1 5 dB 2.2 µF 500 mΩ LDO4 Characteristics Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol Parameter VOUT Accuracy Output Voltage VOUT Range IOUT IQ Conditions IOUT = 125 mA, VOUT = 3.3 V, 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Programmable Output Voltage 1.5-2.3 V =100 mV step, 2.5 V, 2.8V, Range 3.0 V and 3.3 V Min Typ Max Units -3.7% 3.3 3.1% V 1.5 3.3 3.3 V 250 mA Rated Output Current 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Output Current Limit VOUT = 0 V Dropout Voltage(Note 10) IOUT = 125 mA 65 Quiescent Current IOUT = 0 mA (Note 11) 55 0 629 7 246 mV µA www.national.com LP5551 Symbol LP5551 Symbol Parameter Conditions Min ΔVOUT Line Regulation 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V, Typ Max Units -0.081 0.306 %/V -0.018 0.018 %/mA IOUT = 125 mA Load Regulation VIN = 3.6 V, 1 mA ≤ IOUT ≤ 250 mA Line Transient Regulation 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V, 24 mV Load Transient Regulation TRISE,FALL = 10 us VDD_A, _D, VPVDD1,2 = 3.6 V, 246 mV 25 mA ≤ IOUT ≤ 225 mA, TRISE,FALL = 100 ns eN PSRR Output Noise Voltage 10 Hz ≤ f ≤ 100 kHz, 0.120 COUT = 4.7 µF Power Supply Ripple Rejection f = 1 kHz, Ratio COUT = 4.7 µF f = 10 kHz, mVRM S 46 dB 34 COUT = 4.7 µF COUT Output Capacitance 0 mA ≤ IOUT ≤ 250 mA Output Capacitor ESR tSTART-UP 2 4.7 5 Start-Up Time from Shut-down COUT = 4.7 µF, IOUT = 250 mA 20 µF 500 mΩ 144 µs AVS/DVS Switcher Characteristics Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol Parameter VOUT Accuracy Output Voltage Conditions IOUT = 200 mA, VOUT = 1.2 V, Min Typ Max Units -4.1% 1.2 4.3% V 0.6 1.2 1.2 V VOUT Range VDD_A, _D, VPVDD1,2 = 3.6 V Programmable Output Voltage Programming Resolution = 4.7 mV Range ΔVOUT Line regulation 2.7V < VDD_A, _D, VPVDD1,2 <5.5 V, IOUT = 10 mA 0.18 %/V Load regulation VDD_A, _D, VPVDD1,2 = 3.6 V IOUT = 100-300 mA 0.011 %/mA IQ Quiescent current consumption IOUT = 0 mA 15 RDSON(P) P-FET resistance VDD_A, _D, VPVDD1,2 = VGS = 3.6 V 425 690 mΩ RDSON(N) N-FET resistance VDD_A, _D, VPVDD1,2 = VGS = 3.6 V 345 635 mΩ ILIM Switch peak current limit 2.7 V < VDD_A, _D <5.5 V 350 520 750 mA fOSC Internal oscillator frequency PWM-mode 805 1000 1125 kHz COUT Output Capacitance 0 mA ≤ IOUT ≤ 300 mA Output Capacitor ESR L Inductor inductance RVFB VFB pin resistance to ground www.national.com 22 5 0 mA ≤ IOUT ≤ 300 mA µF 500 4.7 150 8 µA mΩ µH 440 kΩ Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol Parameter Conditions Min VOFFSET Accuracy Output Voltage Offset Tolerance VAVS = 1.2 V VOFFSET = -0.3 V Iout = 10 µA -0.363 -0.3 Typ Max Units -0.266 V 2.7 ≤ VDD_A, _D, PVDD1,2 ≤ 5.5 V Line Regulation IOUT = 10 uA,VOFFSET = -0.315 0.321 %/V Load Regulation VDD_A, _D, PVDD1,2 = 3.6 V VAVS = 1.2 V -0.107 %/mA VOFFSET Range Programmable Output Voltage Offset: Referenced to VAVS Programming Resolution: See Register Table -0.315 0 IQ Quiescent Current ISOURCE/SINK Output Sourcing and Sinking Capability VDD_A, _D, PVDD1,2 = 3.6 V, VOFFSET = 1 V VOFFSET > VOFFSET(NOM) - 15 mV Steady State 3 ISC (SOURCE) Output Source Short Circuit Limit VDD_A, _D, PVDD1,2 = 3.6 V, VNWELL = 0 V Steady State 42 mA ISC (SINK) Output Sink Short Circuit Limit VDD_A, _D, PVDD1,2 = 3.6 V, VNWELL = VDD_A Steady State 65 mA CLOAD Output Capacitance Of Load 0 µA ≤IOUT ≤ 3 uA 5 nF 2.7 V ≤ VDD_A, _D, PVDD1,2 ≤ 5.5 V 0.1 uA ≤ IOUT ≤ 10 uA 1 50 V uA mA 0.1 1 P-Well Characteristics Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol Parameter Conditions Min Typ Max Units VOUT Accuracy Output Voltage Tolerance VOUT = 0 V IOUT = 10 µA -0.035 0 0.035 V 2.7 ≤ VDD_A, _D, PVDD1,2 ≤ 5.5 V Bias Current Control bits = 00 Line Regulation IOUT = 10 uA VOUT = 0.3 V 0.159 %/V VDD_A, _D, PVDD1,2 = 3.6 V VOUT = 0.3 V 0.011 %/µA 2.7V ≤ VDD_A, _D, PVDD1,2 ≤ 5.5 V Load Regulation 0.1 uA ≤ IOUT ≤ 10 uA VOUT Range Programmable Output Voltage Offset: Referenced to Ground 0 mA ≤ IOUT ≤ 10 uA Programming Resolution: See Register Table IQ Quiescent Current IOUT = 0, P-well Bias Current Control bits = 00 9 -1 0 0.3 V 150 270 uA www.national.com LP5551 N-Well Bias Characteristics LP5551 Symbol Parameter Conditions Min ISINK Output Sinking Capability VDD_A, _D, PVDD1,2 = 3.6 V Bias Current Control bits = 00 VOUT > VOUT(NOM) - 15 mV(Note 12) 8 VDD_A, _D, PVDD1,2 = 3.6 V Bias Current Control bits = 01 VOUT > VOUT(NOM) - 15 mV(Note 12) 36 VDD_A, _D, PVDD1,2 = 3.6 V Bias Current Control bits = 10 VOUT > VOUT(NOM) - 15 mV(Note 12) 52 VDD_A, _D, PVDD1,2 = 3.6 V Bias Current Control bits = 11 VOUT > VOUT(NOM) - 15 mV(Note 12) 80 Typ Max Units uA ISOURCE Output Source Capability VDD_A, _D, PVDD1,2 = 2.7 V 100 CLOAD Output Capacitance of Load 0µA ≤ IOUT ≤ 3 uA 0.1 uA 1 5 nF Logic and Control Inputs Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8, 9) Symbol Parameter Conditions PWICLOCK Rated frequency VIL Input Low Level VIH Input High Level Min Typ Max Units 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V 15 MHz ENABLE, RESETN, SPWI, SCLK 2.7 0.4 V V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V ENABLE, RESETN 2.7 V ≤ VDD_A, _D, V 2 VPVDD1,2 ≤ 5.5 V VIH_PWI Input High Level, PWI SPWI, SCLK, 1.5 V ≤VO2 ≤ 3.3 V IIL Logic Input Current V VO2-0.4V ENABLE, RESETN, 0 V ≤ VDD_A, _D, -5 5 µA SPWI, SCLK, 1.5 V ≤ VO2 ≤ 3.3 V -5 15 µA 2 MΩ VPVDD1,2 ≤ 5.5 V IIL_PWI Logic Input Current, PWI RPD_PWI Pull-down resistance for PWI signals TEN_LOW Minimum low pulse width to enter STARTUP state 0.5 ENABLE pulsed high - low - high 1 10 µsec Logic and Control Outputs Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8, 9) Symbol Parameter Conditions Min Typ Max Units VOL Output low level PWROK, GPOx, SPWI, 0.4 V VOH Output high level PWROK, GPOx, ISOURCE ≤ 1 mA VBAT1-0.4V V VOH_PWI Output high level, PWI SPWI, ISOURCE ≤ 1 mA V ISINK ≤ 1 mA VO2-0.4V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θJA, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at TJ=140°C (typ.). www.national.com 10 Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 6: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet. Note 7: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 8: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Note 9: Guaranteed by design. Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.7V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V Note 11: Quiescent current for LDO1, LDO2, LDO3, and LDO4 do not include shared functional blocks such as the bandgap reference. Note 12: The output voltage is guaranteed not to drop more than 15 mV (VOUT < VOUT(NOM) - 15 mV) while sinking the specified current. 11 www.national.com LP5551 Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP) (AN-1187). LP5551 Simplified Functional Diagram 20172132 FIGURE 5. Simplified Functional Diagram www.national.com 12 LP5551 Typical Performance Characteristics Unless otherwise stated: VIN=3.6V IQ vs. VIN Sleep, no load on LDO3 IQ vs. VIN Shutdown 20172104 20172105 Start-up Sequence All Outputs at Maximum Rated Load Line Transient Response VOSW, VO3 20172106 20172109 Line Transient Response VO1, VO2/4 Load Transient Response VO2/4 20172154 20172153 13 www.national.com LP5551 Load Transient Resoponse VO1 LDO1 PSRR 20172155 20172157 LDO2/4 PSRR LDO3 PSRR 20172158 20172159 Switching Frequency vs. VIN Load Transient Response AVS/DVS Switcher, Automatic PWM/PFM Transition 20172113 20172110 www.national.com 14 LP5551 Load Trainsiet Response AVS/DVS Switcher, PWM only Load Transient Response AVS/DVS Switcher, PFM only 20172114 20172115 VOUT Transient Response Min to Max Transient VOUT Transient Response Max to Min Transient 20172116 20172117 Switch Current Limit vs. VIN Efficiency vs. Load (Switcher) 20172118 20172119 15 www.national.com LP5551 Switching Waveforms PWM Switching Waveforms PFM 20172120 20172121 LP5551 PWI Register Map The PWI standard supports sixteen 8-bit registers on the PWI slave. The table below summarizes these registers and shows default register bit values after reset. The following sub-sections provide additional detail on the use of each individual register. Summary Register Address Register Name Register Usage Type 7 6 5 4 3 2 1 0 0x0 R0 Core voltage R/W 0 1 1 1 1 1 1 1 0x1 R1 Unused R/W - - - - - - - - 0x2 R2 Memory retention voltage R/W 0 1 1 0 0 - - - 0x3 R3 Status register R/O 0 0 0 0 1 1 1 1 0x4 R4 PWI version number R/O 0 0 0 0 0 0 0 1 0x5 R5 N-well Bias R/W 0 0 0 0 0 0 - - 0x6 R6 P-well Bias R/W 0 0 0 0 0 0 - - 0x7 R7 LDO2 voltage R/W 0 1 1 1 1 - - - 0x8 R8 LDO1 voltage R/W 0 0 1 0 1 - - - 0x9 R9 PFM/PWM force R/W 0 0 - - - - - - 0xA R10 SW_DVS voltage R/W - - - - - - - - 0xB R11 Enable Control R/W - - 1 1 1 1 1 1 0xC R12 LDO 4 voltage R/W 0 1 1 1 1 - - - 0xD R13 GPO Control R/W 0 0 0 0 0 0 0 0 0xE R14 Reserved R/W - - - - - - - - 0xF R15 Reserved R/W - - - - - - - - R0 - Core Voltage Register Address 0x0 Type R/W Reset Default 8h’7F www.national.com 16 Reset Default Value Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:0 Voltage Core voltage value. Default value is in bold. Voltage Data Code [7:0] Voltage Value (V) 7h’00 0.6 7h’xx Linear scaling 7h’7f 1.2 (default) R1 - Unused Register Address 0x1 Type R/W Reset Default 8h’00 Bit Field Name Description or Comment 7:0 Unused Write transactions to this register are ignored. Read transactions will return a “No Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification). R2 – VO3 Voltage Register (Memory Retention Voltage) Address 0x2 Type R/W Reset Default 8h’60 Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h’0 0.6 4h’1 0.65 4h’2 0.7 4h’3 0.75 4h’4 0.8 4h’5 0.85 4h’6 0.9 4h’7 0.95 4h’8 1 4h’9 1.05 4h’A 1.1 4h’B 1.15 4h’C 1.20 (default) 4h’D 1.25 4h’E 1.3 4h’F 1.35 These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into these bits using the Register Write command is ignored. 17 www.national.com LP5551 Bit LP5551 R3 - Status Register Address 0x3 Type Read Only Reset Default 8h’0F Bit Field Name Description or Comment 7 Reserved Reserved, read returns 0 6 Reserved Reserved, read returns 0 5 User Bit Unused, read returns 0 4 User Bit Unused, read returns 0 3 Fixed OK Unused, read returns 1 2 IO OK Unused, read returns 1 1 Memory OK Unused, read returns 1 0 Core OK Unused, read returns 1 R4 - PWI Version Number Register Address 0x4 Type Read Only Reset Default 8h’01 Bit Field Name Description or Comment 7:0 Version Read transaction will return 8h’01 indicating PWI 1.0 specification. Write transactions to this register are ignored. R5 - N-Well Bias Register Address 0x5 Type R/W Reset Default 8h’00 Bit Field Name Description or Comment 7 Sign 1: Negative offset 0: Positive offset 6:2 Voltage Sign Data Code [7] Voltage Data Code [6:2] Voltage Offset from core voltage 0 5h’19 – 5h’1f 1V 5h’01 – 5h’18 0.042 - 1 V, 0.042 V steps 5h’00 Active clamp to SW_AVS (default) 5h’00 0V 5h’01 – 5h’0f -0.021 – -0.315V, -0.021 V steps 5h’10 –5h’1f -0.315 V 1 0:1 Unused R6 - P-Well Bias Register Address 0x6 Type R/W Reset Default 8h’00 www.national.com 18 LP5551 Bit Field Name Description or Comment 7 Sign 1: Negative offset 0: Positive offset 6:2 Voltage Sign Data Code [7] Voltage Data Code [6:2] Voltage Offset from ground 0 5h’10 –5h’1f 0.3 V 5h’01 – 5h’0f 0.021 – 0.3V, 0.021 V steps 5h’00 Active clamp to ground (default) 5h’00 0V 5h’01 – 5h’18 -0.042 - -1 V, -0.042 V steps 5h’19 – 5h’1f -1 V 1 0:1 Unused R7 – VO2 Voltage Register (I/O Voltage) Address 0x7 Type R/W Reset Default 8h’78 Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h’0 1.5 4h’1 1.5 4h’2 1.5 4h’3 1.5 4h’4 1.6 4h’5 1.7 4h’6 1.8 4h’7 1.9 4h’8 2 4h’9 2.1 4h’A 2.2 4h’B 2.3 4h’C 2.5 4h’D 2.8 4h’E 3 4h’F 3.3 (default) These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into these bits using the Register Write command is ignored. R8 – VO1 Voltage Register (PLL/Fixed Voltage) Address 0x8 Type R/W Reset Default 8h’28 19 www.national.com LP5551 Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ’0’. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h’0 0.7 4h’1 0.8 4h’2 0.9 4h’3 1 4h’4 1.1 4h’5 1.2 (default) 4h’6 1.3 4h’7 1.4 4h’8 1.5 4h’9 1.6 4h’A 1.7 4h’B 1.8 4h’C 1.9 4h’D 2 4h’E 2.1 4h’F 2.2 These bits are fixed to ‘0’. Reading these bits will result in a 3b’000. Any data written into these bits using the Register Write command is ignored. R9– PFM/PWM Force Register Address 0x9 Type R/W Reset Default 8h’00 Bit Field Name Description or Comment 7:4 Unused These bits are fixed to ‘0’. Reading these bits will result in a ‘000000’. Any data written into these bits using the Register Write command is ignored. 3:2 AVS PFM/ PWM Force 1:0 DVS PFM/ PWM Force PFM Force (bit 3) PWM Force (bit 2) Automatic Transition 0 0 Automatic Transition 1 1 Forced PFM Mode 1 0 Forced PWM Mode 0 1 PFM Force (bit 1) PWM Force (bit 0) Automatic Transition 0 0 Automatic Transition 1 1 Forced PFM Mode 1 0 Forced PWM Mode 0 1 R10 – SW_DVS Voltage Register Address 0xA Type R/W Reset Default 8h’7F www.national.com 20 Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:0 Voltage DVS voltage value. Default value is in bold. Voltage Data Code [6:0] Voltage Value (V) 7h’00 0.6 7h’xx Linear scaling 7h’7f 1.2 (default) R11 – Enable Control Register Address 0xB Type R/W Reset Default 8h’3F Bit Field Name 7:6 Unused 5 R10 Enable (DVS Switcher) 4 R9 Enable (LDO 4) 3 R8 Enable (LDO 1) 2 R6 Enable (P-Well bias) Description or Comment 1: DVS switching regulator is enabled 0: DVS switching is disabled 1: LDO 4 regulator is enabled 0: LDO 4 regulator is disabled 1: LDO 1 regulator is enabled 0: LDO 1 regulator is disabled 1: P-Well bias is enabled 0: P-Well bias is clamped to ground <which ground?> 1 R5 Enable (N-Well bias) 1: N-Well bias is enabled 0: N-Well bias tracks register R0 (AVS switcher voltage) 0 R2 Enable (Memory Retention) 1: Memory Retention regulator is enabled 0: Memory Retention regulator is disabled R12 – LDO4 Voltage Register Address 0xC Type R/W Reset Default 8h’78 21 www.national.com LP5551 Bit LP5551 Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Voltage Data Code [6:3] Voltage Value (volts) 4h’0 1.5 4h’1 1.5 4h’2 1.5 4h’3 1.5 4h’4 1.6 4h’5 1.7 4h’6 1.8 4h’7 1.9 4h’8 2 4h’9 2.1 4h’A 2.2 4h’B 2.3 4h’C 2.5 4h’D 2.8 4h’E 3 4h’F 3.3 (default) Unused R13 – GPO Control Address 0xD Type R/W Reset Default 8h’00 Bit Field Name 7:6 Unused 5:4 P-Well Sink Current Control Description or Comment These bits set the maximum sink current capability for the P-Well regulator bit 5 bit 4 Nominal 0 0 36 uA 0 1 52 uA 1 0 80 uA 1 1 3 GPO_3 control Drives high to VDD_D 2 GPO_2 control Drives high to VDD_D 1 GPO_1 control Drives high to VDD_D 0 GPO_0 control Drives high to VDD_D R14 – Reserved Address 0xE Type R/W Reset Default 8h’00 www.national.com 22 Field Name Description or Comment 7:0 Unused Write transactions to this register are ignored. Read transactions will return a “No Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification) frame. 23 www.national.com LP5551 Bit LP5551 Type R/W Reset Default 8h'00 R15 – Manufacturer Register Adress 0xF Bit Field Name Description or Comment 7:0 Reserved Do not write to this register www.national.com 24 their default levels. LP5551 can be turned off by supplying the Shutdown command over PWI, or by setting ENABLE and/or RESETN to '0'. The LP5551 can be switched to the Sleep state by issuing the Sleep command. In the Sleep state the core voltage regulator is off, but the PWROK output is still ‘1’. The memory voltage regulator (VO3) provides the programmed memory retention voltage. LDO1 and LDO2 are on. The LP5551 can be activated from the Sleep state by giving the Wake-up command. This resumes the last programmed Active state configuration. The device can also be switched off by giving the Shutdown command, or by setting ENABLE and/or RESETN to ‘0’ In the Shutdown-state all output voltages are ‘0’, and PWROK-signal is ‘0’ as well. The LP5551 can exit the Shutdown-state if either ENABLE or RESETN is ‘0’. In either case the device moves to the Start-up state. See Figure 8. Figure 6 shows the LP5551 state diagram. The figure assumes that supply voltage to the regulator IC is in the valid range. DEVICE INFORMATION The LP5551 is a PowerWise Interface (PWI) compliant power management unit (PMU) for application or baseband processors in mobile phones or other portable equipment. It operates cooperatively with processors using National Semiconductor’s Advanced Power Controller (APC) to provide Adaptive or Dynamic Voltage Scaling (AVS, DVS) which drastically improves processor efficiencies compared to conventional power delivery methods. The LP5551 consists of a high efficiency switching DC/DC buck converter to supply the AVS or DVS voltage domain, three LDOs for supplying the logic, PLL, and memory, and PWI registers and logic. OPERATION STATE DIAGRAM The LP5551 has four operating states: Start-up, Active, Sleep and Standby. The Start-up state is the default state after reset. All regulators are off and PWROK output is ‘0’. The device will power up when the external enable-input is pulled high. After the powerup sequence LP5551 enters the Active state. In the Active state all regulators are on and PWROK-output is ‘1’. Immediately after Start-up the output voltages are at 20172145 FIGURE 6. LP5551 State Diagram 25 www.national.com LP5551 Operation Description LP5551 modulation (PFM). In PWM the converter switches at 1MHz. Each period can be split into two cycles. During the first cycle, the high-side switch is on and the low-side switch is off, therefore the inductor current is rising. In the second cycle, the high-side switch is off and the low-side switch is on causing the inductor current to decrease. The output ripple voltage is lowest in PWM mode Figure 7. As the load current decreases, the converter efficiency becomes worse due to the increased percentage of overhead current needed to operate in PWM mode. The LP5551 can operate in PFM mode to increase efficiency at low loads. By default, the part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The inductor valley current goes below 0 A B. The peak PMOS switch current drops below the IMODE level: VOLTAGE SCALING The LP5551 is designed to be used in a voltage scaling system to lower the power dissipation of baseband or application processors in mobile phones or other portable equipment. By scaling supply voltage with the clock frequency of a processor, dramatic power savings can be achieved. Two types of voltage scaling are supported, dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS). DVS systems switch between pre-characterized voltages which are paired to clock frequencies used for frequency scaling in the processor. AVS systems track the processor performance and optimize the supply voltage to the required performance. AVS is a closed loop system that provides process and temperature compensation such that for any given processor, temperature, or clock frequency, the minimum supply voltage is delivered. DIGITALLY CONTROLLED VOLTAGE SCALING The LP5551 delivers fast, controlled voltage scaling transients with the help of a digital state machine. The state machine automatically optimizes the control loop in the LP5551 switching regulator to provide large signal transients with minimal over- and undershoot. This is an important characteristic for voltage scaling systems that rely on minimal over- and undershoot to set voltages as low as possible and save energy. During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typ) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The peak current in PFM mode is: LARGE SIGNAL TRANSIENT RESPONSE The switching converter in the LP5551 is designed to work in a voltage scaling system. This requires that the converter has a well controlled large signal transient response. Specifically, the under- and over-shoots have to be minimal or zero while maintaining settling times less than 100 usec. Typical response plots are shown in the Typical Performance section. PowerWise™ INTERFACE To support DVS and AVS, the LP5551 is programmable via the low power, 2 wire PowerWise Interface (PWI). This serial interface controls the various voltages and states of all the regulators in the LP5551. In particular, the switching regulator voltage can be controlled between 0.6V and 1.2V in 128 steps (linear scaling). This high resolution voltage control affords accurate temperature and process compensation in AVS. The LDO voltages can also be set, however they are not intended to be dynamic in operation. The LP5551 supports the full command set as described in PWI 1.0 specification: • • • • • • • • • Core Voltage Adjust Reset Sleep Shutdown Wakeup Register Read Register Write Authenticate Synchronize PWM/PFM OPERATION The switching converter in the LP5551 has two modes of operation: pulse width modulation (PWM) and pulse frequency www.national.com 20172103 FIGURE 7. Operation in PFM Mode and Transfer to PWM Mode 26 PWM/PFM FORCE REGISTER (R9) By default, the LP5551 automatically transitions between PFM and PWM to optimize efficiency. The PWM/PFM force register (R9) provides the option to override the automatic transition and force PFM or PWM operation (see R9 – PWM/ PFM Force Register declaration). Note that if the operating mode of the regulator is forced to be PFM then the switch current limit is reduced to 100 mA (50 mA average load current). EN/RESETN The LP5551 can be shutdown via the ENABLE or RESETN pins, or by issuing a shutdown command from PWI. To disable the LP5551 via hardware (as opposed to the PWI shutdown command), pull the ENABLE and/or the RESETN pin (s) low. To enable the LP5551, both the ENABLE and the RESETN pins must be high. Once enabled, the LP5551 engages the power-up sequence and all voltages return to their default values. When using PWI to issue a shutdown command, the PWI will be disabled along with the regulators in the LP5551. To reenable the part, either the ENABLE, RESETN, or both pins must be toggled (high – low – high). The part will then enter the power-up sequence and all voltages will return to their default values. Figure 8 summarizes the ENABLE/RESETN control. The ENABLE and RESETN pins provide flexibility for system control. In larger systems such as a mobile phone, it can be advantageous to enable/disable a subsystem independently. For example, the LP5551 may be powering the applications processor in a mobile phone. The system controller can power down the applications processor via the ENABLE pin, but leave on other subsystems. When the phone is turned off or in a fault condition, the system controller can have a global reset command that is connected to all the subsystems (RESETN for the LP5551). However, if this type of control is not needed, the ENABLE and RESETN pins can be tied together and used as a single enable/disable pin. CURRENT LIMIT The switching converter in the LP5551 detects the peak inductor current and limits it for protection (see Electrical Characteristics table and/or Typical Performance section). To determine the average current limit from the peak current limit, the inductor size, input and output voltage, and switching frequency must be known. The LP5551 is designed to work with a 4.7uH inductor, so: INPUT CAPACITOR The input capacitor to the switching converter supplies the AC switching current drawn from the switching action of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle this current: The power dissipated in the input capacitor is given by: The input capacitor must be rated to handle both the RMS current and the dissipated power. A 22 µF ceramic capacitor is recommended for the LP5551. OUTPUT CAPACITOR The switching converters in the LP5551 are designed to be used with a 22uF ceramic output capacitor. The dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. The output capacitor of the switching converter absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency of the 20172151 FIGURE 8. ENABLE and RESETN operation 27 www.national.com LP5551 INDUCTOR A 4.7uH inductor should be used with the LP5551. The inductor should be rated to handle the peak load current plus the ripple current: Application Information LP5551 ripple current. Ceramic capacitors are predominately used in portable systems and have very low ESR and remain capacitive up to high frequencies. The switcher peak - to - peak output voltage ripple in steady state can be calculated as: LDO LOADING CAPABILITY The LDOs in the LP5551 can regulate to a variety of output voltages, depending on the need of the processor. These voltages can be programmed through the PWI. Table 1 summarizes the parameters of the LP5551 LDOs. LDO INFORMATION The LDOs included in the LP5551 provide static supply voltages for various functions in the processor. Use the following sections to determine loading and external components. TABLE 1. LDO Parameters PWI Register Output voltage range Recommended Maximum Output Current Dropout Voltage (typical) Typical Load LDO1 R8 0.6 V – 2.2 V 100 mA 200 mV PLL LDO2 R7 1.5 V – 3.3 V 250 mA 150 mV I/O LDO3 R2 VOSW + 0.05 V1 50 mA 200 mV Memory/Memory retention 250 mA 150 mV User defined V2 LDO4 R12 0.7 V – 1.35 1.5 V – 3.3 V 1. LDO3 tracks the switching converter output voltage (VOSW) plus a 50 mV offset when the LP5551 is in active state. 2. LDO3 regulates at the set memory retention voltage when the LP5551 is in shutdown state. LDO OUTPUT CAPACITOR ments. The LDOs in the LP5551 are designed to be used with ceramic output capacitors. The dielectric should be X5R, The output capacitor sets a low frequency pole and a high X7R, or comparable material to maintain proper tolerances. frequency zero in the control loop of an LDO. The capacitance Use the following table to choose a suitable output capacitor: and the equivalent series resistance (ESR) of the capacitor must be within a specified range to meet stability requireTABLE 2. Output Capacitor Selection Guide Output Capacitance Range (Recommended Typical Value) ESR range LDO1 1 µF – 20 µF (2.2 µF) 5 mohm – 500 mohm LDO2 2 µF – 20 µF (4.7 µF) 5 mohm – 500 mohm LDO3 0.7 µF – 2.2 µF (1.0 µF) 5 mohm– 500 mohm LDO4 2 µF – 20 µF (4.7 µF) 5 mohm – 500 mohm www.national.com 28 LP5551 BOARD LAYOUT CONSIDERATIONS 20172161 FIGURE 9. Board Layout Design Recommendations for the LP5551 29 www.national.com LP5551 Physical Dimensions inches (millimeters) unless otherwise noted 36-Lead LLP Package NS Package Number SQA36A www.national.com 30 LP5551 Notes 31 www.national.com LP5551 PowerWise™ Technology Compliant Energy Management Unit Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. 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As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. 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