A3907 Low Voltage Voice Coil Motor Driver Features and Benefits Description ▪ WLCSP package for minimum footprint ▪ Ramp control circuit ▪ Fixed I2C logic thresholds ▪ 10-bit D-to-A converter ▪ 100 μA resolution ▪ Low voltage I2C serial interface ▪ Low current draw sleep mode-active low ▪ 2.3 to 5.5 V operation Designed for linear control of small form factor voice coil motors, the A3907 is capable of peak output currents to 102 mA and operating voltages to 5.5 V. Internal circuit protection includes thermal shutdown with hysteresis, flyback clamp diode, and undervoltage monitoring of VDD. Applications: ▪ Camera focus motor Package: 6-Bump Chip Scale Package (suffix CG) Functional Block Diagram 2.3 to 5.5V 1.8 V VDD IOUT Bandgap Ref 1.8 kΩ 1.8 kΩ 10 Bit DAC SDA SCL I2C Serial Interface Control Logic SLEEPZ Timer A3907-DS, Rev. 1 1.2 Ω GND A3907 Low Voltage Voice Coil Motor Driver Selection Guide Part Number A3907ECGTR Packing 4000 pieces per reel Package Bumped wafer-level chip-scale package (WLCSP) Pb-free Pb-free chip with high-temperature solder balls (RoHS compliant) Absolute Maximum Ratings Characteristic Symbol Supply Voltage VDD Logic Input Voltage Range VIN Operating Ambient Temperature TA Notes Range E Rating Unit 6 V –0.3 to VDD + 0.3 V –40 to 85 ºC Junction Temperature TJ(max) 150 ºC Storage Temperature Tstg –40 to 150 ºC Thermal Characteristics Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* On 4-layer PCB based on JEDEC standard Value Unit 64 ºC/W *Additional thermal information available on the Allegro website Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3907 Low Voltage Voice Coil Motor Driver ELECTRICAL CHARACTERISTICS Valid at TA = 25°C, VDD = 2.3 to 5.5 V; unless otherwise noted Characteristics Supply Current Symbol IDD UVLO Enable Threshold VUVLO(th) UVLO Hysteresis VUVLO(hys) Thermal Shutdown Temperature Thermal Shutdown Hysteresis Power-Up Delay TJTSD TJTSD(hys) Test Conditions Sleep Mode (SLEEPZ = low), VDD = 2.3 to 3.5 V Min. Typ. Max. Unit – 0.5 2 mA – < 100 500 nA VDD rising – 2 2.295 V – 100 – mV Temperature increasing – 165 – °C Recovery = TJTSD - TJTSD(hys) tdPO – 15 – °C – 10 – μs D-to-A Converter Resolution Res Target = 100 μA/LSB – 10 – bit Relative Accuracy errINL Code = 64 to 1023, Endpoint method – ±4 – LSB Differential Nonlinearity errDNL Maximum Output Current Gain Error Guaranteed monotonic – – ±1 LSB IMAX Code = 1023 – 102.3 – mA errA TJ = 25°C, Code 64 to 1023, VDD = 2.6 to 3.0 V –10 <3 10 %FS – 0.2 – LSB/°C Gain Error Drift1 ΔerrA Minimum Code Error IOS1 Code = 1 0 1 5 mA Offset Error IOS Code = 64 – 0.5 – mA –10 – 10 % 0.35 – VDD – 0.1 V – 2 – Ω TJ = –40°C to 125°C Output Slew Rate Timer errTS Output Voltage Range VOUT Output On Resistance RDS(on) Relative to target value RSENSE + RSINK, IOUT = 102.3 mA I2C Interface Bus Free Time Between Stop and Start tBUF 1.3 – – μs Hold Time Start Condition tHD:STA 0.6 – – μs Setup Time for Repeated Start Condition tSU:STA 0.6 – – μs SCL Low Time tLOW 1.3 – – μs SCL High Time tHIGH 0.6 – – μs Data Setup Time tSU:DAT 100 – – ns Data Hold Time tHD:DAT 0 900 – ns Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3907 Low Voltage Voice Coil Motor Driver ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, VDD = 2.3 to 5.5 V; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit tSU:STO 0.6 VIL – – – μs – 0.84 V I2C Interface Setup Time for Stop Condition Logic Input (SDA, SCL Pins) Low Level Logic Input (SDA, SCL Pins) High Level VIH 1.26 – – V ¯S¯¯L¯¯E¯¯E¯¯P¯ Pin Input Low Level VSLPINL – – 0.7 V ¯S¯¯L¯¯E¯¯E¯¯P¯ Pin Input High Level VSLPINH Input Hysteresis Logic Input Current 1.5 – – V VHYS SDA and SCL only – 100 – mV μA IIN VIN = 0 V to VDD –1 0 1 SDA Pin Output Voltage VOL ILOAD = 1.5 mA – – 0.36 V SCL Clock Frequency fCLK – – 400 kHz SDA Output Fall Time tOF – – 250 ns 1Assured VIH to VIL by design and characterization, not production tested. I2C Timing Diagram tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF SDA tLOW tHIGH SCL Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3907 Low Voltage Voice Coil Motor Driver Functional Description Output Current Level Control The A3907 output current level, IOUT , is controlled dynamically by programming the D-to-A converter (DAC) value via the I2C serial port. A 10-bit Level Control code, having a decimal equivalent value from 0 through 1023, is clocked into the SDA pin. one continuous time interval, or divided over two sequential time subintervals. When the single-interval method is selected, the total change in IOUT is accomplished over the total time interval determined by the Rate Control code in table 1, calculated as follows: CodeT = |(CodeNewTarget – CodePreviousTarget)| / 2 , The target output current can be calculated by: IOUT = nDAC × 100 μA , (1) where nDAC is the decimal equivalent of the Level Control code. For example, a code of 5 (000001012) sets an output current target of 500 μA. Programming Level Control code 0 disables the output sink drive. In addition, the DAC is automatically set to code 0 at power-up and also at a fault condition on VDD. Output Current Slew Rate Control When a new current level control instruction is received on the SDA input, the A3907 moves to the new target currrent level by incrementing or decrementing through each of the intermediate current levels until it arrives at the new programmed value. The control instruction received at the SDA input includes both the 10-bit Level Control code and a 4-bit Ramp Control code. The Level Control code is used to determine the absolute value of the changes in IOUT (see equation 1), and the Ramp Control code maps to a lookup table of time intervals (represented in table 1). Together, these two codes determine the shape of the current level change function. Step or Ramp Function The A3907 can change to the new target level using either a step or a ramp slew rate function. When a step function is selected, the A3907 moves to the new target level without imposing any additional time delays between DAC updates. To select a step function, program one of the four Ramp Control codes in table 1 that disable the ramp feature. When a ramp function is selected, the A3907 imposes time delays between each DAC update, calculated according to the particular function option selected. To select a ramp function, program one of the twelve Ramp Control codes in table 1 that enable the ramp feature. Single or Dual Subintervals For either the step or the ramp slew rate method, the total change can be accomplished in either (2) and T = CodeT × tdT , (3) where tdT is the delay factor, in table 1. When the dual-subintervals method is selected, the elapsed time for each subinterval is determined separately by the Rate Control code in table 1. The time interval from initiation, T0, to the switchover point, T1, is calculated as follows: CodeSwitchover = |(CodeNewTarget – CodePreviousTarget)| / 2 , (4) and T1 = CodeSwitchover × tdT1 , (5) where tdT1 is the delay factor for the initial time subinterval, in table 1. The current amplitude at the switchover point is calculated based on equation 1, as follows: ISwitchover = (CodeLow + CodeSwitchover ) × 100 μA , (6) where CodeLow is the lesser of CodeNewTarget and CodePreviousTarget . The time interval from the switchover point, T1, until the target current level is reached, T2, is calculated as follows: T2–T1 = CodeSwitchover × tdT2 , (7) where tdT2 is the delay factor for the second time subinterval, in table 1. Output Function Programming Two examples of output level and slew rate programming are shown in figure 1. Both examples are ramp slew rate functions, using the dual-subinterval method. In example A, an increment in IOUT is shown, and example B shows a decrement in IOUT. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3907 Low Voltage Voice Coil Motor Driver Example A • The new target current level is 30 mA, so Level Control code • The A3907 has been previously programmed to Level Control code 100 (11001002), for a target IOUT of 100 × 100 μA = 10 mA (equation 1). • The new target current level is 20 mA, so Level Control code 200 (110010002) is programmed (invert equation 1). • For this example, the slew rate function selected is represented by Ramp Control code 11002 : ramp, dual-subinterval, initial subinterval delay factor 781 ns, second subinterval delay factor 50 μs. 300 (1001011002) is programmed (invert equation 1). • For this example, the slew rate function selected is represented by Ramp Control code 11012 : ramp, dual-subinterval, initial subinterval delay factor 781 ns, second subinterval delay factor 100 μs. • The A3907 determines the switchover point, T2, as follows: CodeSwitchover = |(1000 – 300)|/2 = 350 (equation 2), • The A3907 determines the switchover point, T1, as follows: CodeSwitchover = |(200 – 100)|/2 = 50 (equation 2), T1 = 350 × 0.781 μs = 273 μs (equation 5), IT1 = 350 + 300 × 100 μA = 65 μA (equation 6). T1 = 50 × 0.781 μs = 39 μs (equation 5), IT1 = 50 + 100 × 100 μA = 150 μA (equation 6). • The A3907 determines the target time final point, T2, as follows: • The A3907 determines the target time final point, T1, as follows: CodeSwitchover = |(1000 – 300)|/2 = 350 (equation 2) , CodeSwitchover = |(200 – 100)|/2 = 50 (equation 2) , T2–T1 = 350 × 100 μs = 35 ms (equation 5). T2–T1 = 50 × 50 μs = 2.5 ms (equation 5). T0 T1 Table 1. Slew Rate Function Table Dual Interval Delay Factor (μs) 25 200 20 150 100 T1 T0 tdT 0 0 0 0 0 (ramp feature disabled) 0 0 0 1 0 0 1 0 12.5 0 0 1 1 25 0 1 0 0 50 1000 100 0 6.25 0.5 1.0 1.5 2.0 2.5 10 T1 T2 515 0 0.04 0.5 0.08 1.0 0.10 1.5 0.12 2.0 0.14 2.5 010 Time (ms) Example A T0 T1 0 1 0 1 100 900 0 1 1 0 200 800 0 1 1 1 T3 T2 T1 T0 0 (ramp feature disabled) tdT2 1 0 0 0 1 0 0 1 0 (ramp feature disabled) 1 0 1 0 12.5 1 0 1 1 25 1 1 0 0 1 1 0 1 100 1 1 1 0 200 1 1 1 1 6.25 0.781 0 150 50 T3 tdT1 15 Expanded Below 50 0 (ramp feature disabled) T2 100 80 700 Expanded Below 600 60 500 400 300 40 0 5 10 15 20 25 30 35 200 800 80 20 T1 100 700 0 600 IOUT (mA) Single Interval Timer Bits Settings Level Control Code Slew Rate Method Level Control Code • The A3907 has been previously programmed to Level Control code 1000 (11111010002), for a target IOUT of 1000 × 100 μA = 100 mA (equation 1). T2 250 IOUT (mA) Example B 0 5 1 10 215 203 70 25 4 30 35 5 60 0 Time (ms) Example B Figure 1. Examples of programmed IOUT change Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3907 Low Voltage Voice Coil Motor Driver I2C Interface This is a serial interface that uses two bus lines, SCL and SDA, to access the internal control registers. Data is exchanged between a microcontroller (master) and the A3907 (slave). The clock input to SCL is generated by the master, while SDA functions as either an input or an open drain output, depending on the direction of the data. The I2C input thresholds do not depend on the VDD voltage of the A3907. The levels are fixed at approximately 1V. The fixed levels allow the SDA and SCL lines to be pulled-up to a different logic level than the VDD supply of the 3907. Timing Considerations The control sequence of the communication through the I2C interface is composed of several steps in sequence: 1. Start Condition. Defined by a negative edge on the SDA line, while SCL is high. 2. Address Cycle. 7 bits of address, plus 1 bit to indicate write (0) or read(1), and an acknowledge bit. The address setting is 0x18, 0x1A, 0x1C, or 0x1E. 3. Data Cycles. Write requires 7 bits of address data selecting the internal control register, followed by an acknowledge bit. 4. Stop Condition. Defined by a positive edge on the SDA line, while SCL is high. Except to indicate a Start or Stop condition, SDA must be stable while the clock is high. SDA can only be changed while SCL is low. It is possible for the Start or Stop condition to occur at any time during a data transfer. The A3907 always responds by resetting the data transfer sequence. To indicate a write cycle, the Read/Write bit is set to low. Mulitple writes are allowed. If desired, the readback bit can be set to high to check what was last written. The Acknowledge bit is used by the master to determine if the slave device is responding to its address and data transmissions. When the A3907 decodes the 7-bit address field as a valid address, it responds by pulling SDA low during the ninth clock cycle. During a data write from the master, the A3907 pulls SDA low during the clock cycle that follows the last data byte, in order to indicate that the data has been successfully received. In both cases, the master device must release the SDA line before the ninth clock cycle, in order to allow this handshaking to occur. Slave (A3907) Address Device Identifier 0 0 Control Register MS Byte (I2C Write register) 0 1 R/W 1 X X 0 Control Register MS Byte (I2C Write register) Bit Name Function Bit Name Function 0 D4 DAC 0 T0 Time Setting LSB 1 D5 DAC 1 T1 Time Setting Bit 1 2 D6 DAC 2 T2 Time Setting Bit2 3 D7 DAC 3 T3 Time Setting Bit 3 4 D8 DAC 4 D0 DAC LSB 5 D9 DAC MSB 5 D1 DAC 6 T5 Not used 6 D2 DAC 7 SLEEP 1=Sleep 0=Normal 7 D3 DAC Write Operation Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3907 Low Voltage Voice Coil Motor Driver Output Voltage Range To guarantee the accuracy and linearity of the programmed current, the voltage on the IOUT pin, VOUT , should be greater than 350 mV. The output voltage is a function of the battery voltage, motor resistance, and the programmed load current, IOUT. Clamp Diode When the IC output is turned off, the load inductance causes the output voltage, VOUT , to rise. An internal clamp diode, connected between the IOUT and VDD pins, is integrated into the IC to ensure the output voltage remains at a safe level. ¯S¯¯L ¯¯E ¯¯E¯¯P¯ Pin ¯¯L ¯¯E ¯¯E ¯¯P pin is an active low input. A logic low signal disables The S all of the internal circuitry and prevents the IC from draining battery power. Applications Information Headroom The current may not reach the programmed level if there is not adequate headroom in the output circuit. The IC output voltage must be over 350mV to guarantee normal linear operation. VDD, ILOAD, and RLOAD can be adjusted to ensure the device operates in the linear range. When equation 7 is not satisfied, the load current will be limited by the series impedance and may not reach the programmed level. VDD(min) – RLOAD(max) × IOUT(max) ≥ 350 mV . (7) always be positive for each incremental step. DNL = (IOUT(n+1) – IOUT(n)) / LSB , (8) where (n = 64 to 1023). DNL should be < 1 LSB. Offset Error The measured output current at Level Control code 64, compared to the ideal value according to the transfer function: 6.4 mA. Relative Accuracy (INL) This error is calculated by measuring the worse case deviation from a straight line defined from endpoints. The straight line endpoints are defined by the actual measured values at Level Control code 63 and 1023 (see figure 2). Gain Error The difference between the slopes of the ideal transfer function and the actual transfer function. The gain error is calculated by subtracting the offset error at Level Control code 16 from the actual transfer function. This calculated value is compared to the ideal transfer function and reported as a percentage of the ideal full scale value: 102.3 mA (see figure 3). Differential Nonlinearity (DNL) A measure of the monotonicity of the DAC (see equation 8). The slope of the line must Gain Error Drift The change in slope of the transfer function due to temperature, expressed as LSB / °C. IOUT Errors Defined Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3907 Low Voltage Voice Coil Motor Driver IOUT (mA) 102.3 0 0 64 1023 512 Level Control Code Straight line between measured Codes 64 and 1023 Relative Accuracy (64-1023), Errors exaggerated for clarity Figure 2. Relative Accuracy Offset Error Gain Error IOUT (mA) 102.3 0 Ideal DAC Actual DAC (Errors Exaggerated) Calculated Gain Error, Offset Error Removed 0 63 Level Control Code 1023 Figure 3. Gain Error Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3907 Low Voltage Voice Coil Motor Driver CG Package, 6-Ball WLCSP 1.465±0.020 C B A A B C B A X 17 1 B 1 0.500 0.965±0.020 2 2 0.500 1.000 C All dimensions nominal, not for tooling use Dimensions in millimeters Exact configuration at supplier discretion within limits shown 0.500±0.050 C 6X PCB Layout Reference View 0.05 C X 0.200±0.030 SEATING PLANE A Die orientation mark 0.10 M C A B 0.05 M C 1.000 0.500 B Terminal #A1 mark area C Reference view of typical layout for solder pads All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances 2 0.500 1 C B A 0.233 A 0.233 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A3907 Low Voltage Voice Coil Motor Driver Copyright ©2009-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11