RENESAS HA16163T

HA16163T
Synchronous Phase Shift Full-Bridge Control IC
REJ03F0001-0600
Rev.6.00
Jul 01, 2008
Features
•
•
•
•
•
High frequency operation; oscillator frequency = 2 MHz max.
Full-bridge phase-shift switching circuit with adjustable delay times
Integrated secondary synchronous rectification control with adjustable delay times
Three-level over current protection; pulse by pulse, timer Latch, one shot OCP
Package: TSSOP-20
Application
• 48 V input isolated DC/DC converter
• Primary; Full-bridge circuit topology
• Secondary; current doubler or center-tapped rectification
Illustrative Circuit
+48V
+
–
FET Driver
Vbias
FET
Driver
VCC
FET
Driver
FET
Driver
OUT
-A
OUT
-B
CS
RAMP
FET
Driver
OUT
-C
OUT
-D
OUT
-E
FET Driver
OUT
-F
Optical feedback circuitry
COMP
VREF
GND
FB
RT
SYNC
SS
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 1 of 29
REMOTE
DELAY DELAY DELAY
-1
-2
-3
HA16163T
Pin Arrangement
SYNC
1
20
RT
RAMP
2
19
GND
CS
3
18
OUT-A
COMP
4
17
OUT-B
REMOTE
5
16
OUT-C
FB
6
15
OUT-D
SS
7
14
OUT-E
DELAY-1
8
13
OUT-F
DELAY-2
9
12
VCC
DELAY-3
10
11
VREF
(Top view)
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
SYNC
Pin Function
Synchronization I/O for the oscillator
RAMP
CS
COMP
REMOTE
FB
SS
DELAY-1
DELAY-2
DELAY-3
VREF
VCC
OUT-F
OUT-E
OUT-D
OUT-C
OUT-B
OUT-A
GND
RT
Current sense signal input for the full-bridge control loop
Current sense signal input for OCP
Error amplifier output
Remote on/off control
Voltage feedback input
Timing capacitor for both soft start and timer latch
Delay time adjustor for the full-bridge control signal (OUT-A and B)
Delay time adjustor for the full-bridge control signal (OUT-C and D)
Delay time adjustor for the secondary control signal (OUT-E and F)
5 V/20 mA Output
IC power supply input
Secondary control signal
Secondary control signal
Full-bridge control signal
Full-bridge control signal
Full-bridge control signal
Full-bridge control signal
Ground level for the IC
Timing resistor for the oscillator
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 2 of 29
HA16163T
Block Diagram
VCC
H
5V
Generator
UVL
UVLO
VREF
L
REMOTE
H
VREF
GOOD
L
+
−
ON: 1.417V
OFF: 1.333V
VREF
RT
Start-up
counter
32 clock
Current Ref.
Generator
VREFGOOD
Circuit Bias
VREF
DELAY
OUT-A
Oscillator
DELAY-1
RES
SYNC
SYNC. I/O
VREF
Q
DELAY
Error Amp
VREF
VREF
R
500μ
−
+
FB
OUT-B
DELAY
Q
OUT-C
S
DELAY-2
1.25V
VREF
Comparator
−
+
20k
COMP
10k
− +
1.55V
1.46V
DELAY
OUT-D
0.4V
RAMP
Clamp Circuit
VREF
R
Q
Zero Delay
S
VREFGOOD
4V
10μ
RES
SS
R
Q
S
SS IN
LOCKOUT
SEQ.
DISCHARGE
+
−
PULSE BY PULSE
0.4V
+
−
ONE SHOT
0.6V
CS
VREF
ONE PULSE
87μA
FAULT
LOGIC
LIMIT IN
Zero delay
DELAY
GND
Note that all switches in the block diagram are turned on when control signal is high.
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 3 of 29
OUT-E
DELAY
DELAY-3
VREF
OUT-F
HA16163T
Absolute Maximum Ratings
(Ta = 25°C)
Item
Power supply voltage
Peak output current
DC output current
VREF output current
COMP sink current
DELAY set current
RT set current
VREF terminal voltage
Terminal group 1 voltage
Operating junction temperature
Storage temperature
Notes: 1.
2.
3.
4.
5.
Symbol
Vcc
Ipk-out
Idc-out
Iref-out
Isink-comp
Iset-delay
Iset-rt
Vter-ref
Vter-1
Tj-opr
Tstg
Rating
20
±50
±5
–20
2
0.3
0.3
–0.3 to 6
–0.3 to (Vref +0.3)
–40 to +125
–55 to +150
Unit
V
mA
mA
mA
mA
mA
mA
V
V
°C
°C
Rated voltages are with reference to the GND pin.
Shows the transient current when driving a capacitive load.
For rated currents, inflow to the IC is indicated by (+), and outflow by (–).
VREF pin voltage must not exceed VCC pin voltage.
Terminal group 1 is defined the pins;
REMOTE, CS, RAMP, COMP, FB, SS, RT, SYNC, DELAY-1 to 3, OUT-A to F
6. θja
228°C/W Board condition; Glass epoxy 55 mm × 45 mm × 1.6 mm, 10% wiring density.
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 4 of 29
Note
1
2, 3
3
3
3
3
3
1, 4
1, 5
6
HA16163T
Electrical Characteristics
(Ta = 25°C, Vcc = 12 V, RT = 33 kΩ, Rdelay = 51 kΩ, unless otherwise specified.)
Item
Supply
VREF
Oscillator
SYNC
Remote
Error
amplifier
Min
Typ
Max
Unit
Start threshold
VH
Symbol
9.0
9.8
10.6
V
Shutdown threshold
VL
7.3
7.9
8.5
V
UVLO hysteresis
dVUVL
1.7
1.9
2.1
V
Test Conditions
Start-up current
Is
—
90
150
μA
Vcc = 8.5V
Operating current
Icc
—
7
10
mA
No load on VREF pin
Output voltage
Vref
4.9
5.0
5.1
V
Line regulation
Vref-line
—
0
10
mV
Vcc = 10V to 16V
Load regulation
Vref-load
—
6
20
mV
Iref = –1mA to –20mA
Temperature stability
dVref/dTa
—
±80 *
1
—
ppm/°C
Oscillator frequency
fosc
—
960 *
1
—
kHz
Switching frequency
fsw
412
480
547
kHz
Line stability
fsw-line
–1.5
0
Temperature stability
dfsw/dTa
—
±0.1 *
RT voltage
VRT
2.5
Input threshold
VTH-SYNC
Output high
VOH-SYNC
Output low
Ta = –40 to 105°C
Measured on OUT-A, -B
1.5
%
Vcc = 10V to 16V
—
%/°C
Ta = –40 to 105°C
2.7
2.9
V
2.5
2.85
3.2
V
3.5
4.0
—
V
RSYNC = 33kΩ to GND
VOL-SYNC
—
0.05
0.15
V
RSYNC = 33kΩ to VREF
1
Minimum input pulse
TI-MIN
50
—
—
ns
Output pulse width
TO-SYNC
—
500
—
ns
On threshold voltage
VON
1.374
1.417
1.460
V
Off threshold voltage
VOFF
1.293
1.333
1.373
V
Input bias current
IREMOTE
0
0.4
2
μA
FB input voltage
VFB
1.225
1.250
1.275
V
FB input current
IFB
–1.0
0
1.0
μA
Open-loop DC gain
Av
—
80 *
—
dB
Unity gain bandwidth
BW
—
2*
—
MHz
Output source current
ISOURCE
–610
–430
–350
μA
FB = 0.75V, COMP = 2V
Output sink current
ISINK
2.0
6.5
—
mA
FB = 1.75V, COMP = 2V
Output high voltage
VOH-EO
3.7
3.9
—
V
FB = 0.75V, COMP; open
Output low voltage
VOL-EO
—
0.1
0.4
V
FB = 1.75V, COMP; open
–0.16
–0.07
0.0
V
FB = 0.75V, COMP; open
SS = 1V
Output clamp voltage *
2
VCLAMP-EO
1
1
Notes: 1. Reference values for design. Not 100% tested in production.
2. VCLAMP-EO = VCOMP – SS voltage (1V)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 5 of 29
REMOTE = 2V
FB and COMP are shorted
FB = 1.25V
HA16163T
Electrical Characteristics (cont.)
(Ta = 25°C, Vcc = 12 V, RT = 33 kΩ, Rdelay = 51 kΩ, unless otherwise specified.)
Item
Phase
modulator
Min
Typ
RAMP offset voltage
VRAMP
Symbol
—
0.4 *
RAMP bias current
IRAMP
–5
–0.8
5
μA
RAMP = 0.3V
RAMP sink current
ISINK-RAMP
8
26
—
mA
RAMP = 1V, COMP = 0V
Dmin
—
0* *
Maximum phase shift
Dmax
—
97.0 * *
2
1 4
Max
Unit
—
V
Test Conditions
—
%
RAMP = 1V, COMP = 0V
—
%
RAMP = 0V, COMP = 2.1V
Tpd
—
30
60
ns
COMP = 2.1V
TD1, 2, 3
22
33.5
45
ns
Delay set R = 51k
Terminal voltage
VD1, 2, 3
1.9
2.0
2.1
V
Delay set R = 51k
Source current
ISS
–14
–10
–6
μA
SS = 1V
Discharge current
IRES-SS
5
10
—
mA
Soft-start reset voltage
VRES-SS
0.25
0.40
0.55
V
SS high voltage
VOH-SS
3.9
4.0
4.1
V
DELAY-1, -2, -3 *
Soft start
1 4
Minimum phase shift
Delay to OUT-C, -D *
Delay
1
3
Notes: 1. Reference values for design. Not 100% tested in production.
2. Tpd is defined as;
RAMP
1V
0V
OUT-C/D
5V
0V
50%
50%
Tpd
3. TD1, 2, 3 are defined as;
TD1
TD1
OUT-A
OUT-B
50%
For primary
control
OUT-C
TD2
TD2
OUT-D
OUT-E
For secondary
control
TD3
OUT-F
TD3
4. Maximum/Minimum phase shift is defined as;
T2
OUT-A
D=
× 2 × 100 (%)
T1
T2
OUT-D
T1
OUT-B
T2
OUT-C
T1
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 6 of 29
SS = 1V, REMOTE = 0V
Measured on SS
HA16163T
Electrical Characteristics (cont.)
(Ta = 25°C, Vcc = 12 V, RT = 33 kΩ, Rdelay = 51 kΩ, unless otherwise specified.)
Item
Over
current
protection
Symbol
Pulse-by-pulse current limit
threshold
One-shot OCP threshold
Typ
Max
Unit
0.36
0.40
0.44
V
Test Conditions
VCS-SD
0.54
0.60
0.66
V
Tpd-cs
—
40
80
ns
CS = 0V to 0.47V
Timer latch integration
time
TTL
44
63
82
μs
CS = 0.47V step function,
SS = 0.022μF
High voltage
VOH-OUT
4.3
4.8
—
V
IOUT = –5mA
Low voltage
VOL-OUT
—
0.1
0.4
V
IOUT = 5mA
Rise time
tr
—
5
15
ns
COUT = 33pF
Fall time
tf
—
5
15
ns
COUT = 33pF
TD4
—
3*
—
ns
Delay to OUT pins *
Output
Min
VCS-PP
Timing offset *
1
2
3
Notes: 1. Tpd-cs is defined as;
CS
0.47V
0
50%
OUT-C/D
50%
Tpd-cs
2. TD4 is defined as;
50%
OUT-D
OUT-E
OUT-C
50%
TD4
50%
OUT-F
50%
TD4
3. Reference values for design. Not 100% tested in production.
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 7 of 29
HA16163T
Timing Diagram
Note: All voltage, current, time shown in the diagram is typical value.
Full Bridge and Secondary Control
COMP
COMP/3(internal signal)
RAMP+0.4V
(internal signal)
0.4V
RAMP
TD1
TD1
OUT-A
OUT-B
OUT-C
TD2
TD2
OUT-D
TD3
OUT-E
TD3
OUT-F
VIN
OUT-A
DRIVE
MA
MC
DRIVE
OUT-C
OUT-B
DRIVE
MB
MD
DRIVE
OUT-D
DRIVE
ME
MF
DRIVE
RAMP
OUT-E
External Power Stage
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 8 of 29
OUT-F
HA16163T
Start-up and Shutdown
9.8V
7.9V
VCC
ON
REMOTE
ON
OFF
5V
VREF
0V
RES
(Internal signal)
32 counts
VREFGOOD
High
(Internal signal)
Low
32 counts
4.0V
SS
0V
DISCHARGE
(Internal signal)
High
Low
From Error Amp
COMP
20k
10k
Current information
Comparator
−
+
For Phase Modulation
0.4V
RAMP
Clamp
VREF
4.0V
SS
Iss
10μA
SS IN
Css
Discharge
Soft-start Block
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 9 of 29
HA16163T
Timer Latch and One Shot OCP
0.6V
0.4V
CS
4V
0.4V
3.9V
3.78V
3.9V
SS
0.4V
OUT ENABLE
LOCKOUT
(Internal signal) OUT DISABLE
SEQ.
(Internal signal)
FAULT LOGIC
FOR PHASE MODULATION
3.9V
4V
10μA
RES
3.78V
−
+
0.4V
−
+
SS IN
SS
R
Q
S
Q
R
DISCHARGE
PULSE BY PULSE
ONE SHOT
0.6V
+
−
CS
Q
R
S
SHORT DET.
+
−
S
SEQ.
87μA
0.4V
−
+
R
Q
LIMIT IN
S
VREFGOOD
LOCKOUT
All Flip-flop are initialized by VREFGOOD in turn on period.
OCP Block
SS IN : Voltage detector input of SS pin.
SEQ. : Timer Latch function is not activated when SEQ. signal is Low.
SHORT DET. : Once ONE SHOT comparator detect short current in the power supply, SHORT DET. is High
until SS voltage reaches down to 0.4V.
DISCHARGE : Gate control for SS capasitor reset.
LIMIT IN : One shot OCP input.
LOCKOUT : Lock-out signal for OUT-A to F.
VREFGOOD : System reset signal. VREFGOOD is High when either VREF<4.6V or Remote off mode.
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 10 of 29
HA16163T
Functional Description
Note: All voltage, current, time shown in the diagram is typical value unless otherwise noted.
UVLO
UVLO (Under Voltage Lockout Operation) is a function that halts operation of the IC in the event of a low IC power
supply voltage.
When IC operation is halted, the 5 V internal voltage generation circuit (VREF) halts, and therefore operation of
circuitry using VREF as the operating power supply halts. Circuit blocks other than UVLO use VREF as their
operating power supply. Therefore, the power supply current of the IC becomes equal to the current dissipated by the
UVLO circuit. The following graphs show the relationship between the VCC input current and VCC input voltage, and
between VREF and the VCC input voltage.
ICC
ICC
Is
0
7.9V 8.5V 9.8V 12V
20V
VCC
VREF
5V
0
7.9V
9.8V
20V
VCC
Figure 1
REMOTE
IC outputs (OUT-A through OUT-F) can be halted by means of the REMOTE pin. In this case, the IC output logic
level is low.
In the remote off state, VREF output is not halted, and therefore the current dissipation of the IC does not decrease to
the start-up level. Also, control by means of the REMOTE pin is not possible when the IC has been halted by UVLO.
The soft start capacitance is discharged in the remote off state. Therefore, operation begins from soft start mode when
the next remote on operation is performed. The relationship between the REMOTE pin and the operating mode of the
IC is shown in the following figure.
IC operating
ON
mode
OFF
0V
1.333V 1.417V
Figure 2
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 11 of 29
5V
REMOTE
HA16163T
The remote on and off threshold voltages are provided with hysteresis of 84 mV (typ). Remote control can be
performed by means of analog input as shown in the diagram below as well as by means of logic control. The
following diagram shows an example in which the power supply set input voltage is sensed by means of the REMOTE
pin, and the power supply set start-up voltage is set to 34 V, and the shutdown voltage to 32 V.
VIN
5V(VREF)
VIN(on) = VON(remote) × (R1+R2)/R2
= 1.417V × 24
= 34.008V
HA16163
220k
R1
10k
REMOTE
VIN(off) = VOFF(remote) × (R1+R2)/R2
= 1.333V × 24
= 31.992V
R2
10k
100p
Full-bridge
control
GND
Remote control circuit VIN sense circuit
(logic input)
(analog input)
Power Stage
Figure 3
Start-up Counter
When the VREFGOOD signal (internal signal) goes to the logic low level, the HA16163 starts operating as a controller.
The VREFGOOD signal is created from the REMOTE comparator and VREFGOOD circuit output via a 32-clock startup counter.
VCC
H
UVLO
5V
Generator
UVL
L
REMOTE
ON: 1.417V
OFF: 1.333V
+
−
From Oscillator
Start-up
counter
32 clock
VREF
H
VREF
GOOD
L
VREFGOOD
Circuit Bias
Figure 4
Therefore, the start of IC operation is a 32-count later than UVLO release or the remote on trigger. When the oscillator
frequency is set to 1 MHz, this represents a delay of 32 μs. This delay enables operation to be halted until VREF (5 V)
stabilizes when UVLO is released. Note that the start-up counter operates when VREF rises or when a remote on
operation is performed, but does not operate when VREF falls or when a remote off operation is performed (there is no
logic delay due to the start-up counter).
9.8V
7.9V
VCC
4.6V
4.4V
VREF
32 counts
RES
(Internal signal)
VREFGOOD
(Internal signal)
Start of Operation
operation halted
Figure 5
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Page 12 of 29
HA16163T
Oscillator
The oscillation frequency of the oscillator is set by means of a resistance connected between the RT pin and GND. The
following graph shows the relationship between the external resistance and the oscillation frequency. The typical value
of the oscillation frequency is given by the following equation.
fosc =
1
25 [pF] × RT [Ω] + 150 [ns]
[Hz]
fosc vs. RT
10000
HA16163
fosc (kHz)
SYNC
1000
(2.7 V)
RT
GND
100
RT
10
10
100
RT (kΩ)
1000
Figure 6
Place the resistor for connection to the RT pin as close to the pin as is possible. Please design the pattern so that the
level of cross-talk from other signals is minimized.
Synchronized Operation
Parallel synchronized operation is possible by connecting the SYNC pins of HA16163s. In this case, up to four slave
ICs can be connected to one master IC. A value of at least twice the master RT value should be set for the slave IC RT
values.
(2.7V)
RT
HA16163
HA16163
MASTER
SLAVE
RT SYNC
SYNC RT
GND
GND
(2.7V)
2*RT
HA16163
SLAVE
SYNC RT
(2.7V)
GND
Max. 4 slaves
Figure 7 Parallel Synchronized Operation
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 13 of 29
2*RT
HA16163T
External synchronized operation is possible by supplying a synchronization signal to the SYNC pins of HA16163s. In
this case, a frequency not exceeding 1/2 that of the master clock should be set for the HA16163s.
A maximum master clock frequency of 4 MHz should be used. See the figure below for the input waveform conditions.
HA16163
TTL or CMOS
SLAVE
MASTER
MASTER CLOCK
SYNC RT
(2.7V)
RT
GND
HA16163
SLAVE
SYNC RT
(2.7V)
GND
RT
Figure 8 External Synchronized Operation
TCYCLE
TI-MIN
Item
TCYCLE
TI-MIN
TIL-MIN
VIH-SYNC
VIL-SYNC
TIH-SYNC
TIL-SYNC
TIL-MIN
Figure 9 SYNC Pin Input Conditions
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Page 14 of 29
Input Range
250ns min.
50ns min.
100ns min.
3.2V to Vref
0V to 2.5V
HA16163T
Synchronous Phase Shift Full-Bridge Control
The HA16163 is provided with full-bridge control outputs OUT-A through OUT-D, and secondary-side synchronous
rectification control outputs OUT-E and OUT-F. ZVS (Zero Voltage Switching) can be performed by adjusting timing
delays TD1 and TD2 between the OUT-A through OUT-D outputs by means of an external resistance. OUT-E and OUTF have an output timing suitable for secondary-side full-wave rectification, and so can be used in either current doubler
or center tap applications. The following figure shows full-bridge ZVS + current doubler operation using an ideal
model.
RES pulse
(Internal signal)
SA
TD1
SB
Full-bridge
control switch
(on when high) SC
TD2
SD
Synchronous
SE
rectification
control switch
(on when high) SF
Transformer
primary
both-side
voltage
TD3
VIN
0
–VIN
Transformer
VIN/N
secondary
0
both-side
–VIN/N
voltage
Subinterval:
Time:
1
t0
2
t1
3
t2
4
t3
5
t4
t5
Figure 10
• Subinterval: 1
In interval 1, SA and SD are turned on, and VIN is generated on the transformer primary side. On the transformer
secondary side, a value proportional to the winding ratio is generated, and the primary-side power is transmitted to
the load side.
At this time, secondary-side switch SE is off and SF is on.
L1
VIN
SA
SE
SC
V12
V11
VOUT
Lr
Cr1
SB
SD
Cr2
SF
L2
Subinterval: 1
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HA16163T
• Subinterval: 2
As SD is turned off at point t1, the primary-side current flows into resonant capacitance Cr2. At this time Cr2 is
charged, and therefore the potential of V12 rises. Considering that the exciting current and the L1 and L2 ripple
currents are considerable smaller than Io, the following is an approximate equation for the slope of V12.
dV12 0.5 Io
1
=
⋅
dt
Cr2
N
⋅⋅⋅⋅⋅(1)
[V/s]
Here, N is the ratio of the primary coil to the secondary coil (N = N1/N2), and Io is the output current.
As SE and SF are on, the transformer secondary side is in the shorted state, and the value of the current flowing up
to that time is retained.
L1
VIN
SA
SE
SC
V12
V11
VOUT
Lr
SB
Cr1
SD
Cr2
SF
L2
Subinterval: 2
• Subinterval: 3
SC is turned on at point t2. ZVS operation can be attained by setting the SD off (t2) → SC on (t3) delay to the
optimal value. This delay time can be expressed by equation (2).
TD2 =
N
⋅ Cr2 ⋅ VIN
0.5 Io
⋅⋅⋅⋅⋅(2)
[s]
After SC is turned on, the transformer primary side is in the shorted state, and therefore the current value
immediately after SC was turned on is retained.
L1
VIN
SA
SE
SC
V12
V11
VOUT
Lr
Cr1
SB
SD
Cr2
SF
L2
Subinterval: 3
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HA16163T
• Subinterval: 4
As SA is turned off at point t3, the primary-side current discharges resonant capacitance Cr1, and the potential of
V11 falls. A negative potential is applied to resonant inductor Lr, and a flux reset starts. At this time, since the
series resonance circuit is composed of Cr1 and Lr, the V11 waveform changes to a sine wave. The resonance
frequency is given by equation (3).
fr =
1
2π √(Cr1 ⋅ Lr)
⋅⋅⋅⋅⋅(3)
[Hz]
L1
VIN
SA
SC
SE
V12
V11
VOUT
Lr
Cr1
SB
SD
SF
Cr2
L2
Subinterval: 4
• Subinterval: 5
When synchronous switch SF is turned off at point t4, the current flowing in SF up to that time continues to flow
through the SF body diode. SF turn-off must be performed before completion of the resonant inductor Lr flux reset.
If SF is not off on completion of the Lr flux reset, power transmission will be performed with the transformer
secondary-side shorted, and therefore an excessive current will flow in the transformer primary and secondary sides,
and parts may be damaged.
Also, if the SF body diode is on for a long period, loss will be high. Therefore, optimal timing should be set by
means of the HA16163's delay adjustment pin, DELAY-3.
Lr reset time tr is given by equation (4) when the resonance voltage peak value is within the input voltage.
treset(Lr)|vpp≤VIN =
1 1
⋅
4 fr
= 0.5π √(Cr1 ⋅ Lr)
[s] ⋅⋅⋅⋅⋅(4)
Here, vpp is the resonance voltage peak value.
vpp =
Io 1
⋅
⋅ √(Lr/Cr1)
2 N
⋅⋅⋅⋅⋅(5)
[V]
L1
VIN
SA
SC
SE
VOUT
V12
V11
Lr
Cr1
SB
SD
Cr2
SF
L2
Subinterval: 5
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 17 of 29
HA16163T
• Time: t5
SB is turned on at point t5. The SB switching loss can be minimized by turning on SB when the SB both-side
voltages are at a minimum (when the resonance voltage is at a peak). The SB turn-on timing can be set with TD1 of
the HA16163. The time when the resonance voltage is at a peak is given by equation (4).
From t5 onward, operation is on the same principle as in Subinterval 1 through Subinterval 5.
L1
VIN
SA
SC
SE
V12
V11
VOUT
Lr
Cr1
SB
SD
Cr2
SF
L2
Time: t5
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 18 of 29
HA16163T
Delay Setting
Inter-output delays (TD1, TD2, TD3) are set by means of a resistance connected between the DELAY-1 (-2, -3) pin and
GND. The following graph shows the relationship between the external resistance and delay. The typical value of the
delay set time is given by the following equation.
TD = 0.5 [pF] × RD [Ω] + 8 [ns]
[s]
When the RD value is small, the set time will be larger than the above calculated value due to the effect of internal
delay, etc., and therefore a constant setting should be made with reference to the following graph.
TD vs. RD
TD (ns)
1.00E+03
HA16163
1.00E+02
(2.0V)
1.00E+01
DELAY-1
(DELAY-2)
(DELAY-3)
RD
GND
1.00E+00
1
10
100
RD (kΩ)
1000
Figure 11
Place the resistor for connection to the DELAY-1,2,3 pin as close to the pin as is possible. Please design the pattern so
that the level of cross-talk from other signals is minimized.
DELAY-3 (TD3)
There is a condition that secondary-side control output OUT-E and OUT-F delay TD3 is 0 s (typical) in order to prevent
shorting of the transformer secondary side. The relationship between TD3 and the IC operating state is shown in the
following table.
Mode
Light load
Pulse by pulse OCL
One shot OCL
Definition
COMP < 1.65V
CS ≥ 0.4V
CS ≥ 0.6V
Operation of OUT-E, OUT-F
TD3 = 0
TD3 = 0
Fixed low (operation halted)
Note
1
2
Notes: 1. Light-load detection is performed by means of the error amplifier output voltage. Light-load detection
characteristics are as shown in the following diagram.
VREF
FB
Error Amp.
−
+
500μ
Light Load
Detector
−
+
TD3
TD3
set value
1.25V
20k
COMP
10k
−
+
Comparator
0.4V
0
1.46V 1.55V COMP
voltage
Light Load Detector Characteristics
RAMP
2. TD3 of the next OUT-E or OUT-F after the pulse-by-pulse current limiter (PBP OCL) operates is 0 s (typical).
When OUT-C and OUT-D are subsequently inverted by the Phase Shift Comparator, not the PBP OCL, TD3
is restored to the value set by means of the DELAY-3 pin.
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 19 of 29
HA16163T
Application
Note: All voltage, current, time shown in the diagram are typical value.
Sample application circuits are given here. Confirmatory experiments should be carried out when applying these
examples to products.
Slope Compensation
In order to improve the unstable operation characteristic of current mode, voltage slopes in a current sense signal can be
superimposed. The following is a possible slope compensation method.
5V(VREF)
HA16163
OUT-A
OUT-B
OUT-D
OUT-C
Compensated signal
Current sense signal
RAMP
Comparator
−
+
0.4V
S
Q
R
RES
Figure 12
Driving a Pulse Transformer
OUT-A through OUT-F of this IC are CMOS outputs that use Vref as their power supply. When directly driving a
pulse transformer, the Vref voltage fluctuates according to the exciting current. As Vref fluctuation may make internal
circuit operation unstable, direct drive of a pulse transformer should be avoided.
• Case 1 (NG)
The figure below shows a case where a pulse transformer is driven directly. Vref voltage fluctuation occurs due to
the exciting current.
HA16163
Vref value fluctuates due to
this exiting current
Vref
Cref
Internal
Circuitry
OUT-E
Case 1 (NG)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 20 of 29
HA16163T
• Case 2
The figure below shows an example in which a current amplifier is added by means of transistors. A reverse current
due to the exciting current is prevented by a blocking diode, and therefore capacitance CB is charged. In this way,
fluctuation of the Cref potential is suppressed and stable operation can be achieved.
As well as a buffer implemented by means of a transistor, standard logic IC or buffer IC connection is also possible.
The buffer circuit power supply method should be implemented in the same way.
Blocking diode
HA16163
CB
Vref
Cref
Internal
Circuitry
OUT-E
Case 2
• Case 3
The figure below shows an example of a drive power supply method using emitter following. For the same reason
as described above, fluctuation of the Cref potential is suppressed and stable operation can be achieved.
VCC
HA16163
CB
Vref
Cref
Internal
Circuitry
OUT-E
Case 3
Supplying Power from an External Power Supply
It is also possible to use an external source as the power supply for the HA16163T as shown in figure 13. The
VREFGOOD circuit controls whether the IC is operating or stopped. The threshold voltage of the VREFGOOD circuit
is 4.6 V (typ.) on the rising edge and 4.4 V on the falling edge. Since the IC’s characteristics vary with the value of the
external voltage, this voltage must be provided by a high-precision 5-V source.
Vcc
Vext
5V ± 2%
VREF
HA16163T
Figure 13
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 21 of 29
HA16163T
Characteristic Curves
UVL Voltage vs. Ambient Temperature Characteristics
11.0
10.5
10.0
VH
VH (V)
9.5
9.0
8.5
8.0
VL
7.5
7.0
–40
–25
0
25
50
75
100
125
Ta (°C)
Standby Current vs. Ambient Temperature Characteristics
160
Vcc = 8.5V
140
120
Is (μA)
100
80
60
40
20
0
–40
–25
0
25
50
Ta (°C)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 22 of 29
75
100
125
HA16163T
Operating Current vs. Ambient Temperature Characteristics
12
No load on VREF pin
10
Icc (mA)
8
6
4
2
0
–40
–25
0
25
50
75
100
125
Ta (°C)
VREF Output Voltage vs. Ambient Temperature Characteristics
5.20
5.15
5.10
Vref (V)
5.05
5.00
4.95
4.90
4.85
4.80
–40
–25
0
25
50
Ta (°C)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 23 of 29
75
100
125
HA16163T
Remote-on Voltage vs. Ambient Temperature Characteristics
1.48
1.46
VON (V)
1.44
1.42
1.40
1.38
1.36
1.34
–40
–25
0
25
50
75
100
125
Ta (°C)
Remote-off Voltage vs. Ambient Temperature Characteristics
1.40
1.38
VOFF (V)
1.36
1.34
1.32
1.30
1.28
1.26
–40
–25
0
25
50
Ta (°C)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 24 of 29
75
100
125
HA16163T
Error Amplifier Feedback Voltage vs. Ambient Temperature Characteristics
1.30
FB and COMP are shorted
1.28
VFB (V)
1.26
1.24
1.22
1.20
–40
–25
0
25
50
75
100
125
Ta (°C)
Error Amplifier Source Current vs. Ambient Temperature Characteristics
0
FB = 0.75V, COMP = 2V
–100
ISOURCE (mA)
–200
–300
–400
–500
–600
–40
–25
0
25
50
Ta (°C)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 25 of 29
75
100
125
HA16163T
Error Amplifier Sink Current vs. Ambient Temperature Characteristics
20
FB = 1.75V, COMP = 2V
18
16
ISINK (mA)
14
12
10
8
6
4
2
0
–40
–25
0
25
50
75
100
125
Ta (°C)
Soft-start Pin Current vs. Ambient Temperature Characteristics
–5
SS = 1V
–6
–7
–8
Iss (μA)
–9
–10
–11
–12
–13
–14
–15
–40
–25
0
25
50
Ta (°C)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 26 of 29
75
100
125
HA16163T
Switching Frequency vs. Ambient Temperature Characteristics
580
560
540
fsw (kHz)
520
500
480
460
440
420
400
380
–40
–25
0
25
50
75
100
125
Ta (°C)
TD1 Delay vs. Ambient Temperature Characteristics
50
45
TD1 (ns)
40
35
30
25
20
15
–40
–25
0
25
50
Ta (°C)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 27 of 29
75
100
125
HA16163T
Current Sense Delay Time vs. Ambient Temperature Characteristics
70
60
Tpd (ns)
50
40
30
20
10
0
–40
–25
0
25
50
75
100
125
Ta (°C)
Overcurrent Protection Delay Time vs. Ambient Temperature Characteristics
100
Tpd-cs (ns)
80
60
40
20
0
–40
–25
0
25
50
Ta (°C)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 28 of 29
75
100
125
HA16163T
Package Dimensions
JEITA Package Code
P-TSSOP20-4.4x6.5-0.65
RENESAS Code
PTSP0020JB-A
*1
Previous Code
TTP-20DAV
MASS[Typ.]
0.07g
D
F
20
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
11
c
HE
*2
E
bp
Terminal cross section
( Ni/Pd/Au plating )
Index mark
Reference Dimension in Millimeters
Symbol
10
1
e
bp
L1
x
M
A
Z
*3
A1
θ
L
y
Detail F
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 29 of 29
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Min Nom Max
6.50 6.80
4.40
0.03 0.07 0.10
1.10
0.15 0.20 0.25
0.10 0.15 0.20
0°
8°
6.20 6.40 6.60
0.65
0.13
0.10
0.65
0.4 0.5 0.6
1.0
Sales Strategic Planning Div.
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Colophon .7.2