APL5338A 2A Bus Termination Regulator Features General Description • Sourcing and Sinking Current up to 2A • VCNTL Supply Voltage Range: 3.1V to 5.5V The APL5338A linear regulator is designed to provide a regulated voltage with bi-directional output current for • VIN Supply Voltage Range: 1.2V to 3.6V • VTT and VTTREF Voltage Tracks at Half the VREF DDR-SDRAM termination. The APL5338A integrates two power transistors to source or sink current up to 2A. It also incorporates current-limit and thermal shutdown into a single chip. Voltage • VTT and VTTREF Voltage with ±10mV Accuracy • Excellent Load Transient Response • Stable with 10µF Ceramic Output Capacitor • Current-Limit Protection • Thermal Shutdown Protection • Power-On-Reset Function on VCNTL • S3, S5 Input Signals for ACPI States • Small MSOP-10P, DFN2x2-8 and TDFN3x3-10 • Lead Free and Green Devices Available The output voltage of APL5338A tracks the voltage at VREF pin. An internal resistor divider is used to provide a half voltage of VREF for VTTREF and VTT Voltage. The VTT output voltage is only requiring 10µF of ceramic output capacitance for stability and fast transient response. The S3 and S5 pins provide the sleep state for VTT (S3 state) and suspend state (S4/S5 state) for device when S5 and S3 are both pulled low the device provides the soft-off for VTT and VTTREF. The MSOP-10P, DFN2x2-8 and TDFN3x3-10 packages with a copper pad is available Packages which provides excellent thermal impedance. (RoHS Compliant) Simplified Application Circuit Applications • CIN 10µF 1 2 3 4 5 COUT 10µF DDR 2/3 Memory Termination APL5338A VREF VIN VTT PGND VCNTL S5 GND S3 VTTSNS VTTREF 10 9 8 7 6 C1 0.1µF ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 1 www.anpec.com.tw APL5338A Pin Configuration VREF 1 VIN 2 VTT 3 PGND 4 10 VCNTL VIN 2 9 S5 GND VTT 3 8 GND PGND 4 VCNTL VREF 1 8 S5 7 GND 6 S3 5 VTTREF 7 S3 VTTSEN 5 DFN-2x2-8 (Top View) 6 VTTREF = Exposed Pad (connected to VCNTL plane for better heat dissipation) MSOP-10P (Top View) VREF 1 VIN 2 VTT 3 PGND 4 VTTSEN 5 10 VCNTL 9 S5 8 GND 7 S3 6 VTTREF GND TDFN3X3-10 (Top View) = Exposed Pad (connected to ground plane for better heat dissipation) Ordering and Marking Information Package Code XA : MSOP-10P QB : TDFN3x3-10 QA : DFN2x2-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL5338A Assembly Material Handling Code Temperature Range Package Code APL5338A XA : L5338 XXX XX XXXXX - Date Code APL5338A QB : APL 5338 XXXXX XXXXX - Date Code APL5338A QA : 338A X XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 2 www.anpec.com.tw APL5338A Absolute Maximum Ratings (Note 1) Symbol VCNTL Parameter VCNTL Supply Voltage (VCNTL to GND) Rating Unit -0.3 ~ 7 V VIN VIN Supply Voltage (VIN to GND) -0.3 ~ VCNTL + 0.3 V VTT VTT Output Voltage (VTT to GND) -0.3 ~ VIN + 0.3 V VTTREF Output Voltage (VTTREF to GND) -0.3 ~ VIN + 0.3 V VREF Input Voltage (VREF to GND) -0.3 ~ 7 V VTTSNS, S3 and S5 Voltage -0.3 ~ 7 V VTTREF VREF PGND to GND Voltage TJ TSTG TSDR -0.3 ~ 0.3 Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds V 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Typical Value Unit Junction-to-Ambient Resistance in Free Air (Note 2) MSOP-10P 60 o C/W TDFN3x3-10 60 DFN2x2-8 80 Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of MSOP-10P and TDFN3x3-10 is soldered directly on the PCB. θJA Recommended Operating Conditions Symbol VCNTL VIN VREF VS3, VS5 Parameter VCNTL to GND VIN to GND (VIN<VCNTL+0.3V) VREF to GND (0.5VREF<VIN) 3.1 ~ 5.5 V 1.2 ~ 3.6 V 1.0 ~ 3.6 VCNTL=3.3V 1.0 ~ 1.6 V 0 ~ 5.5 V A 10 ~ 100 µF Capacitance of VTT Output Multi-layer Ceramic Capacitor (MLCC) 10 ~ 47 µF Ambient Temperature -40 ~ 85 o -40 ~ 125 o CIN VIN Input Capacitor TJ Unit -2 ~ +2 VTT Output Current TA Range VCNTL=5V S3, S5 to GND IVTT COUT (Note 3) (Note 4) Junction Temperature C C Note 3 : Refer to the typical application circuit. Note 4 : If the VTT output current is “+2A”, then VTT source would be 2A current, and vice versa. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 3 www.anpec.com.tw APL5338A Electrical Characteristics Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=VREF=1.8V, CIN=10µF, COUT=10µF and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL5338A Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVCNTL VIN VCNTL Supply Current TJ = 25oC, VCNTL=5V, VS3=VS5=5V, no load 0.2 0.5 1 VCNTL Standby Current TJ = 25oC, VCNTL=5V, VS3=0V, VS5=5V, no load 20 50 80 VCNTL Shutdown Current TJ = 25oC, VCNTL=5V, VS3=VS5=0V, no load, VIN=VREF=0V - 0.3 1.0 VIN Supply Current TJ = 25oC, VCNTL=5V, VS3=VS5=5V, no load 0.3 0.6 1.0 VIN Standby Current TJ = 25oC, VCNTL=5V, VS3=0V, VS5=5V, no load - 5 10 VIN Shutdown Current TJ = 25oC, VCNTL=5V, VS3=VS5=0V, no load, VIN=VREF=0V - 0.5 1.0 mA µA mA µA INPUT IMPEDANCE IVREF VREF Input Impedance VCNTL=5V, VS3=VS5=5V 1 3 5 µA IVTTSNS VTTSNS Input Current VCNTL=5V, VS3=VS5=5V - 10 - nA 2.6 2.8 3.0 - 0.2 - POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS VCNTL POR Voltage Threshold VCNTL rising VCNTL POR Hysteresis V VTT OUTPUT VTT Output Voltage VTT Output Accuracy to VTTREF ILIM VTT Current Limit VIN=VREF=1.8V - 0.9 - VIN=VREF=1.5V - 0.75 - VIN=VREF=1.35V - 0.675 - VIN=VREF=1.35V/1.5V/1.8V, over temperature and load current range -10 - 10 VCNTL=5V Sourcing Current 2.8 3.0 3.5 VCNTL=5V Sinking Current -2.8 -3.0 -3.5 VTT Leakage Current VTT=0.9V, VS3=0V, VS5=5V, TJ =25 oC - 2.5 4.0 VTTSNS Leakage Current VTT=0.9V, TJ =25 oC -1.0 - 1.0 VTT Discharge Current VTT=0.5V, VS3=VS5=0V, TJ =25 oC, VREF=0V 15 25 35 VIN=VREF=1.8V - 0.9 - VIN=VREF=1.5V - 0.75 - VIN=VREF=1.35V - 0.675 - -10 - +10 10 20 30 0.3 0.5 0.8 V mV A µA mA VTT OUTPUT VTTREF VTTREF Output Voltage IVTTREF VTTREF Output Voltage Tolerance to 0.5VREF VTTREF Source Current Limit IVTTREFDIS VTTREF Discharge Current Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 VIN=VREF, IVTTREF<10mA VTTREF=0V o VTTREF=0.5V, VS3=VS5=0V, TJ =25 C 4 V mV mA www.anpec.com.tw APL5338A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=VREF=1.8V, CIN=10µF, COUT=10µF and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL5338A Test Conditions Unit Min. Typ. Max. LOGIC THRESHOLD VIH High Threshold Voltage VS3, VS5 Rising 1.6 - - VIL Low Threshold Voltage VS3, VS5 Falling - - 0.4 - 0.2 - S3, S5, TJ =25 oC - - 4 TJ Rising - 150 - - 30 - S3, S5 Hysteresis Leakage Current V µA THERMAL SHUTDOWN TSD Thermal Shutdown Temperature Thermal Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 5 o C www.anpec.com.tw APL5338A Typical Operating Characteristics VCNTL Supply Current vs. Temperature VCNTL Shutdown Current vs. Temperature 1.0 VCNTL=5V VS3=VS5=5V VCNTL Shutdown Current (µA) VCNTL Supply Current (mA) 0.60 0.55 0.50 0.45 0.40 -40 -20 0 20 40 60 0.9 VCNTL=5V VS3=VS5=0V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -20 80 100 120 140 Junction Temperature ( oC) VIN Supply Current vs. Temperature 0.9 VIN Shutdown Current (µA) VIN Supply Current (mA) VCNTL=5V VS3=VS5=5V 1.0 0.8 0.6 0.4 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -40 -20 0 20 40 60 0.0 -40 -20 80 100 120 140 20 40 60 80 100 120 140 VTT Output Voltage vs. Temperature VTTREF Output Voltage vs. Temperature 0.910 VCNTL=5V VIN=VREF=1.8V IVTTREF=0mA 0.908 VTT Output Voltage (V) VTTREF Output Voltage (V) 0 Junction Temperature (oC) 0.910 0.906 60 80 100 120 140 VCNTL=5V VS3=VS5=0V Junction Temperature ( oC) 0.908 40 VIN Shutdown Current vs. Temperature 1.0 1.2 0.2 20 Junction Temperature (oC) 1.6 1.4 0 0.904 0.902 0.900 0.898 0.896 0.894 VCNTL=5V VIN=VREF=1.8V 0.906 0.904 0.902 0.900 0.898 0.894 0.892 0.890 -40 -20 0 20 40 60 80 100 120 140 Junction Temperature ( oC) 0.890 -40 -20 6 IVTT=10mA 0.896 0.892 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 IVTT=-10mA 0 20 40 60 80 100 120 140 Junction Temperature (oC) www.anpec.com.tw APL5338A Typical Operating Characteristics (Cont.) VTT Discharge Current vs. Temperature VTTREF Discharge Current vs. Temperature 40 VCNTL=5V VS2=VS5=0V VTTREF=0.5V 0.8 VTT Discharge Current (mA) VTTREF Discharge Current (mA) 1.0 0.6 0.4 0.2 0.0 -40 -20 0 20 40 60 25 20 15 60 80 100 120 140 VTTREF Voltage vs. VTTREF Load Current (DDR3) 0.760 0.758 VTTREF Voltage (V) 0.902 0.900 0.898 0.896 0.754 0.752 0.750 0.748 0.746 0.744 0.892 0.742 0 2 4 6 8 0.740 0 10 VCNTL=5V VIN=VREF=1.5V 0.756 0.894 0.908 40 VTTREF Voltage vs. VTTREF Load Current (DDR2) 0.904 0.910 20 Junction Temperature ( oC) 0.906 0.890 0 Junction Temperature ( oC) VCNTL=5V VIN=VREF=1.8V 0.908 2 4 6 8 10 VTTREF Load Current (mA) VTTREF Load Current (mA) VTT Voltage vs. VTT Load Current (DDR2) VTT Voltage vs. VTT Load Current (DDR3) 0.760 VCNTL=5V VIN=VREF=1.8V 0.758 0.906 0.756 0.904 0.754 VTT Voltage (V) VTTREF Voltage (V) 30 10 -40 -20 80 100 120 140 0.910 VTT Voltage (V) 35 VCNTL=5V VS2=VS5=0V VTT=0.5V 0.902 0.900 0.898 0.896 0.752 0.750 0.748 0.746 0.894 0.744 0.892 0.742 0.890 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.740 -2.0 -1.5 -1.0 -0.5 0.0 2.0 0.5 1.0 1.5 2.0 VTT Load Current (A) VTT Load Current (A) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 VCNTL=5V VIN=VREF=1.5V 7 www.anpec.com.tw APL5338A Operating Waveforms (Refer to the section “Typical Application Circuits” VCNTL=5V, VIN=VREF=1.8V, TA=25oC) Startup Waveform-S5 Low to High 1 2 Startup Waveform-S3 Low to High VS5 VS 5 1 VS3 2 VS 3 VTTRE F 3 4 V TTREF 3 VTT V TT 4 IVTT=IVTTREF=0A CH1: VS5, 5V/Div, DC IVTT=IVTTREF=0A CH1: VS5, 5V/Div, DC CH2: VS3, 5V/Div, DC CH3: VTTREF, 500mV/Div, DC CH4: VTT, 500mV/Div, DC TIME:100µs/Div CH2: VS3, 5V/Div, DC CH3: VTTREF, 500mV/Div, DC CH4: VTT, 500mV/Div, DC TIME:100µs/Div Shutdown Waveform-S3 High to Low Shutdown Waveform-S3 and S5 High to Low VS 5 VS5 1 1 VS 3 VS 3 2 2 VTTREF 3 VTTREF V TT 3 4 V TT 4 IVTT=IVTTREF=0A CH1: VS5, 5V/Div, DC IVTT=IVTTREF=0A CH1: VS5, 5V/Div, DC CH2: VS3, 5V/Div, DC CH3: VTTREF, 500mV/Div, DC CH4: VTT, 500mV/Div, DC TIME:100µs/Div CH2: VS3, 5V/Div, DC CH3: VTTREF, 500mV/Div, DC CH4: VTT, 500mV/Div, DC TIME:100µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 8 www.anpec.com.tw APL5338A Operating Waveforms (Cont.) (Refer to the section “Typical Application Circuits” VCNTL=5V, VIN=VREF=1.8V, TA=25oC) VTT Load Transient Response 1 VTTRE F 2 V TT IV TT 3 IVTT=-2A (Sink) to 2A (Source) to -2A CH1: VTTREF, 50mV/Div, DC CH2: VTT, 50mV/Div, DC CH3: I VTT, 2A/Div, DC TIME:100µs/Div Pin Description PIN I/O FUNCTION TDFN3x3-10 MSOP-10P DFN2x2-8 NAME 1 1 1 VREF I 2 2 2 VIN I 3 3 3 VTT O 4 4 4 PGND 5 5 - VTTSNS I 6 6 5 VTTREF O 7 7 6 S3 I 8 8 7 GND 9 9 8 S5 I S5 Signal Input. 10 Exposed Pad VCNTL I Power Input for Internal Control Circuitry. A bypass capacitor 0.1µF should be connected near the pin. - GND 10 Exposed Pad Exposed Pad Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 Reference Voltage Input for VTT and VTTREF Regulator. Power Input for VTT and VTTREF Pin. An input capacitor should be connected from VIN to PGND. VTT Output Voltage Pin. Source and sink current up to 2A. To insure the stability issue, the output capacitor typical 10µF should be connected from VTT to PGND. I/O Power Ground for VIN and VTT. Voltage Sense for VTT. Connect to the positive node of VTT output capacitors. VTT Reference Output Pin. A small capacitor 0.1µF should be connected from VTTREF to GND. S3 Signal Input. I/O Signal Ground. I/O Signal Ground. 9 www.anpec.com.tw APL5338A Block Diagram VIN VREF VTTREF GND VCNTL POR VTT S3 Soft-Start and Control Logic S5 VTTSEN Thermal Shutdown Current Limit PGND Typical Application Circuit VIN 1.8/1.5/1 .35V VCNTL APL5338A CIN 10µF VREF VTT 0.9/0.75/0.675V -2~+2A Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 C2 0.1µF VCNTL VIN S5 VTT GND S3 PGND C OUT 10µF 5V VTTSNS 10 VTTREF C1 0.1µF www.anpec.com.tw APL5338A Function Description VTT Source/Sink Regulator S3, S5 Control The APL5338A is a low dropout source/sink linear regulator with maximum 2A source/sink current. Two internal The S3 and S5 signals control the VTT and VTTREF states and these pins should be connected to SLP_S3 and N-channel MOSFETs controlled by separate high bandwidth error amplifiers regulate the output voltage by sourc- SLP_S5 signals respectively. The table1 shows the truth table of the S3 and S5 pins. When both S3 and S5 are ing current from VIN or sinking current to PGND. To prevent two pass elements from shoot-through, a voltage above the logic threshold voltage, the VTT and VTTREF are turned on at S0 state. When S3 is low and S5 is high, offset is created between two positive inputs of the error amplifiers. the VTT voltage is disabled and left high impedance in S3 state. When both S3 and S5 are low, the VTT and Power-On-Reset (POR) VTTREF are turned off and discharged to the ground through internal MOSFETs during S4/S5 state. (Note that The APL5338A monitors the VCNTL pin voltage for poweron-reset function to prevent erroneous operation. The if the S3 is forced high and S5 is forced low, then VTTREF is discharged and VTT is at high-Z state. Such condition built-in POR circuit keeps the outputs shutoff until internal circuit is operating properly. Typical POR threshold is is not recommended.) 2.8V with 0.2V hysteresis. Thermal Shutdown A thermal shutdown circuit limits the junction tempera- VTTREF Regulator VTTREF voltage follows 1/2VREF voltage which is the ture of the APL5338A. When the junction temperature exceeds +150oC, the device will turn off the MOSFETs, al- reference of the VTT regulator. The VTTREF block consists of a resistor divider and a low pass filter. The regu- lowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle lator can source current up to 20mA (typical). To insure after the junction temperature cools by 30oC, resulting in a pulsed output during continuous thermal overload the stability, a 0.1µF ceramic capacitor should be connected from VTTREF to GND. conditions. The thermal shutdown is designed with a 30oC hysteresis to lower the average junction tempera- Soft-Start and Current Limit ture during continuous thermal overload conditions, extending lifetime of the device. For normal operation, de- The APL5338A monitors the output current, both sourcing and sinking current, and limits the maximum output vice power dissipation should be externally limited so that junction temperatures will not exceed +125oC. current to prevent damages during current overload or short circuit (shorted from VOUT to GND or VIN) conditions. The APL5338A provides a soft-start function, using the constant current to charge the output capacitor that gives a rapid and linear output voltage rise. If the load current is above the current limit start-up, the VTT cannot start successfully. Table1. The truth table of S3 and S5 pins STATE S3 S5 VTTREF VTT S0 H H 1 1 S3 L H 1 0(high-Z) S4/5 L L 0(discharge) 0(discharge) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 11 www.anpec.com.tw APL5338A Application Information Input Capacitor Layout Consideration The APL5338A requires proper input capacitors to supply surge current during stepping load transients to prevent Figure 1 illustrates the layout. Below is a checklist for your layout: the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to 1. Please place the input capacitors close to the VIN. 2. Output capacitors for VTT must be close to the pin with the VIN limits the slew rate of the surge current, it is necessary to place the input capacitors near VIN as close as short and wide track. 3. VTTSNS should be connected to the output capacitors possible. Input capacitors should be greater than 10µF. A capacitor of 0.1µF (MLCC) or above is recommended for of VTT separated from large current path to avoid effect of ESR and ESL. The ESR and ESL of ground track VCNTL pin noise decoupling. between VTT and GND should be minimized. 4. VREF should be connected to VIN by a separate track. Output Capacitor VREF is the reference voltage of VTTREF, so avoid any noise to get into the VREF. The APL5338A needs a proper output capacitor to maintain circuit stability and improve transient response over 5. PGND is the ground of VIN and VTT. GND is the signal ground of VREF, VTTREF S3 and S5. GND and PGND temperature and current. In order to insure the circuit stability, a 10µF MLCC (minimum) as an output capacitor should be isolated with a single point connection between them. must be placed near the VTT. W ith X5R and X7R dielectrics. 6. Soldering the exposed pad to ground is good for heatsinking. Numerous vias 0.33 mm in diameter con- Thermal Consideration nected from the thermal land to the internal/solderside ground plane(s) should be used to enhance The APL5338A maximum power dissipation depends on the differences of the thermal resistance and tempera- dissipation. Large ground plane is good for heatsinking. Optimum ture between junction and ambient air. The power dissipation PD across the device is: performance can only be achieved when the device is mounted on a PC board according to the board layout PD = (TJ - TA) / θJA where (TJ-TA) is the temperature difference between the diagrams which are shown as Figure 2. junction and ambient air. θJA is the thermal resistance between junction and ambient air. Assuming the TA=25°C VIN VCNTL and maximum TJ=150°C (typical thermal limit threshold), the maximum power dissipation is calculated as: CIN APL5338A VREF PD(max) = (150-25)/60 = 2.08(W) for TDFN3x3-10/MSOP-10P packages VTT PD(max) = (150-25)/80 = 1.56(W) for DFN 2x2-8 package For normal operation, do not exceed the maximum oper- VIN S5 VTT GND PGND COUT 5V VCNTL VTTSNS C2 S3 VTTREF C1 ating junction temperature of TJ = 125oC. The calculated power dissipation should be less than: Figure 1 PD =(125-25)/60 = 1.66(W) for TDFN3x3-10/MSOP-10P packages PD = (125-25)/80 = 1.25(W) for DFN2x2-8 package The exposed pad provides an electrical connection to ground and channels heat away. Connect the exposed pad to ground by using a large ground plane. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 12 www.anpec.com.tw APL5338A Application Information (Cont.) Recommended Minimum Footprint Layout Consideration (Cont.) 0.010 PGND 8 7 6 5 10 9 8 7 6 0.061 For dissipating heat GND 0.181 VCNTL VIN C2 COUT 0.098 0.098 CIN VTT C1 PGND 1 APL5338A 2 3 5 4 GND 0.020 Figure 2. MSOP-10P package Recommended Layout Unit : Inch MSOP-8P The via diameter = 0.012 0.012 Hole size = 0.008 0.024 0.0965 0.012 0.02 0.062 Unit: Inch TDFN3x3-10 The via diameter = 0.012 Hole size = 0.008 Ground plane for Thermal PAD 0.0118 0.022 0.051 0.012 0.02 0.0315 Unit: Inch DFN2x2-8 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 13 www.anpec.com.tw APL5338A Package Information MSOP-10P D SEE VIEW A E E2 EXPOSED PAD E1 D1 c e 0.25 A GAUGE PLANE SEATING PLANE A1 L VIEW A S Y M B O L 0 A2 b MSOP-10P MILLIMETERS MIN. INCHES MAX. MIN. MAX. A 1.10 A1 0.00 0.15 0.000 0.006 A2 0.75 0.95 0.030 0.037 b 0.17 0.33 0.007 0.013 c 0.08 0.23 0.003 0.009 0.043 D 2.90 3.10 0.114 0.122 D1 1.50 2.50 0.059 0.098 E 4.70 5.10 0.185 0.201 E1 2.90 3.10 0.114 0.122 E2 1.50 2.50 0.059 0.098 e 0.50 BSC 0.020 BSC L 0.40 0.80 0.016 0.031 0 0° 8° 0° 8° Note: 1. Follow JEDEC MO-187 BA-T. 2. Dimension “D”does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not flash or protrusions. 3. Dimension “E1” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 6 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 14 www.anpec.com.tw APL5338A Package Information TDFN3x3-10 D E A b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e TDFN3x3-10 S Y M B O L A MIN. MAX. MIN. 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 INCHES MILLIMETERS A3 0.20 REF MAX. 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 2.20 2.70 0.087 0.106 E 2.90 3.10 0.114 0.122 E2 1.40 1.75 0.055 0.069 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 15 www.anpec.com.tw APL5338A Package Information DFN2x2-8 A b E D Pin 1 dot D2 A1 A3 NX aaa C E2 SEATING PLANE L K Pin 1 Corner e S Y M B O L MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 0.012 0.083 DFN2x2-8 MILLIMETERS A3 INCHES 0.20 REF 0.008 REF b 0.18 0.30 0.007 D 1.90 2.10 0.075 D2 1.00 1.60 0.039 0.063 E 1.90 2.10 0.075 0.083 E2 0.60 1.00 0.024 0.039 0.45 0.012 e 0.50 BSC L 0.30 K 0.20 aaa 0.016 BSC 0.018 0.008 0.08 0.003 Note : 1. Follow from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 16 www.anpec.com.tw APL5338A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application M S O P -1 0 P Application T D F N 3 x 3 -1 0 Application D F N 2 x 2 -8 A H 3 3 0 . 0 ±2 . 0 0 50 MIN. P0 P1 T1 12.4+2.00 -0 . 0 0 P2 4 . 0 0 ±0 . 1 0 8 . 0 0 ±0 . 1 0 2 . 0 0 ±0 . 0 5 A H 3 3 0 . 0 ±2 . 0 0 50 MIN. P0 P1 T1 12.4+2.00 -0 . 0 0 P2 4.0 ±0 . 1 0 8.0 ±0 . 1 0 2.0 ±0.0 5 A H 1 7 8 . 0 ±2 . 0 0 50 MIN. P0 P1 T1 8.4+2.00 -0 . 0 0 P2 4.0 ±0 . 1 0 4.0 ±0 . 1 0 2.0 ±0 . 0 5 C 13.0+0.50 -0 . 2 0 D0 1.5+0.10 -0 . 0 0 C 13.0+0.50 -0 . 2 0 D0 1.5+0.10 -0 . 0 0 C 13.0+0.50 -0 . 2 0 D0 1.5+0.10 -0 . 0 0 d D W E1 F 1.5 M IN. 20.2 MIN. 1 2 . 0 ±0 . 3 0 1 . 7 5 ±0 . 1 0 5.5 ±0 . 0 5 D1 A0 B0 K0 5 . 3 0 ±0 . 2 0 3 . 3 0 ±0 . 2 0 1 . 4 0 ±0 . 2 0 d T 0.6+0.00 -0 . 4 0 D W E1 F 1.5 M IN. 20.2 MIN. 1 2 . 0 ±0 . 3 0 1 . 7 5 ±0 . 1 0 5.5 ±0 . 0 5 D1 A0 B0 K0 3 . 3 0 ±0 . 2 0 3 . 3 0 ±0 . 2 0 1 . 3 0 ±0 . 2 0 d T 0.6+0.00 -0 . 4 0 D W E1 F 1.5 M IN. 20.2 MIN. 8.0 ±0 . 2 0 1 . 7 5 ±0 . 1 0 3.5 ±0 . 0 5 D1 T 0.6+0.00 -0 . 4 0 1.5 M IN. 1.5 M IN. 1.5 M IN. A0 B0 K0 2 . 3 5 ±0 . 2 0 2 . . 3 5 ±0 . 2 0 1 . 3 0 ±0 . 2 0 (mm) Devices Per Unit Package Type Unit Quantity MSOP-10P Tape & Reel 3000 TDFN3x3-10 Tape & Reel 3000 DFN2x2-8 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 17 www.anpec.com.tw APL5338A Taping Direction Information MSOP-10P USER DIRECTION OF FEED TDFN3x3-10 USER DIRECTION OF FEED DFN2x2-8 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 18 www.anpec.com.tw APL5338A Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 19 www.anpec.com.tw APL5338A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 20 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL5338A Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 21 www.anpec.com.tw