APW7276 PMIC for LCD Bias Power Features General Description • Input Voltage Range from 2.7V to 5.5V • Positive & Negative Charge Pump for VGH & VGL The APW7276 integrates with a high-performance step- • High Performance Operation Amplifier up converter, two charge pump controllers and one high current operational amplifiers for TFT-LCD applications. - +100mA Output Short Circuit Current - 13V/µs Slew Rate The main step-up regulator is a current-mode, fixed-frequency PWM switching regulator. The 1.5MHz switching - 10MHz, -3dB Bandwidth frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel • Control Output for External P-MOSFET to Support • Adjustable Power Sequence by External Capacitor • Internal Soft-start • Cycle By Cycle Current Limit plifiers are ideal for V COM applications, with 100mA output short circuit current drive, 10MHz bandwidth, and • Multiple Overload Protection 13V/µs slew rate. All inputs and outputs are rail-to-rail. • Over Temperature Protection • The APW7276 is available in a tiny 3mm x 3mm 20-pin Available in TQFN3x3-20 Package QFN package (TQFN3x3-20). • Halogen and Lead Free Available (RoHS Compliant) Completely Disconnecting the Battery designs.The charge pump controllers provide regulated the gate-driver of TFT-LCD VGH and VGL supplies.The am- Applications • Panel Pin Configuration Simplified Application Circuit FB GND 17 16 15 LX 2 14 EN FBN 3 (Exposed Pad) 13 PS GND 4 GND 12 POS DRVN 5 11 GND 8 9 10 DRVP SUP VS FBP VCOM Negative Charge Pump 1 REF 7 VGH Positive Charge Pump GND 6 VGL 18 VCOM BSW Step-up Converter 19 VSUP 20 VAVDD VIN VCOM CDLY VIN TQFN3x3-20 Top View = Thermal Pad (connected to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 1 www.anpec.com.tw APW7276 Ordering and Marking Information Package Code QB: TQFN3x3-20 Operating Ambient Temperature Range I : -40 to 85oC APW7276 Assembly Material Handling Code Handling Code TR : Tape & Reel Temperature Range Package Code APW7276 QB: APW 7276 XXXXX Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Parameter Rating Unit Input Bias Supply Voltage (VIN to GND) -0.3 ~ 6 V LX, DRP, DRN, PS, SUP, VS, POS, VCOM to GND Voltage -0.3 ~ 20 V FB, FBP, FBN, BSW, CDLY, REF, EN to GND Voltage -0.3 ~ 6 V Symbol VIN PD Power Dissipation TJ Maximum Junction Temperature TSTG TSDR Internally Limit Storage Temperature Maximum Lead Soldering Temperature (10 Seconds) W 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance in free air Typical Value Unit (Note 2) TQFN3x3-20 50 TQFN3x3-20 12 Case-to-Ambient Resistance in free air (Note 2) °C/W °C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 2 www.anpec.com.tw APW7276 Recommended Operating Conditions (Note 3) Symbol Range Unit VIN Input Bias Supply Voltage (VIN to GND) Parameter 2.7 ~ 5.5 V VSUP Main Step-up Converter Output Voltage VIN ~ 15 V VGH Positive Charge Pump Output Voltage 0 ~ 2*VSUP -2 V VGL Negative Charge Pump Output Voltage -VSUP+2 ~ VREF V CIN Input Power Capacitor 4.7 ~ µF L1 Inductor Range 1 ~ 10 µH CVGH VGH Capacitor 0.22 ~ 2.2 µF CVGL VGL Capacitor 0.22 ~ 2.2 µF CREFF VREF Capacitor 0.1 ~ 0.47 µF R1 Feedback Resistance of VSUP 0.1 ~ 1 MΩ R4 Feedback Resistance of VGH 0.1 ~ 1 MΩ R6 Feedback Resistance of VGL 0.1 ~ 0.54 MΩ TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o C C Note 3: Refer to the typical application circuit. Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=3.6V and TA= 25oC. Symbol Parameter Test Conditions APW7276 Unit Min. Typ. Max. 2.7 - 5.5 V VFB = 1V, switching - 2 5 mA VFB = 1.3V, no switching - 300 - µA EN = GND - 0.1 1 µA UVLO Threshold Voltage 2.2 2.4 2.6 V UVLO Hysteresis Voltage 50 100 150 mV 1.225 1.25 1.275 V 2 - - mA SUPPLY CURRENT VIN Input Voltage Range IVIN VIN Supply Current ISD VIN Shutdown Input Current UNDER VOLTAGE LOCKOUT (UVLO) VIN STET-UP REGULATOR VREF Reference Voltage IREF Reference Voltage Output Current VIN=2.7V~5.5V, TA = -40 ~ 85oC, IREF = 0 ~ 2mA o VFB FB Regulation Voltage VIN=2.7V~5.5V, TA = -40 ~ 85 C 1.225 1.25 1.275 V FSW Switching Frequency VFB = 1.1V 1.25 1.5 1.75 MHz RON Power Switch On Resistance VIN = 3.6V ILIM Power Switch Current Limit - 0.5 - Ω 2.0 - - A -1 - 1 µA LX Maximum Duty Cycle 92 95 98 % FB Input Current -50 - 50 nA LX Leakage Current DMAX IFB Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 VEN = GND, VLX=0V or 5V, VIN = 5V 3 www.anpec.com.tw APW7276 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VIN=3.6V and TA= 25oC. Symbol Parameter APW7276 Test Conditions Unit Min. Typ. Max. SOFT-START AND SHUTDOWN TSS VTEN Step-up Regulator Soft-start Duration (Note 4) - 2 - ms EN High Threshold VEN Rising - - 1 V V EN Low Threshold VEN Falling 0.4 - - IEN EN Leakage Current VEN = 5V, VIN = 5V -1 - 1 µA IBSW BSW Pull-down Current 3 5 10 µA BSW to VIN Ron - 200 - Ω ICDLY CDLY Charge Current - 10 - µA 1 - V CDLY High Threshold VGL Soft-start without Delay from VSUP - PS to GND Leakage Current VPS=15V - - 100 nA - 1k - Ω - 50 - Ω - - 100 nA - 2 - ms 1.225 1.25 1.275 V -50 - 50 nA 5 - - mA PS to GND On Resistance INTERNAL SWITCH RVS SUP to VS On Resistance SUP to VS Leakage Current VS Soft-start Duration (Note 4) POSITIVE REGULATED CHARGE PUMP VFBP FBP Regulation Voltage IFBP FBP Input Current IDRVP RMS DRVP Output Current VIN=2.7V~5.5V, TA = -40 ~ 85oC VSUP = 12V DRP On Resistance High - 20 - Ω DRP On Resistance Low - 3.5 - Ω 400 500 600 kHz - 2 - ms -25 0 25 mV -50 - 50 nA 5 - - mA DRN On Resistance High - 5 - Ω DRN On Resistance Low - 12 - Ω 400 500 600 kHz - 2 - ms Positive Charge Pump Frequency TSSP Positive Charge Pump Soft-start Duration (Note 4) NEGATIVE REGULATED CHARGE PUMP VFBN FBN Regulation Voltage IFBN FBN Input Current IDRVN RMS DRVN Output Current VIN=2.7V~5.5V, TA = -40 ~ 85oC VSUP = 12V Negative Charge Pump Frequency TSSN Negative Charge Pump Soft-start Duration Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 (Note 4) 4 www.anpec.com.tw APW7276 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VIN=3.6V and TA= 25oC. Symbol Parameter APW7276 Test Conditions Unit Min. Typ. Max. SEQUENCE TDEL1 PS Delay Time (Note 4) - 15 - ms TDEL2 Delay Time Between VAVDD to VGL (Note 4) 1 - 15 ms TDEL3 Delay Time Between VGL to VGH (Note 4) - 15 - ms (Note 4) - 110 - dB VCOMP BUFFER AOL Open Loop Gain VOH Output Voltage High BW SR mV IOUT=5mA VSUP-150 VSUP-80 - mV 2 15 mV IOUT=5mA - 80 150 mV Short Circuit Current 50 70 - mA Continuous Output Current ±40 - - mA VCOM discharge resistance - 2 - kΩ ISC GBWP - - Output Voltage Low PSRR VSUP-15 VSUP-3 IOUT=100µA VOL IVCOM IOUT=100µA Power Supply Rejection Ratio (Note 4) 60 - - dB -3dB Bandwidth (Note 4) - 10 - MHz Gain Bandwidth Product (Note 4) - 8 - MHz Slew Rate (Note 4) - 13 - V/µs Note 4: Guarantee by design, not production test Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 5 www.anpec.com.tw APW7276 Pin Description PIN FUNCTION TQFN3x3-20 NAME 1,4,11,16 GND Signal and Power ground. Connect these pins to exposed pad. 2 REF Internal 1.25V reference voltage output. Connect 1µF capacitor to this pin. 3 FBN Negative charge pump feedback input. 5 DRVN Regulated charge pump driver for VGL. Connect to flying capacitor. 6 DRVP Regulated charge pump driver for VGH. Connect to flying capacitor. 7 SUP 8 VS 9 FBP 10 VCOM 12 POS 13 PS This is the gate drive pin which can be used to control an external P-channel MOSFET to provide input to output isolation of VSUP or VAVDD. See the Typical Application Section. PS is an open-drain output and is pulled low as soon as the delay time of CDLY setting is expired. PS goes high impedance when the EN is low. 14 EN Enable pin. Logic high initiates power-up sequencing. Logic low disable the device. 15 LX Step-up converter inductor/diode connection. 17 FB Main step-up converter feedback input. 18 BSW 19 VIN 20 CDLY Delay Setting Capacitor Connection Pin. Connecting a capacitor from this pin to GND allows the setting of delay time between VSUP to VGL during start-up. Pull this pin exceed 1V ignore the delay time. Exposed Pad GND Signal and Power Ground. This is the supply pin of the positive and negative charge pump driver. Connected this pin to the output of the main step-up converter VSUP. The supply voltage of positive charge pump regulator. Positive charge pump feedback input. VCOM output. Non-inverting Input of VCOM. Bi-direction switch control pin. This switch disconnects VOUT from VIN during shutdown and any fault evens. IC power input. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 6 www.anpec.com.tw APW7276 Typical Operating Characteristics VAVDD vs. IAVDD IAVDD vs.Efferency 100 10.0 9.8 80 9.6 VAVDD (V) Efficiency (%) VOUT=9.5V 60 40 9.4 9.2 9.0 8.8 8.6 20 VIN=3.3V 8.4 VIN=5.0V 8.2 0 VIN=3.3V VIN=5.0V 8.0 0 100 200 300 400 500 0 100 200 Input Current (mA) VIN vs. VREF 400 500 VIN vs. Fsw 2.0 1.8 FSW (MHz) 1.225 VREF (V) 300 IAVDD (mA) 1.175 1.6 1.4 1.125 1.2 1.0 1.075 2.0 3.0 4.0 5.0 6.0 2.4 3.4 4.4 5.4 VIN (V) VIN (V) VIN vs. VAVDD Junction Temperature vs. VREF 1.252 10.0 1.25 1.248 VREF (V) VAVDD (V) 9.5 9.0 1.246 1.244 8.5 IAVDD=100mA IAVDD=200mA 1.242 8.0 1.24 2.7 3.2 3.7 4.2 4.7 -50 5.2 VIN (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 7 0 50 100 Junction Temperature (oC) 150 www.anpec.com.tw APW7276 Typical Operating Characteristics Junction Temperature vs. FSW 1.55 FSW (MHz) 1.5 1.45 1.4 1.35 1.3 -50 0 50 100 150 o Junction Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 8 www.anpec.com.tw APW7276 Operating Wavrforms The test conditions are APW7276, VIN=3.3V, VAVDD=9.5V, VGL=-8.2V, VGH=16.8V, VCOM=VAVDD/2, TA= 25oC unless otherwise specified. Boost Converter PWM continuous Mode: Heavy Load Boost Converter PWM Discontinuous Mode: Light Load VLX VLX 1 1 VAVDD-AC VAVDD-AC 2 2 IL IL 3 3 VIN=3.3V, VAVDD=9.5V/300mA, L=2.2uH VIN=3.3V, VAVDD=9.5V/50mA, L=2.2uH CH1: VLX, 5V/Div, DC CH2: VAVDD-AC, 100mV/Div, AC CH3: IL, 500mA/Div, DC TIME: 400ns/Div CH1: VLX, 5V/Div, DC CH2: VAVDD-AC, 100mV/Div, AC CH3: IL, 500mA/Div, DC TIME: 400ns/Div Power-On Sequence Power-Off Sequence VSUP 2 VSUP VGL 2 1 VGL 1 VGH VGH 3 3 VCOM VCOM 4 4 VIN=3.3V, VAVDD=9.5V/30mA, VGL=-8.2V/8.2kohm, VGH=16.8V/18kohm, EN Power On CH1: VSUP, 5V/Div, DC CH2: VGL, 5V/Div, DC CH3: VGH, 10V/Div, DC CH4: VCOM, 5V/Div, DC TIME: 20ms/Div VIN=3.3V, VAVDD=9.5V/30mA, VGL=-8.2V/8.2kohm,VGH=16.8V/18kohm, EN Power On CH1: VSUP, 5V/Div, DC CH2: VGL, 5V/Div, DC CH3: VGH, 10V/Div, DC CH4: VCOM, 5V/Div, DC TIME: 20ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 9 www.anpec.com.tw APW7276 Operating Wavrforms The test conditions are APW7276, VIN=3.3V, VAVDD=9.5V, VGL=-8.2V, VGH=16.8V, VCOM=VAVDD/2, TA= 25oC unless otherwise specified. Boost Converter Load Transient Response VAVDD-AC 1 IAVDD 2 VIN=3.3V, VAVDD=9.5V, L=2.2uH CH1: VAVDD-AC, 100mV/Div, AC CH2: IAVDD, 200mA/Div, DC TIME: 10ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 10 www.anpec.com.tw APW7276 Block Diagram VIN LX BSW FB VIN UVLO REF Q4 5µA Logic Control REF Gate Driver COMP Q1 PWM Logic Control FB EAMP Slope Compensation GND Current Sense Amplifier 1.5MHz Oscillator Current Limit Comparator REF OK Current REF OTP VS Q2 Shutdown and Soft-start Control EN SUP P1 VGH Logic Control POS SUP DRVP N1 VGL Soft-start VCOM FBP CDLY REF 1V SUP Q5 FBOK VGL Logic Control 10µA DRVN N2 Shutdown PS P2 Q3 15ms Delay FBOK FBN EN Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 11 www.anpec.com.tw APW7276 Typical Application Circuit Q1 APM2301CAC VIN C2 4.7µF 6.3V C1 4.7µF 6.3V VAVDD C5 1µF 16V VSUP C15 0.22µF R3 1M C3 (option) C4 10µF 16V R9 100k VIN BSW L1 2.2µF Q2 APM2309AC ON EN OFF C10 0.47µF D1 LX DRVN R1 680k FB FBN R2 68k R7 45k REF SUP VS VGH C7 1µF 25V C6 1µF 16V VCOM VCOM VS C13 1µF DRVP C8 0.1µF 16V R4 680k Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 R18 300k POS R8 300k FBP R5 56k C11 1µF C12 0.1µF PS C16 1µF 16V VGL R6 300k C17 22pF VSUP C14 0.1µF CDLY C9 0.22µF GND 12 www.anpec.com.tw APW7276 Power On Sequence VEN VREF VBSW VBSW < 1V VSUP 15ms 2ms VPS VGL TCDLY 2ms 15ms VGH VS 2ms VCOM Time The output voltage falling slew rate after shutdown depend on external resistance beside VCOM. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 13 www.anpec.com.tw APW7276 Function Description VIN Under-Voltage Lockout (UVLO) CDLY The Under-voltage lockout (UVLO) circuit compares the input voltage at VIN with the UVLO threshold to ensure Connecting a capacitor from this pin to GND allows the setting of delay time between VGL and VSUP. Once the VSUP the input voltage is high enough for reliable operation. The 100mV (typ) hysteresis prevents supply transients soft-start process enabled, an internal 10µA current source starts to charge CDLY, the VGL channel initiates soft- from causing a restart. Once the input voltage exceeds the UVLO rising threshold, startup begins. When the in- start process once VCDLY exceed 1V. If the VCDLY exceeds 1V before V SUP start up, the V SUP and V GL start up put voltage falls below the UVLO falling threshold, the controller turns off the converter. simultaneously. BSW Main Step-up Converter Control Loop The APW7276 is a constant frequency, synchronous rectifier and current-mode switching regulator. In normal Once VREF is within 8% of its normal regulated output voltage, an internal current source from the BSW to GND operation, the internal main switch (Q1) is turned on each cycle. The peak inductor current at which EAMP turn off to pull BSW low. Once the VBSW below 1V, the step-up converter initiates soft-start process. The VBSW pull to VIN the Q1 is controlled by the voltage on the COMP node which is the output of the error amplifier (EAMP). if main step-up current limit detected without delay, EN pull low or VIN below POR. An external resistive divider connected between VSUP and ground allows the EAMP to receive an output feedback PS This is the gate drive pin which can be used to control an voltage VFB at FB pin. When the load current increases, it causes a slightly decrease in VFB relative to the reference voltage, which in turn causes the COMP voltage to in- external MOSFET switch to provide input to output isolation of VSUP or VAVDD. See the Typical Application Section. crease until the average inductor current matches the new load current. At light load current, the COMP voltage PS is an open-drain output and is latch low as soon as the step-up converter is within 10% of its normal regu- is low. The APW7276 auto skips pulse. lated output voltage for 15ms. GD goes high impedance when the EN input voltage is cycle low. Pulse Skip Modulation APW7276 auto skip pulse at light load. An Isolation Switch from VSUP to VS (Q2) Main Step-up Converter Current Limit The VS is the voltage source of positive charge pump, VGH. As soon as the VGL start-up for 15ms, the P-FET, Q2, The APW7276 integrated a current-limit-comparator in switch soft on. The Q2 fully turns on after 2ms. The Q2 turns off at Q1 current limit detected and EN goes low. main step-up converter. It monitors the inductor current, flows through the N-channel MOSFET, and limits the current peak at current-limit level to prevent loads and the APW7276 from damaging during overload or short-cir- Operational Amplifier The operational amplifier is typically used to drive the cuit conditions. LCD backplane (VCOM) or the gamma-correction divider string. They feature +100mA output short-circuit current, VREF 13V/µs slew rate, and 8MHz bandwidth. The rail-to-rail input and output capability maximizes system flexibility. The VREF initiates soft-start process after POR and EN goes high. Shutdown if POR and EN goes low. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 14 www.anpec.com.tw APW7276 Function Description (Cont.) Positive Charge Pump Negative Charge Pump The positive charge-pump regulator is typically used to The negative charge-pump regulator is typically used to generate the positive supply rail for the TFT LCD gate driver ICs. The output voltage is set with an external Re- generate the negative supply rail for the TFT LCD gate driver ICs. The output voltage is set with an external re- sistive voltage-divider from its output to GND with the midpoint connected to FBP. The charge pump includes a sistive voltage-divider from its output to REF with the midpoint connected to FBN. The number of charge pump high-side p-channel MOSFET (P1) and a low-side n-channel MOSFET (N1) to control the power transfer as shown stages and the setting of the feedback divider determine the output of the negative charge-pump regulator. The in Figure 1. During the first half-cycle, N1 turns on and charges flying capacitors C8 (Figure 1). During the sec- charge-pump controller includes a high-side p-channel MOSFET (P2) and a low-side n-channel MOSFET (N2) to ond half cycle, N1 turns off and P1 turns on, level shifting C8 by VSUP volts. The amount of charge transferred to the control the power transfer as shown in Figure 2. During the first half cycle, P2 turns on, and flying capaci- output is determined by the error amplifier that controls P1’s on-resistance. The positive charge-pump regulator’s tor C10 charges to VSUP minus a diode drop (Figure 2). During the second half cycle, P2 turns off, and N2 turns startup can be delayed from negative charge pump after 15ms, the positive charge-pump regulator is enabled. on, level shifting C10. This connects C10 in parallel with reservoir capacitor C11. If the voltage across C11 minus Each time it is enabled, the positive charge-pump regulator goes through a soft-start routine by ramping up its a diode drop is greater than the voltage across C10, charge flows from C11 to C10 until the diode (D5) turns internal reference voltage from 0 to 1.25V. The soft-start period is 2ms (typ). The soft-start feature effectively limits off. The amount of charge transferred from the output is determined by the error amplifier, which controls N2’s the inrush current during startup. on-resistance. The negative charge-pump regulator is enabled when the step-up regulator reaches regulation and VCDLY exceed 1V. Each time it is enabled, the negative charge- 1.25V VS VS pump regulator goes through a soft-start routine by ramping down its internal reference voltage from 1.25V to 0mV. C15 P1 500kHz The soft-start period is 2ms typically. The soft-start feature effectively limits the inrush current during startup. C8 SUP DRVP N1 VGH GND SUP 500kHz C7 C15 R4 P2 FBP C10 R5 DRVN D5 N2 VGL GND Fig1. Positive Charge Pump Regulator Block Diagram C11 R6 REF FBN R7 Fig2. Negative Charge Pump Regulator Block Diagram Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 15 www.anpec.com.tw APW7276 Function Description (Cont.) Over-Temperature Protection (OTP) TQFN3x3-20 The over-temperature circuit limits the junction temperature of the APW7276. When the junction temperature exceeds 160 oC, a thermal sensor turns off the power MOSFET allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and 0.6mm * 0.25mm 1.65 mm regulates the output voltage again after the junction temperature cools by 40oC. The OTP is designed with a 40oC hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions in- 0.4mm creasing the lifetime of the device. 1.65 mm 0.275 mm Layout Consideration For all switching power supplies, the layout is an important step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully * Just Recommend done, the regulator might show noise problems and duty cycle jitter. Figure 3. Recommended Minimum Footprint 1. The input capacitor C1 and C16 should be placed close to the VIN/SUP and GND. Connecting the capacitor with VIN/SUP and GND pins by short and wide tracks for filtering and minimizing the input voltage ripple. 2. The inductor and Schottky diode should be placed as close as possible to the LX pin to minimize length of the copper tracks as well as the noise coupling into other circuits. 3. A star ground connection or ground plane minimizes ground shifts and noise is recommended. 4. Since the feedback pin (FBx) and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 16 www.anpec.com.tw APW7276 Package Information TQFN3x3-20 D E b A Pin 1 A1 A3 D2 NX aaa C L K E2 Pin 1 Corner e S Y M B O L TQFN3x3-20 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 A3 0.20 REF 0.002 0.008 REF b 0.15 0.25 0.006 0.010 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 0.122 0.071 E 2.90 3.10 0.114 E2 1.50 1.80 0.059 0.50 0.012 e 0.40 BSC L 0.30 K 0.20 0.016 BSC 0.08 aaa 0.020 0.008 0.003 Note : 1. Followed from JEDEC MO-220 WEEE Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 17 www.anpec.com.tw APW7276 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN3x3-20 A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type TQFN3x3-20 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 Quantity 3000 18 www.anpec.com.tw APW7276 Taping Direction Information TQFN3x3-20 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 19 www.anpec.com.tw APW7276 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 20 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7276 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 21 www.anpec.com.tw