APW7137 1MHz, High Efficiency, Step-Up Converter with Internal FET Switch Features General Description • Wide 2.5V to 6V Input Voltage Range • Built-in 0.6Ω N-Channel MOSFET The APW7137 is a fixed switching frequency (1MHz typical), current-mode, step-up regulator with an inte- • Built-in Soft-Start • High Efficiency up to 90% • <1µA Quiescent Current During Shutdown • Current-Mode Operation grated N-channel MOSFET. The device allows the usage of small inductors and output capacitors for portable devices. The current-mode control scheme provides fast transient response and good output voltage accuracy. The APW7137 includes under-voltage lockout, currentlimit, and over-temperature shutdown preventing dam- - Stable with Ceramic Output Capacitors - Fast Transient Response age in the event of an output overload. • Current-Limit Protection • Over-Temperature Protection with Hysteresis • Available in a Tiny 5-Pin SOT-23 and TSOT-23 90 Packages 80 Lead Free and Green Devices Available 70 Efficiency, η (%) • 100 (RoHS Compliant) Applications VIN=5V 60 VIN=3.3V 50 40 30 • Cell Phone and Smart Phone 20 • PDA, PMP, MP3 10 • Digital Camera 0 • Boost Regulators VOUT=12V 0.1 1 Pin Configuration 5 VIN 1000 10µH C1 4.7µF 4 EN 5 VIN 2 SOT-23-5 / TSOT-23-5 (Top View) ON OFF VOUT L1 5V GND 2 FB 3 100 Simplified Application Circuit VIN LX 1 10 Output Current, IOUT (mA) 4 12V LX 1 R1 1.2MΩ C2 4.7µF GND APW7137 EN FB 3 R2 137kΩ ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 1 www.anpec.com.tw APW7137 Ordering and Marking Information Package Code B : SOT-23-5 BT : TSOT-23-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7137 Assembly Material Handling Code Temperature Range Package Code APW7137 B : W37X X - Date Code APW7137 BT : 37WX X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol (Note 1) Parameter Rating Unit VIN VIN Pin to GND -0.3 to 7 V VLX LX Pin to GND -0.3 to 40 V VEN EN Pin to GND -0.3 to VIN V TJ Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds 150 °C -65 to 150 °C 260 °C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Junction to Ambient Thermal Resistance (Note 2) SOT-23-5 260 TSOT-23-5 220 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Unit °C/W Recommended Operating Conditions (Note 3) Symbol VIN Parameter VIN Input Voltage Range Unit 2.5 ~ 6 V VLX LX to GND Voltage -0.3 ~ 36 V VOUT Converter Output Voltage VIN ~ 35 V 2.2 ~ µF CIN COUT Input Capacitor 2.2 ~ µF TA Ambient Temperature Output Capacitor -40 ~ 85 °C TJ Junction Temperature -40 ~ 125 °C Note 3: Please refer to the typical application circuit. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 2 www.anpec.com.tw APW7137 Electrical Characteristics Refer to the typical application circuits. These specifications apply over. VIN=3.6V, IOUT=0mA, TA=-40°C to 85°C, unless otherwise noted. Typical values are at TA=25°C. Symbol Parameter APW7137 Test Conditions Unit Min. Typ. Max. 2.5 - 6 V VFB = 1.0V, switching - 1 2 mA EN = GND - 0.1 1 µA VIN Rising 2.0 2.2 2.4 V 50 100 150 mV TA = 25°C 1.212 1.23 1.248 TA = -40 ~ 85°C 1.205 - 1.255 -50 - 50 nA SUPPLY VOLTAGE AND CURRENT VIN IDD Input Voltage Range Input DC Bias Current ISD TA = -40 ~ 85°C, TJ = -40 ~ 125°C UNDER-VOLTAGE LOCKOUT UVLO Threshold Voltage UVLO Hysteresis Voltage REFERENCE AND OUTPUT VOLTAGES VREF IFB Regulated Feedback Voltage FB Input Current V INTERNAL POWER SWITCH FSW Switching Frequency 0.8 1.0 1.2 MHz RON Power Switch On Resistance - 0.6 - Ω ILIM Power Switch Current Limit 1 1.3 1.6 A LX Leakage Current DMAX VFB=1.1V VEN=0V, VLX=0V or 5V, VIN = 5V LX Maximum Duty Cycle -1 - 1 µA 92 95 98 % SOFT-START AND SHUTDOWN TSS Soft-Start Duration (Note 4) VTEN EN Voltage Threshold - 2 3 ms 0.4 0.7 1 V - 0.1 - V VEN=5V, VIN = 5V -1 ±0.5 1 µA TJ Rising - 150 - °C - 40 - °C VEN Rising EN Voltage Hysteresis ILEN EN Leakage Current OVER-TEMPERATURE PROTECTION TOTP Over-Temperature Protection (Note 4) Over-Temperature Protection Hysteresis (Note 4) Note 4: Guaranteed by design, not production tested. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 3 www.anpec.com.tw APW7137 Typical Operating Characteristics (Refer to the section “Typical Application Circuits”, VIN=3.6V, TA=25oC, unless otherwise specified) Reference Voltage vs. Junction Temperature Switching Current vs. Supply Voltage 1.28 1.2 Reference Voltage, VREF (%) Switching Current, IDD (mA) 1.27 1 0.8 0.6 0.4 0.2 VFB=1.0V 0 2.5 3 3.5 4 4.5 5 5.5 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.19 1.18 -50 6 -25 Supply Voltage, V IN (V) 75 100 125 Supply Voltage 100 0.8 Maximum Duty Cycle, DMAX (%) Switch ON Resistance, RON (Ω) 50 Maximum Duty Cycle vs. Junction temperature 0.7 0.6 VIN=2.7V 0.5 0.4 VIN=3.6V 0.3 VIN=5V 0.2 -50 -25 0 25 50 75 100 90 80 70 60 50 40 125 2.5 3 3.5 Junction Temperature, T J (°C) 4.5 5 5.5 6 Switching Frequency vs. Junction Temperature 1.2 Switching Frequency, FSW (MHz) 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 2.5 4 Supply Voltage, V IN (V) Switching Frequency vs. Supply Voltage Switching Frequency, FSW (MHz) 25 Junction Temperature, T J (°C) Switch ON Resistance vs. 0.9 0 3 3.5 4 4.5 5 5.5 1 0.9 0.8 0.7 0.6 0.5 0.4 -50 6 Supply Voltage, V IN (V) Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 1.1 -25 0 25 50 75 100 125 Junction Temperature, T J (°C) 4 www.anpec.com.tw APW7137 Typical Operating Characteristics (Cont.) (Refer to the section “Typical Application Circuits”, VIN=3.6V, TA=25oC, unless otherwise specified) Output Voltage vs. Output Current Efficiency vs. Output Current 100 12.20 VIN=5V 90 12.15 Output Voltage, VOUT(V) Efficiency, η (%) 80 70 60 VIN=3.3V 50 40 30 20 10 12.10 VIN=5V 12.05 12.00 11.95 VIN=3.3V 11.90 11.85 VOUT=12V 0 11.80 0.1 1 10 100 1000 0.1 Output Current, I OUT (mA) 1 10 100 1000 Output Current, IOUT (mA) Output Voltage vs. Supply Voltage 12.20 Output Voltage, VOUT(V) 12.15 12.10 12.05 12.00 11.95 11.90 11.85 11.80 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 5 www.anpec.com.tw APW7137 Operating Waveforms (Refer to the section “Typical Application Circuits”, VIN=3.6V, TA=25oC, unless otherwise specified) Start-up Start-up VEN, 1V/Div, DC 1 VEN, 1V/Div, DC 1 VOUT, 5V/Div, DC 2 VOUT, 5V/Div, DC 2 VIN=3.6V IOUT=1mA IIN, 100mA/Div IIN, 100mA/Div 3 3 Time: 0.5ms/Div Time: 0.5ms/Div CH1: VEN, 1V/Div, DC CH2: VOUT, 5V/Div, DC CH3: IIN, 100mA/Div, DC Time: 0.5ms/Div VIN=3.6V IOUT=100mA CH1: VEN, 1V/Div, DC CH2: VOUT, 5V/Div, DC CH3: IIN, 100mA/Div, DC Time: 0.5ms/Div Normal Operation Normal Operation VLX, 10V/Div VLX, 10V/Div 1 1 VOUT, 50mV/Div VOUT, 50mV/Div 2 2 IL, 100mA/Div IL, 100mA/Div Time: 1µs/Div 3 VIN=3.3V IOUT=80mA 3 CH1: V LX, 10V/Div, DC CH2: V OUT, 50mV/Div, AC CH3: I L, 100mA/Div, DC Time: 1µs/Div Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 Time: 1µs/Div VIN=5V IOUT=80mA CH1: VLX, 10V/Div, DC CH2: VOUT, 50mV/Div, AC CH3: IL, 100mA/Div, DC Time: 1µs/Div 6 www.anpec.com.tw APW7137 Operating Waveforms (Cont.) (Refer to the section “Typical Application Circuits”, VIN=3.6V, TA=25oC, unless otherwise specified) Load Transient Response Load Transient Response VOUT, 200mV/Div, AC 1 30mA VOUT, 200mV/Div, AC 1 IOUT, 50mA/Div 1mA 2 Time: 0.2ms/Div Time: 0.5ms/Div CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.5ms/Div Load Transient Response Load Transient Response VOUT, 200mV/Div, AC 30mA IOUT, 50mA/Div 1mA 2 VIN=3.3V VOUT=12V CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.2ms/Div 1 VIN=3.3V VOUT=12V 30mA IOUT, 50mA/Div Time: 0.2ms/Div 2 VIN=5V VOUT=12V 1mA IOUT, 50mA/Div Time: 0.5ms/Div CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.5ms/Div CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.2ms/Div Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 VIN=5V VOUT=12V 30mA 1mA 2 VOUT, 200mV/Div, AC 1 7 www.anpec.com.tw APW7137 Operating Waveforms (Cont.) (Refer to the section “Typical Application Circuits”, VIN=3.6V, TA=25oC, unless otherwise specified) Load Transient Response Load Transient Response VOUT, 200mV/Div, AC 1 VOUT, 200mV/Div, AC 1 IOUT, 50mA/Div 150mA 150mA 30mA IOUT, 50mA/Div 30mA 2 2 VIN=3.3V VOUT=12V Time: 0.1ms/Div Time: 0.1ms/Div CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.1ms/Div CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.1ms/Div Load Transient Response Load Transient Response VOUT, 200mV/Div, AC 1 VIN=3.3V VOUT=12V VOUT, 200mV/Div, AC 1 150mA IOUT, 50mA/Div 150mA IOUT, 50mA/Div 30mA 30mA 2 Time: 0.1ms/Div 2 VIN=5V VOUT=12V VIN=5V VOUT=12V CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.1ms/Div CH1: VOUT, 200mV/Div, AC CH2: IOUT, 50mA/Div, DC Time: 0.1ms/Div Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 Time: 0.1ms/Div 8 www.anpec.com.tw APW7137 Operating Waveforms (Cont.) (Refer to the section “Typical Application Circuits”, VIN=3.6V, TA=25oC, unless otherwise specified) Line Transient Response Line Transient Response VIN, 1V/Div, DC VIN, 1V/Div, DC 5V 4.2V 3.2V 4V VOUT, 0.2V/Div, AC VOUT, 0.2V/Div, AC 2 2 1 1 Time: 0.2ms/Div IOUT=40mA VOUT=12V Time: 0.2ms/Div CH1: VIN, 1V/Div, DC CH2: VOUT, 0.2/Div, AC Time: 0.2ms/Div Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 IOUT=40mA VOUT=5V CH1: VIN, 1V/Div, DC CH2: VOUT, 0.2/Div, AC Time: 0.2ms/Div 9 www.anpec.com.tw APW7137 Pin Description PIN. FUNCTION NO NAME 1 LX 2 GND 3 FB Feedback Input. The device senses feedback voltage via FB and regulate the voltage at 1.23V. Connecting FB with a resistor-divider from the output that sets the output voltage in the range from VIN to 30V. 4 EN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V to shut it down. In shutdown, all functions are disabled to decrease the supply current below 1µA. Do not left this pin floating. 5 VIN Main Supply Pin. Must be closely decoupled to GND with a 2.2µF or greater ceramic capacitor. Switch pin. Connect this pin to inductor/diode here. Power and signal ground pin. Block Diagram VIN UVLO EN LX Gate Driver Control Logic Over-Temperature Protection Slop Compensation Current Limit Current Sense Amplifier Σ Oscillator Error Amplifier ICMP GND FB COMP EAMP VREF 1.23V Soft-Start Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 10 www.anpec.com.tw APW7137 Typical Application Circuits VIN L1 VOUT 10µH 5V C1 4.7µF 5 2 ON OFF 4 12V LX VIN 1 R1 1.2MΩ C2 4.7µF GND APW7137 FB EN 3 R2 137kΩ Figure 1. Typical 5V to 12V Supply VIN VOUT L1 4.7µH 3.3V C1 4.7µF 5 2 ON OFF 4 5V LX VIN 1 R1 430kΩ C2 10µF GND APW7137 FB EN 3 R2 140kΩ Figure 2. Standard 3.3V to 5V Supply L1 VIN VOUT 22µH C1 4.7µF 5 2 100Hz~300Hz 4 VIN LX 1 C2 1µF Up to 8 WLEDs GND APW7137 EN FB Duty=100%, ILED=20mA 3 R1 62Ω Duty=0%, LED off Figure 3. Brightness control using a PWM signal apply to EN Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 11 www.anpec.com.tw APW7137 Typical Application Circuits (Cont.) +13V C6 0.47µF +9V C4 0.47µF C5 C9 0.1µF 0.1µF C3 C7 0.1µF 0.1µF -8V C10 0.47µF -4V C8 0.47µF VIN C1 4.7µF 5 2 ON OFF 4 L1 VOUT 4.7µH 5V VIN LX 1 R1 430kΩ C2 10µF GND APW7137 EN FB 3 R2 140kΩ Figure 4. Multiple Output for TFT-LCD Power Supply Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 12 www.anpec.com.tw APW7137 Function Description Main Control Loop Over-Temperature Protection (OTP) The APW7137 is a constant frequency and current-mode The over-temperature circuit limits the junction tempera- switching regulator. In normal operation, the internal Nchannel power MOSFET is turned on each cycle when the ture of the APW7137. When the junction temperature exceeds 150 oC, a thermal sensor turns off the power oscillator sets an internal RS latch, and then turned off when an internal comparator (ICMP) resets the latch. The MOSFET allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the COMP node which is regulates the output voltage again after the junction temperature cools by 40oC. The OTP is designed with a 40oC the output of the error amplifier (EAMP). An external resistive divider connected between VOUT and ground allows hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions in- the EAMP to receive an output feedback voltage VFB at FB pin. When the load current increases, it causes a slightly creasing the lifetime of the device. Enable/Shutdown to decrease in VFB associated with the 1.23V reference, which in turn, it causes the COMP voltage to increase Driving EN to the ground places the APW7137 in shut- until the average inductor current matches the new load current. down mode. When in shutdown, the internal power MOSFET turns off, all internal circuitry shuts down, and the quiescent supply current reduces to 1µA maximum. VIN Under-Voltage Lockout (UVLO) The Under-Voltage Lockout (UVLO) circuit compares the input voltage at VIN with the UVLO threshold to ensure the input voltage is high enough for reliable operation. The 100mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO rising threshold, startup begins. When the input voltage falls below the UVLO falling threshold, the controller turns off the converter. Soft-Start The APW7137 has a built-in soft-start to control the output voltage rise during start-up. During soft-start, an internal ramp voltage, connected to the one of the positive inputs of the error amplifier, raises up to replace the reference voltage (1.23V typical) until the ramp voltage reaches the reference voltage. Current-Limit Protection The APW7137 monitors the inductor current, flows through the N-channel MOSFET, and limits the current peak at current-limit level to prevent loads and the APW7137 from damaging during overload or short-circuit conditions. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 13 www.anpec.com.tw APW7137 Application Information Input Capacitor Selection The peak inductor current is calculated as the following equation: 1 V ⋅ (VOUT − VIN ) IPEAK = IIN(MAX ) + ⋅ IN 2 VOUT ⋅ L ⋅ FSW The input capacitor (CIN) reduces the ripple of the input current drawn from the input supply and reduces noise injection into the IC. The reflected ripple voltage will be smaller when an input capacitor with larger capacitance is used. For reliable operation, it is recommended to VIN select the capacitor with maximum voltage rating at least 1.2 times of the maximum input voltage. The capacitors IL IIN LX N-FET CIN IOUT D1 VOUT ESR ISW should be placed close to the VIN and the GND. COUT Inductor Selection IL Selecting an inductor with low dc resistance reduces conduction losses and achieves high efficiency. The efficiency ILIM is moderated whilst using small chip inductor which op- IPEAK ∆IL erates with higher inductor core losses. Therefore, it is necessary to take further consideration while choosing IIN an adequate inductor. Mainly, the inductor value determines the inductor ripple current: larger inductor value ISW results in smaller inductor ripple current and lower conduction losses of the converter. However, larger inductor value generates slower load transient response. A reasonable design rule is to set the ripple current, ∆IL, to be 30% to 50% of the maximum average inductor current, IL(AVG). The inductor value can be obtained as below, V L ≥ IN VOUT ID 2 VOUT − VIN η × × F ⋅I SW OUT (MAX ) ∆IL IL (AVG ) IOUT Output Capacitor Selection where The current-mode control scheme of the APW7137 al- VIN = input voltage lows the usage of tiny ceramic capacitors. The higher capacitor value provides good load transients response. VOUT = output voltage FSW = switching frequency in MHz Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, IOUT = maximum output current in amp. η = Efficiency tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the ideal ∆IL /IL(AVG) = inductor ripple current/average current output capacitor. (0.3 to 0.5 typical) To avoid the saturation of the inductor, the inductor should be rated at least for the maximum input current of the Δ VOUT = ΔVESR + ΔVCOUT ∆VCOUT ≈ converter plus the inductor ripple current. The maximum input current is calculated as below: IIN(MAX ) = V − VIN ⋅ OUT V ⋅ OUT FSW ∆VESR ≈ IPEAK ⋅ RESR IOUT (MAX ) ⋅ VOUT VIN ⋅ η Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 IOUT COUT where IPEAK is the peak inductor current. 14 www.anpec.com.tw APW7137 Application Information (Cont.) 4. A star ground connection or ground plane minimizes ground shifts and noise is recommended. Output Capacitor Selection (Cont.) For ceramic capacitor application, the output voltage ripple is dominated by the ∆VCOUT. When choosing the input and output ceramic capacitors, the X5R or X7R with their good VOUT t e m p e r a t u r e an d v o l t a g e c h a r ac t e r i s t i c s a r e recommended. L1 D1 LX C2 VIN R1 The output voltage is set by a resistive divider. The external resistive divider is connected to the output which allows remote voltage sensing as shown in “Typical Application Circuits”. A suggestion of the maximum value of R2 C1 Output Voltage Setting VEN Optimized APW7137 Layout R1 is 2MΩ and R2 is 200kΩ for keeping the minimum current that provides enough noise rejection ability through the resistor divider. The output voltage can be calculated as below: R1 R1 VOUT = VREF ⋅ 1 + = 1.23 1 + R2 R2 Diode Selection To achieve the high efficiency, a Schottky diode must be used. The current rating of the diode must meet the peak current rating of the converter. Layout Consideration For all switching power supplies, the layout is an important step in the design especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. The input capacitor should be placed close to the VIN and the GND without any via holes for good input voltage filtering. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. 3. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 15 www.anpec.com.tw APW7137 Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 INCHES MILLIMETERS MIN. MAX. MIN. MAX. 0.057 A 1.45 A1 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 0.020 b 0.30 0.50 0.012 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 0.118 0.071 E 2.60 3.00 0.102 E1 1.40 1.80 0.055 e 0.95 BSC e1 1.90 BSC 0.037 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 16 www.anpec.com.tw APW7137 Package Information TSOT-23-5 D e E E1 SEE VIEW A b c 0.25 A GAUGE PLANE SEATING PLANE A1 A2 e1 L VIEW A TSOT-23-5 S Y M B O L MIN. MAX. MIN. MAX. A 0.70 1.00 0.028 0.039 MILLIMETERS INCHES A1 0.01 0.10 0.000 0.004 A2 0.70 0.90 0.028 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC 0.037 BSC e1 1.90BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Followed from JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 17 www.anpec.com.tw APW7137 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOT-23-5 TSOT-23-5 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.20±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity SOT-23-5 Tape & Reel 3000 TSOT-23-5 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 18 www.anpec.com.tw APW7137 Taping Direction Information SOT-23-5 USER DIRECTION OF FEED TSOT-23-5 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 19 www.anpec.com.tw APW7137 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 20 www.anpec.com.tw APW7137 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Volume mm Thickness <350 <2.5 mm 235 °C ≥2.5 mm 220 °C Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 3 Volume mm ≥350 220 °C 220 °C Volume mm 350-2000 260 °C 250 °C 245 °C 3 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 21 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7137 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2013 22 www.anpec.com.tw