AOC2802 Common-Drain Dual N-Channel Enhancement Mode Field Effect Transistor General Description Product Summary The AOC2802 uses advanced trench technology to provide excellent RSS(ON), low gate charge and operation with gate voltages as low as 2.5V while retaining a 12V VGS(MAX) rating. It is ESD protected. This device is suitable for use as a unidirectional or bi-directional load switch, facilitated by its common-drain configuration. Vss ID (at VGS=4.5V) 20V 6A RSS(ON) (at VGS=4.5V) < 34mΩ RSS(ON) (at VGS=4.0V) < 35mΩ RSS(ON) (at VGS=3.1V) < 43mΩ RSS(ON) (at VGS=2.5V) < 54mΩ WLCSP 1.57x1.57_4 Bottom View Equivalent Circuit Top View D2 D1 G2 S2 G1 Pin1(S1) S1 G1 G2 S2 S1 Absolute Maximum Ratings TA=25°C unless otherwise noted Parameter Symbol Source-Source Voltage VSS Gate-Source Voltage VGS Source Current (DC) Note1 Source Current (Pulse) Power Dissipation TA=25°C Note2 Note1 Junction and Storage Temperature Range Note 1. Mounted on minimum pad PCB Note 2. PW <300 µs pulses, duty cycle 0.5% max Rev 4: Nov 2012 Units V ±12 V IS 6 ISM 60 PD TA=25°C Maximum 20 TJ, TSTG www.aosmd.com 1.3 -55 to 150 A W °C Page 1 of 5 Electrical Characteristics (TJ=25°C unless otherwise noted) Symbol Parameter STATIC PARAMETERS Source-Source Breakdown Voltage BVSSS Conditions Min IS=250µA, VGS=0V, Test Circuit 6 Typ 20 1 Zero Gate Voltage Source Current IGSS Gate leakage current VSS=0V, VGS= ±10V, Test Circuit 2 BVGSO Gate-Source Breakdown Voltage VSS=0V, IG=±250µA, Test Circuit 7 ±12 VGS(th) Gate Threshold Voltage VSS=VGS IS=250µA, Test Circuit 3 0.5 TJ=55°C 5 Note TJ=125°C 1 10 1 1.5 28 34 µA V VGS=4.5V, IS=3A, Test Circuit 4 Static Source to Source On-Resistance Units V VSS=20V, VGS=0V, Test Circuit 1 ISSS RSS(ON) Max 41 48 VGS=4.0V, IS=3A, Test Circuit 4 30 35 VGS=3.1V, IS=3A, Test Circuit 4 36 43 VGS=2.5V, IS=3A, Test Circuit 4 45 54 V mΩ gFS Forward Transconductance Note VSS=5V, IS=3A, Test Circuit 3 19 VFSS Diode Forward Voltage Note IS=1A,VGS=0V, Test Circuit 5 0.6 1 V 1000 1200 pF DYNAMIC PARAMETERS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate resistance VGS=0V, VSS=10V, f=1MHz, 152 S pF 114 pF 1.5 kΩ SWITCHING PARAMETERS Turn-On DelayTime tD(on) 284 ns tr Turn-On Rise Time ns tD(off) Turn-Off DelayTime VGS=10V, VSS=10V, RL=1.5Ω, RGEN=6Ω , 900 5 µs tf Turn-Off Fall Time 4.8 µs VG1S1=4.5V, VSS=10V, IS=6A 10.4 nC Total Gate Charge Qg Note: Pulsed VGS=0V, VSS=0V, f=1MHz THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE Rev 4: Nov 2012 www.aosmd.com Page 2 of 5 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 60 20 4.5V 4V 3.5V 50 VSS=5V 16 3V 40 IS(A) IS (A) 12 30 2.5V 8 20 125°C VGS=2V 10 - 4 75°C 25° 0 0 0 1 2 3 4 5 0.5 VSS (Volts) Fig 1: On-Region Characteristics 1 1.25 1.5 1.75 2 2.25 VGS(Volts) Figure 2: Transfer Characteristics 65 55 VGS=2.5V 50 45 VGS=3.1V 40 VGS=4V 35 30 Normalized On-Resistance 1.6 60 RSS(ON) (mΩ Ω) 0.75 VGS=4.5V VGS=4V VGS=3.1V 1.4 VGS=2.5V 1.2 1 VGS=4.5V 25 0.8 0 5 10 15 20 0 IS (A) Figure 3: On-Resistance vs. Drain Current and Gate Voltage 25 50 75 100 125 150 175 Temperature (°C) Figure 4: On-Resistance vs. Junction Temperature 100 1.0E+01 IS=3A 90 1.0E+00 RSS(ON) (mΩ Ω) 80 1.0E-01 70 125°C 50 IS (A) Note 2. 60 PW <300 µs pulses, duty cycle 0.5% max 125°C 1.0E-02 1.0E-03 40 75°C 25°C 1.0E-04 30 25°C 20 1.0E-05 -25°C 10 0 2 4 6 8 10 12 1.0E-06 VGS (Volts) Figure 5: On-Resistance vs. Gate-Source Voltage Rev 4: Nov 2012 www.aosmd.com 0.0 0.5 1.0 1.5 2.0 VSS (Volts) Figure 6: Body-Diode Characteristics Page 3 of 5 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 1400 6 VSS=10V IS=6A 1200 Capacitance (pF) VGS (Volts) 5 4 3 2 1 Ciss 1000 800 Crss 600 Coss 400 Crss Coss 200 0 0 0 2 4 6 8 10 12 14 0 Qg (nC) Figure 7: Gate-Charge Characteristics 100.0 5 10 15 VSS (Volts) Figure 8: Capacitance Characteristics 50 TJ(Max)=150°C TA=25°C 10µs 40 RSS(ON) limited 100µs 1.0 1ms DC 0.1 10ms 100ms TJ(Max)=150°C TA=25°C Power (W) 10.0 IS (Amps) 20 30 20 10 1s 0 0.0 0.01 0.1 1 VSS (Volts) 10 100 0.001 Figure 9: Maximum Forward Biased Safe Operating Area (Note E) 0.01 0.1 1 10 100 1000 Pulse Width (s) Figure 10: Single Pulse Power Rating Junction-toAmbient (Note E) Zθ JA Normalized Transient Thermal Resistance 10 D=Ton/(Ton+T) TJ,PK=TA+PD.ZθJA.RθJA RθJA=100°C/W In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse 1 Note 2. PW <300 µs pulses, duty cycle 0.5% max PD 0.1 Single Pulse Ton T 0.01 0.00001 Rev 4: Nov 2012 0.0001 0.001 0.01 0.1 1 10 Pulse Width (s) Figure 11: Normalized Maximum Transient Thermal Impedance www.aosmd.com 100 1000 Page 4 of 5 TEST CIRCUIT 1 Isss TEST CIRCUIT 2 Igss1,2 POSITIVE VSS FOR ISSS+ POSITIVE VGS FOR IGSS1+ S2 NEGATIVE VSS FOR ISSS- S2 NEGATIVE VGS FOR IGSS1When FET1 is measured between GATE and SOURCE A G2 G2 of FET2 are shorted D2 D2 D1 D1 VSS G1 G1 A VG S1 TEST CIRCUIT 3 Vgs(off) S1 TEST CIRCUIT 4 Rss(on) S2 S2 When FET1 is measured Vss/Is between GATE and SOURCE of FET2 are shorted G2 A G2 Is D2 D2 D1 D1 VSS G1 V G1 VSS VGS VGS S1 TEST CIRCUIT 5 VF(SS)1,2 S1 TEST CIRCUIT 6 BVDSS POSITIVE VSS FOR ISSS+ NEGATIVE VSS FOR ISSS- S2 S2 4.5V When FET1 measured G2 G2 IF FET2 VGS=4.5V Is D2 D2 D1 D1 V G1 V G1 VSS VGS=0 S1 S1 TEST CIRCUIT 7 BVGSO1,2 POSITIVE VSS FOR ISSS+ NEGATIVE VSS FOR ISSS- S2 When FET1 is measured between GATE and SOURCE G2 of FET2 are shorted D2 D1 G1 V IG Rev 4: Nov 2012 S1 www.aosmd.com Page 5 of 5