Technology Licensed from International Rectifier Advanced Power Electronics Corp. APU3039 SYNCHRONOUS PWM CONTROLLER WITH OVER CURRENT PROTECTION DESCRIPTION FEATURES Current Limit using Lower MOSFET Sensing Using the 6V internal regulator for charge pump circuit allows single supply operation up to 18V Programmable Switching Frequency up to 400KHz Soft-Start Function 0.8V Precision Reference Voltage Available Uncommitted Error Amplifier Available for DDR Voltage Tracking Applications Stable with Ceramic Capacitor RoHS Compliant APPLICATIONS DDR Memory VDDQ/VTT Applications Graphic Card Hard Disk Drive Netcom on-board DC to DC regulator application Output voltage as low as 0.8V Low Cost On-Board DC to DC The APU3039 controller IC is designed to provide a synchronous Buck regulator and is targeted for applications where the cost and size is critical. The APU3039 operates with a single input supply up to 18V. The output voltage can be programmed as low as 0.8V for low voltage applications. Selectable current limit is provided to tailor to external MOSFET’s on-resistance for optimum cost and performance. The APU3039 features an uncommitted error amplifier for tracking output voltage and is capable of sourcing or sinking current for applications such as DDR bus termination. This device features a programmable switching frequency set from 200KHz to 400KHz, under-voltage lockout for both Vcc and Vc supplies, an external programmable soft-start function as well as output under-voltage detection that latches off the device when an output short is detected. TYPICAL APPLICATION 18V L1 D1 C3 1uF C9 1uF Vcc C11 Optional Vc U1 HDrv APU3039 OCSet VP VREF Rt Comp C8 5600pF R1 14K Gnd C4 1uF VOUT2 SS / SD C7 0.1uF C2 3x 15uF 25V R2 C1 15uF C5 0.1uF Q1 AP9408AGH D2 L2 4.7uH 5.76K Q2 AP9412AGH LDrv PGnd 1uH 3.3V @ 8A C6 2x 330uF 40mΩ R3 Fb R4 1K 3.16K Figure 1 - Typical application of APU3039. PACKAGE ORDER INFORMATION TA (°C) 0 To 70 DEVICE APU3039VN 0 To 70 APU3039M Data and specifications subject to change without notice. PACKAGE 20-Pin VQFN 5x5 14-Pin Plastic SOIC NB 1 200806024 Advanced Power Electronics Corp. APU3039 ABSOLUTE MAXIMUM RATINGS Vcc Supply Voltage .................................................. -0.5V To 25V Vc Supply Voltage .................................................... -0.5V To 25V Storage Temperature Range ...................................... -65oC To 150oC Operating Junction Temperature Range ..................... 0oC To 125oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. PACKAGE INFORMATION 14-PIN PLASTIC SOIC (M) VP Fb Co mp SS /SD OC Se t 20-Pin VQFN 5x5 20 19 18 17 16 15 VOUT2 VREF 1 NC 2 NC 3 14 NC Pad 13 NC 12 Rt Vcc 4 11 NC 5 7 8 9 LD rv PG nd Gn d HD rv 6 10 *Exposed pad on underside is connected to a typical 1" square copper pad through vias for 4layer PCB board design. Vc NC Rtthja=37 ℃/W Rthjc=2.3℃ /W Vcc 1 14 VREF LDrv 2 13 VP PGnd 3 12 Fb Gnd 4 11 Comp HDrv 5 Vc 10 SS 6 9 DCset Rt 7 8 Vout2 Rtthja=88℃/W Rthjc=45℃ /W ELECTRICAL SPECIFICATIONS Unless otherwise specified, specifications apply over Vcc=5V, Vc=12V and TA=0-70oC. Typical values refer to 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temp. PARAMETER Feedback Voltage Fb Voltage Initial Accuracy Fb Voltage Line Regulation Reference Voltage Ref Voltage Initial Accuracy Drive Current UVLO UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - Vc UVLO Hysteresis - Vc UVLO Threshold - Fb Supply Current Vcc Dynamic Supply Current Vc Dynamic Supply Current Vcc Static Supply Current Vc Static Supply Current SYM VFB LREG VREF IREF TEST CONDITION MIN TYP MAX UNITS 0.784 0.800 0.3 0.816 V % 0.784 0.8 2 0.816 V µA 4.75V<Vcc<20V Note 1 UVLO VCC Supply Ramping Up UVLO VC Supply Ramping Up UVLO Fb Fb Ramping Down Dyn ICC Dyn IC ICCQ ICQ Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF SS=0V SS=0V 0.3 4.4 0.26 3.47 0.20 0.4 0.5 V V V V V 7 7 5 3 15 9 9 4 mA mA mA mA 2 Advanced Power Electronics Corp. PARAMETER Error Amp Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance VP Voltage Range Soft-Start Section Charge Current Oscillator Section Frequency Ramp Amplitude Output Drivers Lo Drive Rise Time Hi Drive Rise Time Lo Drive Fall Time Hi Drive Fall Time Dead Band Time Max Duty Cycle Min Duty Cycle Internal Regulator Output Voltage Drive Current Current Limit OC Threshold Set Current OC Comp Off-Set Voltage SYM APU3039 TEST CONDITION MIN TYP +0.08 55 700 IFB1 IFB2 SS=3V SS=0V -1 30 VP Note 1 0.8 14 VRAMP SS=0V Rt=Open Rt=Gnd Note 1 Tr(LO) Tr(HI) Tf(LO) Tf(HI) TDB DMAX DMIN CLOAD=1500pF, VCC=12V CLOAD=1500pF, VCC=12V CLOAD=1500pF CLOAD=1500pF HDrv going Hi or Low Fb=0.6V, Freq=200KHz Fb=1.0V VOUT2 IOUT2 Vcc=12V SS IB Freq IOCSET VOC(OFFSET) MAX UNITS +1 70 1.5 22 200 400 1.25 35 40 40 40 40 100 88 100 100 100 100 µA µA µmho V µA KHz VPP 0 ns ns ns ns ns % % 5.7 40 6 65 6.3 V mA 21 -2 28 1.5 35 5 µA mV Note 1: Guaranteed by design but not tested for production. PIN DESCRIPTIONS(APU3039VN) PIN# 1 4 6 7 8 9 10 12 PIN SYMBOL PIN DESCRIPTION VREF Reference Voltage. This pin can source current about 2µA. Vcc This pin provides biasing for the internal blocks of the IC as well as power for the low side FET driver. A minimum of 1µF, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. LDrv Output driver for the synchronous power MOSFET. PGnd This pin serves as the separate ground for MOSFET's driver and should be connected to system's ground plane. Gnd This pin serves as analog ground for internal reference and control circuitry. A high frequency capacitor must be connected from Vcc pin to this pin for noise free operation. HDrv Output driver for the high side power MOSFET. This pin should not go negative (below ground), this may cause problem for the gate drive circuit. It can happen when the inductor current goes negative (Source/Sink), soft-start at no load and for the fast load transient from full load to no load. To prevent negative voltage at gate drive, a low forward voltage drop diode might be connected between this pin and ground. Vc This pin is connected to a voltage that must be at least 4V higher than the bus voltage of the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A minimum of 1µF, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. Rt The switching frequency can be Programmed between 200KHz and 400KHz by connecting a resistor between Rt and Gnd. By floating the pin, the switching frequency will be 200KHz and by grounding the pin, the switching frequency will be 400KHz. 3 Advanced Power Electronics Corp. APU3039 PIN DESCRIPTIONS PIN# 15 PIN SYMBOL PIN DESCRIPTION VOUT2 Output of internal regulator. The output is protected for short circuit. A high frequency capacitor is recommended to be connected from this pin to ground. 16 OCSet This pin is connected to the Drain of the lower MOSFET via an external resister and it provides the positive sensing for the internal current sensing circuitry. The external resistor programs the current limit threshold depending on the RDS(ON) of the power MOSFET. An external capacitor can be placed in parallel with the programming resistor to provide high frequency noise filtering. This pin provides soft-start for the switching regulator. An internal current source charges 17 SS / SD an external capacitor that is connected from this pin to ground which ramps up the output of the switching regulator, preventing it from overshooting as well as limiting the input current. The converter can be shutdown by pulling this pin down below 0.4V. 18 Comp Compensation pin of the error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. 19 Fb This pin is connected directly to the output of the switching regulator via resistor divider to provide feedback to the Error amplifier. 20 VP Non-inverting input of error amplifier. 2,3,5, NC No connection. 11,13,14 BLOCK DIAGRAM Regulator 6V Vcc 4 VREF 1 0.8V 1.25V Bias Generator 0.2V Vc 3V 1.25V POR 4V 3V 15 VOUT2 0.2V 12 Rt 22uA 3.5V 64uA Max SS / SD 17 10 Vc Rt Ct POR VP 20 Fb 19 Comp 18 Q Vcc R Reset Dom 25K 6 LDrv 0.4V 3V 28uA OCSet 16 9 HDrv S Error Comp Error Amp 25K Oscillator Enbl FbLo Comp 7 PGnd POR OC Comp Figure 2 - Simplified block diagram of the APU3039. 8 Gnd Advanced Power Electronics Corp. APU3039 THEORY OF OPERATION Introduction The APU3039 is a fixed frequency, voltage mode synchronous controller and consists of a precision reference voltage, an uncommitted error amplifier, an internal oscillator, a PWM comparator, an internal regulator, a comparator for current limit, gate drivers, soft-start and shutdown circuits (see Block Diagram). The output voltage of the synchronous converter is set and controlled by the output of the error amplifier; this is the amplified error signal from the sensed output voltage and the voltage on non-inverting input of error amplifier(VP). This voltage is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulses of variable duty-cycle, which drives the two N-channel external MOSFETs. The timing of the IC is provided through an internal oscillator circuit which uses on-chip capacitor. The oscillation frequency is programmable between 200KHz to 400KHz by using an external resistor. Figure 14 shows switching frequency vs. external resistor (Rt). Soft-Start The APU3039 has a programmable soft-start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Vc and Vcc rise above their threshold (3.4V and 4.4V respectively) and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/A’s output of the PWM converter and disables the short circuit protection. During the power up, the output starts at zero and voltage at Fb is below 0.4V. The feedback UVLO is disabled during this time by injecting a current (64µA) into the Fb. This generates a voltage about 1.6V (64µAX25K) across the negative input of E/A and positive input of the feedback UVLO comparator (see Figure 3). 3V 20uA HDrv 64uA Max SS/SD POR Comp 0.8V Fb 25K Error Amp LDrv 25K 0.4V 64uA3 25K=1.6V When SS=0 Feeback UVLO Comp POR Figure 3 - Soft-start circuit for APU3039. The magnitude of this current is inversely proportional to the voltage at soft-start pin. The 20µA current source starts to charge up the external capacitor. In the mean time, the soft-start voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at the positive pin of feedback UVLO comparator and the voltage negative input of E/A. When the soft-start capacitor is around 1V, the current flowing into the Fb pin is approximately 32µA. The voltage at the positive input of the E/A is approximately: 32µA x 25K = 0.8V The E/A will start to operate and the output voltage starts to increase. As the soft-start capacitor voltage continues to go up, the current flowing into the Fb pin will keep decreasing. Because the voltage at pin of E/A is regulated to reference voltage 0.8V, the voltage at the Fb is: VFB = 0.8-25K x (Injected Current) 5 Advanced Power Electronics Corp. APU3039 The feedback voltage increases linearly as the injecting current goes down. The injecting current drops to zero when soft-start voltage is around 2V and the output voltage goes into steady state. Shutdown The converter can be shutdown by pulling the soft-start pin below 0.4V. The control MOSFET turns off and the synchronous MOSFET turns on during shutdown. As shown in Figure 4, the positive pin of feedback UVLO comparator is always higher than 0.4V, therefore, feedback UVLO is not functional during soft-start. Over-Current Protection Over-current protection is achieved with a cycle by cycle scheme and it is performed by sensing current through the RDS(ON) of low side MOSFET. As shown in Figure 5, an external resistor (RSET) is connected between OCSet pin and the drain of low side MOSFET (Q2) and sets the current limit set point. The internal current source develops a voltage across RSET. When the low side switch is turned on, the inductor current flows through the Q2 and results a voltage which is given by: Output of UVLO POR 3V ≅2V Soft-Start Voltage Current flowing into Fb pin ≅1V 0V 64uA VOCSET = IOCSET x RSET-RDS(ON) x iL Voltage at negative input ≅1.6V of Error Amp and Feedback UVLO comparator IOCSET 0.8V APU3039 Q1 L1 OCSet RSET 0.8V VOUT Q2 Osc Voltage at Fb pin ---(1) 0uA 0V Figure 4 - Theoretical operational waveforms during soft-start. Figure 5 - Diagram of the over current sensing. the output start-up time is the time period when softstart capacitor voltage increases from 1V to 2V. The startup time will be dependent on the size of the external soft-start capacitor. The start-up time can be estimated by: 20µA x TSTART/CSS = 2V-1V When voltage VOCSET is below zero, the current sensing comparator flips and disables the oscillator. The high side MOSFET is turned off and the low side MOSFET is turned on until the inductor current reduces to below current set value. The critical inductor current can be calculated by setting: For a given start up time, the soft-start capacitor can be estimated as: CSS ≅ 20µA x TSTART/1V Internal Regulator The regulator powers directly from Vcc and generates a regulated voltage (6V @ 40mA). The output is protected for short circuit. This voltage can be used for charge pump circuitry as shown in Figure 1. Supply Voltage Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if Vc or Vcc fall below 3.4V and 4.4V respectively. Normal operation resumes once Vc and Vcc rise above the set values. VOCSET = IOCSET x RSET - RDS(ON) x IL = 0 ISET = IL(CRITICAL) = R SET x I OCSET RDS(ON) ---(2) If the over-current condition is temporary and goes away quickly, the APU3039 will resume its normal operation. If output is shorted or over-current condition persists, the output voltage will keep going down until it is below 0.4V. Then the output under-voltage lock out comparator goes high and turns off both MOSFETs. The operation waveforms are shown in Figure 6. 6 Advanced Power Electronics Corp. APU3039 From Figure 7, the average inductor current during the current limit mode is: Feedback VREF voltage 0.4V IO(LIM) = ISET + FS(NOM) Switching frequency IOUT ---(4) The inductor's ripple current can be expressed as: IOUT <IL>=IOUT IO(LIM) Normal operation (VIN - VOUT) x VOUT V IN x L x f S Combination of above equation and (4) results in: IOUT Average Inductor Current ∆IPK-PK(LIM) = DMAX/FS(NOM) VOUT High Side MOSFET turn on time (tON) FS(NOM)3 VIN ISET = IO(LIM) - ((V2 x-Vf x L)xVx V ) IN OUT S OUT IN ---(5) Combination of equations (5) and (2) results in the relationship between RSET and output current limit. IO(MAX) IOUT Over Current Shutdown Limit Mode by UVLO Figure 6 - Diagram of over-current operation. Operation in current limit is shown in Figure 7, the high side MOSFET is turned off and inductor current starts to decrease. Because the output inductor current is higher than the current limit setpoint (ISET), the over-current comparator keeps high until the inductor current decreases to be below ISET. Then another cycle starts. During over-current mode, the valley inductor current is: iL(VALLEY) = ISET The peak inductor current is given as: IL(PEAK) = ISET+(VIN-VOUT) x tON/L ---(3) To avoid undesirable trigger of over-current protection, this relationship must be satisfied: ISET / IO(NOM) - ∆IPK-PK(LIM) 2 ∆IPK-PK(NOM) 2 Inductor iL(PEAK) iL(AVG) Current RSET = [ ( RDS(ON) (V IN-V OUT)xV OUT x IO(LIM) IOCSET 2 x f S x L x V IN )] ---(6) Where: IO(LIM) = The Output Current Limit. Typical is 50% higher than nominal output current VIN = Maximum Input Voltage VOUT = Output Voltage fS = Switching Frequency L = Output Inductor RDS(ON) = RDS(ON) of Low Side MOSFET IOCSET = OC Threshold Set Current From the above analysis, the current limit is not only dependent on the current setting resistor RSET and RDS(ON) of low side MOSFET but it is also dependent on the input voltage, output voltage, inductance and switching frequency as well. The cycle-by-cycle over-current limit will hold for a certain amount of time, until the output voltage drops below 0.4V, the under-voltage lock out activates and latches off the output driver. The operation waveform is shown in Figure 7. Normal operation will resume after APU3039 is powered up again. ISET=iL(VALLEY) Current Limit Comparator Output HDrv tON tOFF Figure 7 - Operation waveforms during current limit. 7 Advanced Power Electronics Corp. APU3039 APPLICATION INFORMATION Design Example: The following example is a typical application for APU3039, the schematic is Figure 17 on page 16. VIN = 18V VOUT = 3.3V IOUT = 8A ∆VOUT = 100mV (output voltage ripple ≅ 3% of VOUT) fS = 200KHz Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is referenced to the voltage on non-inverting pin of error amplifier. For this application, this pin (VP) is connected to reference voltage (VREF). The output voltage is defined by using the following equation: R6 VOUT = VP x 1 + ---(7) R5 ( ) VP = VREF = 0.8V tSTART (µF) ---(8) Where tSTART is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.1µF. Choose a ceramic capacitor at 0.1µF. Boost Supply Vc To drive the high side switch, it is necessary to supply a gate voltage at least 4V grater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 9. This method is simple and inexpensive. The operation of the circuit is as follows: when the lower MOSFET is turned on, the capacitor (C1) is pulled down to ground and charges, up to VOUT2 value, through the diode (D1). The bus voltage will be added to this voltage when upper MOSFET turns on in next cycle, and providing supply voltage (Vc) through diode (D2). Vc is approximately: Vc ≅ VOUT2 + VBUS - (VD1 + VD2) When an external resistor divider is connected to the output as shown in Figure 8. VOUT APU3039 VREF Css ≅ 20 x R6 Fb R5 VP Capacitors in the range of 0.1µF and 1µF are generally adequate for most applications. The diode must be a fast recovery device to minimize the amount of charge fed back from the charge pump capacitor into VOUT2. The diodes need to be able to block the full power rail voltage, which is seen when the high side MOSFET is switched on. For low voltage application, schottky diodes can be used to minimize forward drop across the diodes at start up. D1 Figure 8 - Typical application of the APU3039 for programming the output voltage. Equation (7) can be rewritten as: R6 = R5 x ( ) VOUT2 Regulator VOUT - 1 VP Choose R5 = 1K This will result to R6 = 3.16K If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: C3 D2 VBUS Vc C2 C1 Q1 L2 APU3039 HDrv Q2 Figure 9 - Charge pump circuit. Input Capacitor Selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of upper MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: 8 Advanced Power Electronics Corp. IRMS = IOUT D(1-D) ---(9) Where: D is the Duty Cycle, D=VOUT/VIN. IRMS is the RMS value of the input capacitor current. IOUT is the output current for each channel. For VIN=20V, IOUT=8A and D=0.165, the IRMS=3A For higher efficiency, a low ESR capacitor is recommended. Choose three Poscap from Sanyo 25TQC15M (25V, 15µF, 90mΩ) with a maximum allowable ripple current of 3A. Inductor Selection The inductor is selected based on operating frequency, transient performance and allowable output voltage ripple. Low inductor value results to faster response to step load (high ∆i/∆t) and smaller size but will cause larger output ripple due to increase of inductor ripple current. As a rule of thumb, select an inductor that produces a ripple current of 10-40% of full load DC. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: ∆i VOUT 1 VIN - VOUT = Lx ; ∆t = D x ;D= ∆t VIN fS VOUT L = (VIN - VOUT) x ---(11) V INx∆ i x f S Where: VIN = Maximum Input Voltage VOUT = Output Voltage ∆i = Inductor Ripple Current fS = Switching Frequency ∆t = Turn On Time D = Duty Cycle If ∆i = 37%(IO), then the output inductor will be: L = 4.65µH The Coilcraft DO5022HC series provides a range of inductors in different values, low profile suitable for large currents, 4.7µH, 13A is a good choice for this application. This will result to a ripple approximately 37% of output current. Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient APU3039 requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is calculated by the following relationship: ESR [ ∆V O ∆IO ---(10) Where: ∆VO = Output Voltage Ripple ∆i = Inductor Ripple Current ∆VO = 100mV and ∆I ≅ 40% of 8A = 3.2A This results to: ESR=31mΩ The Sanyo TPC series, Poscap capacitor is a good choice. The 6TPC330M, 330µF, 6.3V has an ESR 40mΩ. Selecting two of these capacitors in parallel, results to an ESR of ≅ 20mohm which achieves our low ESR goal. The capacitor value must be high enough to absorb the inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage. Power MOSFET Selection The APU3039 uses two N-Channel MOSFETs. The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gatesource drive voltage (VGS), maximum output current, Onresistance RDS(ON) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter, the average inductor current is equal to the DC load current. The conduction loss is defined as: 2 PCOND(Upper Switch) = ILOADxRDS(ON)xDxθ 2 PCOND(Lower Switch) = ILOADxRDS(ON)x(1 - D)xθ θ = RDS(ON) Temperature Dependency The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. 9 Advanced Power Electronics Corp. APU3039 Choose AP9408AGH for control MOSFET and AP9412AGH for synchronous MOSFET. These devices provide low on-resistance in a compact TO-252 package. These values are taken under a certain condition test. For more details please refer to the AP9408AGH and AP9412AGH data sheets. The MOSFETs have the following data: By using equation (12), we can calculate the total switching losses. AP9408AGH VDSS = 30V ID = 53A RDS(ON) = 10mΩ AP9412AGH VDSS = 30V ID = 68A RDS(ON) = 6mΩ The total conduction losses will be: PCON(TOTAL) = PCON(UPPER) + PCON(LOWER) PCON(TOTAL) = 0.64W The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: VDS(OFF) tr + tf x ILOAD ---(12) x T 2 Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current PSW = The switching time waveform is shown in Figure 10. VDS 90% PSW(TOTAL) = 150mW Programming the Over-Current Limit The over-current threshold can be set by connecting a resistor (RSET) from drain of low side MOSFET to the OCSet pin. The resistor can be calculated by using equation (2). The RDS(ON) has a positive temperature coefficient and it should be considered for the worse case operation. RDS(ON) = 8mΩ x 1.5 = 12mΩ ISET ≅ IO(LIM) = 8A x 1.5 = 12A (50% over nominal output current) This results to: RSET = 5.76KΩ Feedback Compensation The APU3039 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45。). The output LC filter introduces a double pole, –40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 180。 (see Figure 11). The Resonant frequency of the LC filter is expressed as follows: FLC = 1 2π x ---(13) LO x CO Figure 11 shows gain and phase of the LC filter. Since we already have 180。 phase shift just from the output filter, the system risks being unstable. 10% VGS Gain td(ON) tr td(OFF) tf Phase 0。 0dB -40dB/decade Figure 10 - Switching time waveforms. From AP9408AGH data sheet we obtain: AP9408AGH tr = 5ns tf = 6ns FLC Frequency -180。 FLC Frequency Figure 11 - Gain and phase of LC filter. 10 Advanced Power Electronics Corp. APU3039 The APU3039’s error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. First select the desired zero-crossover frequency (Fo): Fo > FESR and FO [ (1/5 ~ 1/10) x fS Use the following equation to calculate R4: The E/A can be compensated with or without the use of local feedback. When operated without local feedback, the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in Figure 12. Note that this method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general, the output capacitor’s ESR generates a zero typically at 5KHz to 50KHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows: 1 FESR = ---(14) 2π x ESR x Co VOUT R6 E/A Comp C9 ) x 1 +sCsR C 4 9 9 ---(15) The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: |H(s=jx2πxFO)| = gm x 1 2 π x R 4xC 9 FLC = 2.8KHz R5 = 1K R6 = 3.16K gm = 700µmho 1 LO x CO 2π For: Lo = 4.7µH Co = 660µF The transfer function (Ve / VOUT) is given by: FZ = For: VIN = 18V VOSC = 1.25V Fo = 20KHz FESR = 12KHz FZ ≅ 0.75X FZ Frequency Figure 12 - Compensation network without local feedback and its asymptotic gain plot. R5 R6 + R5 Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R5 and R6 = Resistor Dividers for Output Voltage Programming gm = Error Amplifier Transconductance FZ ≅ 75%FLC R4 H(s) dB ( ---(18) To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Ve Gain(dB) H(s) = gm x 1 VOSC FoxF ESR R5 + R6 x x x gm 2 VIN FLC R5 This results to R4=12.08K Choose R4=14K Fb R5 Vp=VREF R4 = R5 x R4 R 6xR 5 ---(17) |H(s)| is the gain at zero cross frequency. ---(16) ---(19) FZ = 2.1KHz R4 = 14K Using equations (17) and (19) to calculate C9, we get: C9 ≅ 5300pF; Choose C9 =5600pF One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: FP = 1 2πxR4x C 9xC POLE C9 + CPOLE The pole sets to one half of switching frequency which results in the capacitor CPOLE: CPOLE = 1 π x R4 x fS - 1 C9 fS for FP << 2 ≅ 1 π x R4xfS 11 Advanced Power Electronics Corp. APU3039 For a general solution for unconditionally stability for ceramic capacitor with very low ESR and any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 13. VOUT ZIN C12 C10 R7 R8 FP1 = 0 FP2 = 1 FP3 = 2π xR 7 x FZ1 = (CC 12 12 ) x C11 + C11 ≅ 1 2π x R7 x C12 1 2π x R7 x C11 1 1 FZ2 = 2π x C10 x (R6 + R8)≅ 2π x C10 x R6 C11 R6 1 2π x R8 x C10 Zf Cross Over Frequency: Fb E/A R5 Comp Ve FO = R7 x C10 x Gain(dB) H(s) dB FZ2 FP2 FP3 The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (20) regarding transconductance error amplifier. Frequency Figure 13 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: Ve 1 - gmZf = VOUT 1 + gmZIN The error amplifier gain is independent of the transconductance under the following condition: gmZf >> 1 and gmZIN >>1 ---(20) By replacing ZIN and Zf according to Figure 9, the transformer function can be expressed as: H(s) = 1 x sR6(C12+C11) (1+sR7C11)x [1+sC10(R6+R8)] [1+sR (CC +CC )] x (1+sR C 12 7 ---(21) Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors Vp=VREF FZ1 VIN 1 x VOSC 2π x Lo x Co 12 11 11 8 10 ) As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for overall stability. Based on the frequency of the zero generated by ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation type and location of crossover frequency. Compensator Location of Zero Typical Type Crossover Frequency Output (FO) Capacitor Type II (PI) FPO < FZO < FO < fS/2 Electrolytic, Tantalum Type III (PID) FPO < FO < FZO < fS/2 Tantalum, Method A Ceramic Type III (PID) FPO < FO < fS/2 < FZO Ceramic Method B Table - The compensation type and location of zero crossover frequency. Detail information is dicussed in application Note AN1043 which can be downloaded from the IR Web-Site. 12 Advanced Power Electronics Corp. APU3039 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components. Make all the connections in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET. To reduce the ESR, replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources and be placed close to the IC. In multilayer PCB, use one layer as power ground plane and have a separate control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. 450 Frequency (KHz) 400 350 300 250 200 0 50 100 150 200 250 300 350 400 450 Rt (Kς ) Figure 14 - Switching Frequency versus Resistor. 13 Advanced Power Electronics Corp. APU3039 TYPICAL APPLICATION 5V +12V Vcc C8 2200pF R1 28K 1uH C2 2x 150uF C4 1uF C3 1uF C7 0.1uF L1 SS / SD Vc HDrv VP VREF Rt Comp Gnd Q1 AP9408AGH D1 U1 APU3039 OCSet R2 L2 7.12K 3.3uH Q2 LDrv AP9412AGH VOUT2 PGnd C1 47uF VOUT 2.5V @ 10A C6 2x 330uF, 40mΩ R3 Fb R4 1K 2.15K Figure 15 - Typical application of the APU3039 with two input supplies. 14 Advanced Power Electronics Corp. APU3039 TYPICAL APPLICATION 5V 12V C1 1uF VP Vcc Vc VOUT2 U1 HDrv APU3039 SS / SD OCSet LDrv D1 8K Q1 AP9412AGH C12 0.15uF C14 5.6nF R6 13K C7 2x 330uF, 40mΩ 6TPC330M 1.25K R3 1K Gnd 12V C9 1uF R5 1K VDDQ 1.8V @ 5A 4.7uH R1 R2 27K R4 1K C4 47uF L2 R7 Fb 5V 5V Q1 AP9408AGH PGnd Rt Comp C8 4.7nF 1uH C3 2x 100uF, 55mΩ 10TPB100M C2 1uF VREF C6 0.1uF L1 C10 1uF C11 100uF, 55mΩ 10TPB100M VREF Vcc Vc VP U2 HDrv APU3038 Q2 AP9408AGH D2 L3 SS / SD Rt Comp LDrv PGnd Q2 AP9412AGH VTT (0.9V @ 3A) 4.7uH C13 2x 330uF, 40mΩ 6TPC330M Fb Gnd Figure 16 - Typical application of APU3039 for DDR memory when APU3039 generates VCORE and APU3038 generates the termination voltage. 15 Advanced Power Electronics Corp. APU3039 DEMO-BOARD APPLICATION 18V to 3.3V @ 8A 18V L1 D1 C11 1uF C3 C13 1uF 1uF VOUT2 Vcc C6 0.1uF C10 0.1uF C7 5600pF R7 14K Vc SS / SD U1 HDrv APU3039 OCSet VP VREF Rt Comp Gnd LDrv 1uH C2A,B,C 3x 15uF 25V C5 0.1uF Q1 R4 D2 5.76K Q2 AP9412AGH PGnd C1 15uF AP9408AGH L2 4.7uH C8 470pF C12 R8 1uF 4.7Ω 3.3V @ 8A C9A,B 2x 330uF 40mΩ R9 Fb R10 1K 3.16K Figure 17 - Demo-board application of the APU3039. PARTS LIST Ref Desig Description MOSFET Q1 MOSFET Q2 Controller U1 Schottky Diode D1 Schottky Diode D2 L1 Inductor L2 Inductor C1,C2A,B,C Cap, Poscap C5,6,10 Capacitor Capacitor C7 C8 Capacitor C9A,B Capacitor Capacitor C3,11,12 C13 Capacitor Resistor R4 Resistor R7 R8 Resistor Resistor R9 Resistor R10 Value Qty Part# 30V, 10mΩ, 53A 1 AP9408AGH 30V, 6mΩ, 68A 1 AP9412AGH Synchronous PWM 1 APU3039 Fast Switching 1 BAT54S Fast Switching 1 BAT54 1 DS1608C-102 1µH, 3A 1 DO5022P-472HC 4.7µH, 13A 15µF, 25V 4 25TQC15M 0.1µF, Y5V, 25V 3 ECJ-2VF1E104Z 1 ECU-V1H562KBG 5600pF, X7R, 50V 470pF, X7R, 50V 1 ECJ-2VC1H471J 330uF, 40mΩ 2 6TPB-330M 3 ECJ-2VF1C105Z 1µF, Y5V, 16V 1µF, X7R, 25V 1 ECJ-3YB1E105K 5.76K 1 1 14K 4.7Ω 1 1 3.16K 1K 1 Manuf APEC APEC APEC IR IR Coilcraft Coilcraft Sanyo Panasonic Panasonic Panasonic Sanyo Panasonic Panasonic Web site (www.) a-power.com.tw coilcraft.com sanyo.com maco.panasonic.co.jp sanyo.com maco.panasonic.co.jp 16 Advanced Power Electronics Corp. APU3039 TYPICAL OPERATING CHARACTERISTICS Test Conditions: VIN=20V, VOUT=3.3V, IOUT=0-8A, Fs=200KHz Figure 18 - Normal condition at No Load. Ch1: HDrv, Ch2: LDrv, Ch4: Inductor Current Figure 20 - Soft-Start. Ch1: VIN, Ch2: VOUT, Ch3: VOUT2, Ch4: Vss Figure 19 - Soft-Start pin grounded. Ch1: HDrv, Ch2: LDrv Figure 21 - Output Ripple. Ch1: Output Ripple, Ch2: HDrv, Ch3: LDrv, Ch4: Inductor Current 17 Advanced Power Electronics Corp. APU3039 TYPICAL OPERATING CHARACTERISTICS Test Conditions: VIN=20V, VOUT=3.3V, IOUT=0-8A, Fs=200KHz 8A 0A Figure 22 - Output shorted at start up. Ch1: VOUT, Ch3: Vss, Ch4: Inductor Current Figure 23 - Load Transient Response Ch1: VOUT, Ch3: Output Current 90 88 Efficiency (%) 86 84 82 80 78 76 74 72 70 0 1 2 3 4 5 6 7 Output Current (A) 8 9 10 11 Figure 24 - Efficiency Measurement. VIN=20V, VOUT=3.3V 18 Advanced Power Electronics Corp. APU3039 TYPICAL PERFORMANCE CHARACTERISTICS For all charts: VC=VCC=12V, 20V, 24V Note: Data are taken with few samples to indicate the variation of these parameters over the wide temperature range. 0.802 6.2 0.801 6.15 0.8 6.1 0.799 Vout2 (V) Vref (V) 6.05 0.798 12 Volt 20 Volt 24 Volt 0.797 6 12 Volt 5.95 0.796 20 Volt 5.9 0.795 24 Volt 5.85 0.794 5.8 0.793 -45 -10 25 60 95 -45 130 -10 25 60 95 130 Temperature (C) Temperature (C) Figure 28 - VOUT2 vs.Temperature Figure 25 - VREF vs.Temperature 410 215 214 213 405 12 Volt 20 Volt 211 24 Volt 210 209 208 Frequency (KHz) Frequency (KHz) 212 12 Volt 400 20 Volt 24 Volt 395 207 390 206 205 204 385 -45 -10 25 60 95 130 -45 -10 Figure 26 - Frequency vs.Temperature FS=200KHz 60 95 130 Figure 29 - Frequency vs.Temperature FS=400KHz 200 150 100 12 Volts 20 Volts 24 Volts 50 0 Deadtime, Sync FET Drive Rising Time (ns) 200 Deadtime, Switch FET Drive Rising Time (ns) 25 Temperature (C) Temperature (C) 150 100 12 Volts 20 Volts 24 Volts 50 0 -45 -10 25 60 95 130 Temperature (C) -45 -10 25 60 Temperature (C) 95 130 Figure 27 - Deadtime, Control FET Drive Rising Time vs.Temperature FS=400KHz, CLOAD=3300pF Figure 30 - Deadtime, Sync FET Drive Rising Time vs.Temperature FS=400KHz, CLOAD=3300pF 19 Advanced Power Electronics Corp. APU3039 TYPICAL PERFORMANCE CHARACTERISTICS For all charts: VC=VCC=12V, 20V, 24V 200 200 180 180 160 12 Volts 140 20 Volts 24 Volts 120 100 80 60 40 Control FET Drive Fall Time (ns) Control FET Drive Rise Time (ns) Note: Data are taken with few samples to indicate the variation of these parameters over the wide temperature range. 160 140 12 Volts 120 20 Volts 100 24 Volts 80 60 40 20 20 0 0 -45 -10 25 60 95 130 -45 5 55 Temperature (C) Figure 31 - Control FET Drive Rise Time vs.Temp. FS=400KHz, CLOAD=3300pF 155 Figure 33 - Control FET Drive Fall Time vs.Temp. FS=400KHz, CLOAD=3300pF 200 20 180 18 160 16 140 120 12 Volts 100 20 Volts 24 Volts 80 60 Sync FET Drive Time (ns) Sync FET Drive Rise Time (ns) 105 Temperature (C) 14 12 12 Volts 20 Volts 10 24 Volts 8 6 40 4 20 2 0 0 -45 -10 25 60 95 130 Temperature (C) Figure 32 - Sync FET Drive Rise Time vs.Temp. FS=400KHz, CLOAD=3300pF -45 -10 25 60 95 130 Temperature (C) Figure 34 - Sync FET Drive Fall Time vs.Temp. FS=400KHz, CLOAD=3300pF 20 ADVANCED POWER ELECTRONICS CORP. Package Outline : SOP-14 Millimeters SYMBOLS MIN NOM MAX 1.47 1.60 1.73 A2 0.10 __ __ 0.25 __ b 0.33 1.45 0.41 C 0.19 0.20 0.25 D 8.53 5.79 8.64 8.74 6.20 3.81 __ 3.91 1.27 3.99 __ y 0.40 __ 0.71 __ 1.27 0.076 θ 0° __ 8° A A1 E E1 e L 5.99 0.51 1.All Dimensions Are in Millimeters. 2.Dimension Does Not Include Mold Protrusions. Part Marking Information & Packing : SOP-14 Part Number Package Code U3039M YWWSSS Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence 21 ADVANCED POWER ELECTRONICS CORP. Package Outline : VQFN Millimeters SYMBOLS MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 C 0.19 0.20 0.25 D 4.90 5.00 5.10 D2 3.70 3.80 3.90 E 4.90 5.00 5.10 E2 3.70 3.80 3.90 e __ 0.65 __ L 0.35 0.40 0.45 y 0.00 __ 0.076 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. Part Marking Information & Packing : VQFN Part Number Package Code U3039VN YWWSSS Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence 22