AVAGO 5962

HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572
Dual Channel Line Receiver Hermetically
Sealed Optocoupler
Data Sheet
Description
Features
The HCPL-193X devices are dual channel, hermetically sealed, high CMR, line receiver opto­coup­lers. The
products are capable of operation and storage over the
full military tempera­ture range and can be pur­chased as
either a standard product or with full MIL-PRF-38534 Class
Level H or K testing, or from the DLA Standard Microcircuit
Drawing (SMD) 5962-89572. This sixteen pin DIP may be
purchased with a variety of lead bend and plating options.
See selection guide table for details. Standard Microcircuit
Drawing (SMD) parts are available for each lead style.
•Dual marked with device part number and DLA
standard microcircuit drawing
• Manufactured and tested on a MIL-PRF-38534 certified
line
• QML-38534, Class H and Class K
• Hermetically sealed 16-pin dual in-line package
• Performance guaranteed over full military temperature
range: -55° C to +125° C
• High speed – 10 Mb/s
• Accepts a broad range of drive conditions
• Adaptive line termination included
•Internal shield provides excellent common mode
rejection
• External base lead allows “LED Peaking” and LED
current adjustment
• 1500 Vdc withstand test voltage
• High radiation immunity
• HCPL-2602 function compatibility
• Reliability data available
Functional Diagram
Applications
Truth Table (Positive Logic)
INPUT
ENABLE
OUTPUT
ON
H
L
OFF
H
H
ON
L
H
OFF
L
H
•
•
•
•
•
•
•
•
•
•
•
•
Military and space
High reliability systems
Isolated line receiver
Simplex/multiplex data transmission
Computer-peripheral interface
Microprocessor system interface
Harsh environmental environments
Digital isolation for A/D, D/A conversion
Current sensing
Instrument input/output isolation
Ground loop elimination
Pulse transformer replacement
Note: The connection of a 0.1 µF bypass capacitor between pins 15 and 10 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
All devices are manufactured and tested on a MILPRF-38534 certified line and are included in the DLA
Qualified Manufac­
turers List QML-38534 for Hybrid
Microcircuits.
Each unit contains two indepen­dent channels, consisting
of a GaAsP light emitting diode, an input current regulator,
and an integrated high gain photon detector. The input
regulator serves as a line termination for line receiver
applications. It clamps the line voltage and regulates the
LED current so line reflections do not interfere with circuit
performance. The regulator allows a typical LED current of
12.5 mA before it starts to shunt excess current. The output
of the detector IC is an open collector Schottky clamped
transistor. An enable input gates the detector. The internal
detector shield provides a guaranteed common mode
transient immunity specifi­ca­tion of +1000 V/µsec.
DC specifications are compat­ible with TTL logic and are
guaranteed from -55° C to +125° C allowing trouble-free
interfacing with digital logic circuits. An input current of
10 mA will sink a six gate fan-out (TTL) at the output with
a typical propagation delay from input to output of only
45 nsec.
Selection Guide–Lead Configuration Options
Avago Part # and Options
Commercial
HCPL-1930
MIL-PRF-38534 Class H
HCPL-1931
MIL-PRF-38534 Class K
HCPL-193K
Standard Lead Finish
Gold
Solder Dipped*
Option #200
Butt Joint/Gold Plate
Option #100
Gull Wing/Soldered*
Option #300
Crew Cut/Gold Plate
Option #600
Class H SMD Part #
Prescript for all below
5962-
Gold Plate
8957201EC
Solder Dipped*
8957201EA
Butt Joint/Gold Plate
8957201YC
Butt Joint/Soldered*
8957201YA
Gull Wing/Soldered*
8957201XA
Crew Cut/Gold Plate
Available
Crew Cut/Soldered*
Available
Class K SMD Part #
Prescript for all below
5962-
Gold Plate
8957202KEC
Solder Dipped*
8957202KEA
Butt Joint/Gold Plate
8957202KYC
Butt Joint/Soldered*
8957202KYA
Gull Wing/Soldered*
8957202KXA
*Solder contains lead.
2
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
0.89 (0.035)
1.65 (0.065)
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
Note: Dimensions in millimeters (inches).
Device Marking
Avago DESIGNATOR
Avago P/N
DLA SMD*
DLA SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
* QUALIFIED PARTS ONLY
3
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Avago CAGE CODE*
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on
commercial and hi-rel product.
4.32 (0.170)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product.
DLA Drawing part numbers contain provisions for lead finish.
300
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on
commercial and hi-rel product. This option has solder dipped leads.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
600
1.40 (0.055)
1.65 (0.065)
0.51 (0.020)
MAX.
5° MAX.
9.65 (0.380)
9.91 (0.390)
1.07 (0.042)
1.32 (0.052)
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on
commercial and hi-rel product. Contact factory for the availability of this option on DLA part types.
3.81 (0.150)
MIN.
0.51 (0.020)
MIN.
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
Notes: Dimensions in millimeters (inches).
Solder contains lead.
4
4.57 (0.180)
MAX.
1.14 (0.045)
1.25 (0.049)
7.36 (0.290)
7.87 (0.310)
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-65
+150
°C
Operating Temperature
TA
-55
+125
°C
260 for 10 sec
°C
Lead Solder Temperature
Forward Input Current (each channel)
II
60
mA
Reverse Input Current
IR
60
mA
Supply Voltage (1 minute max)
VCC
7.0
V
Enable Input Voltage (each channel)
VE
5.5*
V
Output Collector Current (each channel)
IO
25
mA
Output Collector Power Dissipation (each channel)
PO
40
mW
Output Collector Voltage (each channel)
VO
7
V
Total Package Power Dissipation
564
mW
Input Power Dissipation (each channel)
168
mW
* not to exceed VCC by more than 500 mV
Schematic
A 0.1 µF bypass capacitor must be
connected between pins 10 and 15
(see note 1).
ESD Classification
(MIL-STD-883, Method 3015)
( ), Class 1
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level
IIL
0
250
μA
Input Current, High Level*
IIH
12.5
60
mA
Supply Voltage, Output
VCC
4.5
5.5
V
High Level Enable Voltage
VEH
2.0
VCC
V
Low Level Enable Voltage
VEL
0
0.8
V
Fan Out (@ RL = 4 kΩ)
N
5
TTL Loads
Operating Temperature
TA
125
°C
-55
*12.5 mA condition permits at least 20% guardband for optical coupling variation. Initial switching threshold is 10 mA or less.
5
Note
2
Electrical Specifications
TA = -55° C to 125° C unless otherwise stated. See note 15.
Group A
Sub-groups
Limits
Parameter
Symbol
Test Conditions
Typ.*
Max.
Units
Fig.
Note
High Level
Output Current
IOH
VCC = 5.5 V, VO = 5.5 V
II = 250 μA, VE = 2.0 V
1, 2, 3
Min.
20
250
μA
3
3
Low Level
Output Voltage
VOL
VCC = 5.5 V; II = 10 mA
VE = 2.0 V,
IOL (Sinking) = 10 mA
1, 2, 3
0.3
0.6
V
1
3
Input Voltage
VI
II = 10 mA
1, 2, 3
V
2
3
II = 60 mA
2.2
2.6
2.35
2.75
Input Reverse
Voltage
VR
IR = 10 mA
1, 2, 3
0.8
1.10
V
3
Low Level
Enable Current
IEL
VCC = 5.5 V, VE = 0.5 V
1, 2, 3
-1.45
-2.0
mA
3
High Level
Enable Current
IEH
VCC = 5.5 V, VE = 1.7 V
1, 2, 3
-1.5
mA
3
High Level
Enable Voltage
VEH
1, 2, 3
V
3, 12
Low Level
Enable Voltage
VEL
1, 2, 3
0.8
V
3
High Level
Supply Current
ICCH
VCC = 5.5 V; II = 0,
VE = 0.5 V both
channels
1, 2, 3
21
28
mA
Low Level
Supply Current
ICCL
VCC = 5.5 V; II = 60 mA,
VE = 0.5 V both channels
1, 2, 3
27
36
mA
Input-Output
Insulation Leakage
Current
II-O
Relative Humidity
≤ 65% t = 5 s,
VI-O = 1500 Vdc
1
1
μA
Propagation
Delay Time to
High Output Level
tPLH
RL = 510 Ω; CL = 50 pF,
II = 13 mA,VCC = 5.0 V
9
100
ns
4, 5
3, 5
Propagation
Delay Time to
Low Output Level
tPHL
ns
4, 5
3, 6
Common Mode
Transient Immunity
at High Output Level
|CMH|
VCM = 50 V (peak),
VO (min.) = 2 V,
RL = 510 Ω; II = 0 mA,
VCC = 5.0 V
9, 10, 11
1000
10,000
V/μs
8, 9
3, 9,
14
Common Mode
Transient Immunity
at Low Output Level
|CML|
VCM = 50 V (peak),
VO (max.) = 0.8 V,
RL = 510 Ω; II = 10 mA,
VCC = 5.0 V
9, 10, 11
1000
10,000
V/μs
8, 9
3, 10, 14
RL = 510 Ω; CL = 50 pF,
II = 13 mA,VCC = 5.0 V
*All typical values are at VCC = 5 V, TA = 25° C.
6
2.0
55
10, 11
4
140
9
60
10, 11
100
120
Typical Specifications
TA = 25° C, VCC = 5 V
Parameter
Symbol
Typ.
Units
Test Conditions
Resistance (Input-Output)
RI-O
1012
Ω
VI-O = 500 V dc
Fig.
Note
3, 13
Capacitance (Input-Output)
CI-O
1.7
pF
f = 1 MHz
3, 13
Input-Input Insulation
Leakage Current
II-I
0.5
nA
≤ 65% Relative Humidity,
VI-I = 500 Vdc, t = 5 s
11
Resistance (Input-Input)
RI-I
1012
Ω
VI-I = 500 Vdc
11
Capacitance (Input-Input)
CI-I
0.55
pF
f = 1 MHz
11
Propagation Delay Time of
Enable from VEH to VEL
tELH
35
ns
RL = 510 Ω, CL = 15 pF,
II = 13 mA, VEH = 3 V, VEL = 0 V
Propagation Delay Time of
Enable from VEL to VEH
tEHL
35
ns
Output Rise Time (10-90%)
tr
30
ns
Output Fall Time (90-10%)
tf
24
ns
Input Capacitance
CI
60
pF
6, 7
3, 7
6, 7
3, 8
RL = 510 Ω, CL = 15 pF,
II = 13 mA
3
f = 1 MHz, VI = 0,
PINS 1 to 2 or 5 to 6
3
3
Notes:
1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each isolator. The power supply bus for the isolators
should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to suppress regenerative feedback
via the power supply.
2. Derate linearly at 1.2 mA/°C above TA = 100° C.
3. Each channel.
4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.
5. The tPLH propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the
output pulse.
6. The tPHL propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the
output pulse.
7. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on the trailing
edge of the output pulse.
8. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on the leading
edge of the output pulse.
9. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.
VOUT > 2.0 V.
10.CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.
VOUT < 0.8 V.
11.Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted together.
12.No external pull up is required for a high logic state on the enable input.
13.Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.
14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the limits specified
for all lots not specifically tested.
15.Standard parts receive 100% testing at 25° C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55° C (Subgroups 1
and 9, 2 and 10, 3 and 11, respectively).
7
Figure 1. Input-Output Characteristics.
Figure 2. Input Characteristics.
Figure 3. High Level Output Current vs. Temperature.
Figure 4. Propagation Delay vs. Temperature.
Figure 5. Enable Propagation Delay vs. Temperature.
8
Figure 6. Test Circuit for tPHL and tPLH.
Figure 7. Test Circuit for tEHL and tELH.
9
Figure 8. Typical Common Mode Transient Immunity.
IIN
VIN
1
16
A
2
15
B
3
VCC
14
4
13
5
12
6
11
7
GND 10
8
5V
510 Ω
OUTPUT VO
MONITORING
0.01 µF NODE
BYPASS
9
VCM
+
–
PULSE GEN.
Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
VOUT
+2.6 V
VCC
+5.5 V
100 Ω
100 Ω
VIN –
+5.0 V
+
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CONDITIONS: II = 30 mA
IO = 10 mA
VCC = 5.5 V
Figure 10. Burn In Circuit.
10
200 Ω
200 Ω
0.01 µF
TA = +125 °C
Application Circuits*
Figure A1. Polarity Non-Reversing.
Figure A2. Polarity Reversing, Split Phase.
11
Figure A3. Flop-Flop Configurations.
MIL-PRF-38534 Class H, Class K, and DLA SMD Test Program
Avago Technologies’ Hi-Rel Optocouplers are in compliance with MIL-PRF-38534 Class H and K. Class H and Class K
devices are also in compliance with DLA drawing 5962-89572.
Testing consists of 100% screen­ing and quality con­formance inspection to MIL-PRF-38534.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5968-9401E
AV02-3843EN - October 17, 2012