ACPL-331J 1.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (VCE) Desaturation Detection, UVLO, Fault Status Feedback and Active Miller Clamping Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-331J is an advanced 1.5 A output current, easyto-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-to implement. Features such as integrated VCE detection, under voltage lockout (UVLO), “soft” IGBT turn-off, isolated open collector fault feedback and active Miller clamping provide maximum design flexibility and circuit protection. • Under Voltage Lock-Out Protection (UVLO) with Hysteresis The ACPL-331J contains a AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. ACPL-331J is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V and 100 A. For IGBTs with higher ratings, the ACPL-331J can be used to drive a discrete power stage which drives the IGBT gate. The ACPL-331J has an insulation voltage of VIORM = 1230 VPEAK. Block Diagram 13 VCC2 UVLO ANODE CATHODE 6, 7 D R I V E R 5, 8 LED1 11 14 VOUT DESAT DESAT 9, 12 SHIELD VEE 2 3 10 LED2 FAULT VS • Miller Clamping • Open Collector Isolated fault feedback • “Soft” IGBT Turn-off • Fault Reset by next LED turn-on (low to high) after fault mute period • Available in SO-16 package • Safety approvals: UL approved, 5000 VRMS for 1 minute, CSA approved, IEC/EN/DIN-EN 60747-5-5 approved VIORM = 1230 VPEAK Specifications • 1.5 A maximum peak output current • 1.0 A minimum peak output current • 250 ns maximum propagation delay over temperature range • 100 ns maximum pulse width distortion (PWD) • 50 kV/μs minimum common mode rejection (CMR) at VCM = 1500 V • ICC(max) < 5 mA maximum supply current • Wide VCC operating range: 15 V to 30 V over temperature range • 1.0 A Miller Clamp. Clamp pin short to VEE if not used • Wide operating temperature range: –40°C to 105°C VCLAMP VCC1 • Desaturation Detection 16 VCLAMP VE Applications • Isolated IGBT/Power MOSFET gate drive • AC and brushless DC motor drives 1, 4 15 SHIELD VLED • Industrial inverters and Uninterruptible Power Supply (UPS) CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Pin Description 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE 7 8 ANODE VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VCLAMP CATHODE VEE 10 9 Pin Symbol Description 1 VS Input Ground 2 VCC1 Positive input supply voltage. (3.3 V to 5.5 V) 3 FAULT Fault output. FAULT changes from a high impedance state to a logic low output within 5 μs of the voltage on the DESAT pin exceeding an internal reference voltage of 6.5 V. FAULT output is an open collector which allows the FAULT outputs from all ACPL-331J in a circuit to be connected together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller. 4 VS Input Ground 5 CATHODE Cathode 6 ANODE Anode 7 ANODE Anode 8 CATHODE Cathode 9 VEE Output supply voltage. 10 VCLAMP Miller clamp 11 VOUT Gate drive voltage output 12 VEE Output supply voltage. 13 VCC2 Positive output supply voltage 14 DESAT Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 6.5 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 μs. 15 VLED LED anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only) 16 VE Common (IGBT emitter) output supply voltage. Ordering Information ACPL-331J is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Package ACPL-331J -000E SO-16 -500E Surface Mount Tape& Reel X X X IEC/EN/DIN EN 60747-5-5 Quantity X 45 per tube X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-331J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: ACPL-331J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. 2 Package Outline Drawings ACPL-331J 16-Lead Surface Mount Package 0.018 (0.457) 0.050 (1.270) 16 15 14 13 12 11 10 LAND PATTERN RECOMMENDATION 9 TYPE NUMBER DATE CODE A 331J YYWW 1 2 3 4 0.458 (11.63) 0.295 ± 0.010 (7.493 ± 0.254) 5 6 7 0.085 (2.16) 8 0.406 ± 0.10 (10.312 ± 0.254) 0.025 (0.64) 0.345 ± 0.010 (8.763 ± 0.254) 9° 0.018 (0.457) 0.138 ± 0.005 (3.505 ± 0.127) 0- 8° 0.025 MIN. 0.408 ± 0.010 (10.363 ± 0.254) ALL LEADS TO BE COPLANAR ± 0.002 0.008 ± 0.003 (0.203 ± 0.076) STANDOFF Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the ACPL331J’s white mold compound is normal and does note affect device performance or reliability. Floating Lead Protrusion is 0.25 mm (10 mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. 3 Regulatory Information The ACPL-331J is approved by the following organizations: IEC/EN/DIN EN 60747-5-5 UL Approval under: DIN EN 60747-5-5 (VDE 0884-5):2011-11 EN 60747-5-5:2011 Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol Characteristic Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000Vrms I – IV I – IV I – IV I – III Climatic Classification 40/100/21 Pollution Degree (DIN VDE 0110/39) 2 Unit Maximum Working Insulation Voltage VIORM 1230 Vpeak Input to Output Test Voltage, Method b**, VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 2306 Vpeak Input to Output Test Voltage, Method a**, VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 1968 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Case Temperature TS 175 °C Input Current IS, INPUT 400 mA Output Power PS, OUTPUT 1200 mW Insulation Resistance at TS, VIO = 500 V RS >109 Ω Safety-limiting values – maximum values allowed in the event of a failure * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802. ** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles. Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7) 1400 P S , OUTPUT P S , INPUT 1200 PS - POWER - mW 1000 800 600 400 200 0 0 25 50 75 100 125 150 175 200 TS - CASE TEMPERATURE - °C 4 Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-331J Units Conditions Minimum External Air Gap (Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. >175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C 2 Output IC Junction Temperature TJ 125 °C 2 Average Input Current IF(AVG) 25 mA 1 Peak Transient Input Current (<1 μs pulse width, 300pps) IF(TRAN) 1.0 A Reverse Input Voltage VR 5 V “High” Peak Output Current IOH(PEAK) 1.5 A 3 “Low” Peak Output Current IOL(PEAK) 1.5 A 3 Positive Input Supply Voltage VCC1 -0.5 7.0 V FAULT Output Current IFAULT 8.0 FAULT Pin Voltage VFAULT -0.5 VCC1 V Total Output Supply Voltage (VCC2 - VEE) -0.5 35 V Negative Output Supply Voltage (VE - VEE) -0.5 15 V Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE) V Gate Drive Output Voltage VO(PEAK) -0.5 VCC2 V Peak Clamping Sinking Current IClamp 1.0 A Miller Clamping Pin Voltage VClamp -0.5 VCC2 V DESAT Voltage VDESAT VE VE + 10 V Output IC Power Dissipation PO 600 mW 2 Input IC Power Dissipation PI 150 mW 2 Solder Reflow Temperature Profile See Package Outline Drawings section mA 6 Table 4. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Operating Temperature TA - 40 105 °C 2 Total Output Supply Voltage (VCC2 - VEE) 15 30 V 7 Negative Output Supply Voltage (VE - VEE) 0 15 V 4 Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE) V Input Current (ON) IF(ON) 8 12 mA Input Voltage (OFF) VF(OFF) - 3.6 0.8 V 5 Table 5. Electrical Specifications (DC) Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol FAULT Logic Low Output Voltage VFAULTL FAULT Logic High Output Current IFAULTH High Level Output Current IOH Low Level Output Current IOL Low Level Output Current During Fault Condition IOLF 90 High Level Output Voltage VOH VCC-2.9 VCC-2.0 Low Level Output Voltage VOL 0.17 Clamp Pin Threshold Voltage VtClamp 2.0 V Clamp Low Level Sinking Current ICL 0.7 A VO = VEE + 2.5 High Level Supply Current ICC2H 2.5 5 mA IO = 0 mA Low Level Supply Current ICC2L 2.5 5 mA IO = 0 mA Blanking Capacitor Charging Current ICHG 0.13 -0.24 -0.33 mA Blanking Capacitor Discharge Current IDSCHG 10 30 DESAT Threshold VDESAT 6 6.5 UVLO Threshold VUVLO+ 10.5 11.6 VUVLO- 9.2 10.3 UVLO Hysteresis (VUVLO+ - VUVLO-) 0.4 1.3 Threshold Input Current Low to High IFLH Threshold Input Voltage High to Low VFHL 0.8 Input Forward Voltage VF 1.2 Temperature Coefficient of Input Forward Voltage ΔVF/ΔTA Input Reverse Breakdown Voltage BVR Input Capacitance CIN 6 Min. -0.3 Typ. Max. Units 0.1 0.4 V IFAULT = 1.1 mA, VCC1 = 5.5V 0.1 0.4 V IFAULT = 1.1 mA, VCC1 = 3.3V 0.02 0.5 μA VFAULT = 5.5 V, VCC1 = 5.5V 0.002 0.3 μA VFAULT = 3.3 V, VCC1 = 3.3V -0.75 -1.0 0.3 0.75 1.0 0.21 Test Conditions 140 2.0 230 0.5 -1.3 5 70 Note 4, 18 5 A VO = VCC2 – 4 A VO = VCC2 – 15 A VO = VEE + 2.5 A VO = VEE + 15 3 mA VOUT - VEE = 14 V 6 V IO = -650 μA 2, 4, 20 V IO = 100 mA 3, 5, 21 3 5, 19 5 7, 8, 9, 23 6, 7, 23 9 VDESAT = 2 V 8, 24 9, 10 mA VDESAT = 7.0 V 25 7.5 V VCC2 -VE >VUVLO- 9, 27 12.5 V VO > 5 V 7, 9, 11 11.1 V VO < 5 V 7, 9, 12 V 6 mA IO = 0 mA, VO > 5 V V 1.6 Fig. 1.95 V IF = 10 mA mV/°C V IR = 10 μA pF f = 1 MHz, VF = 0 V 9 Table 6. Switching Specifications (AC) Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level tPLH 100 180 250 ns tPHL 100 180 250 ns 1, 10, 11, 12, 13, 26 13, 15 Propagation Delay Time to Low Output Level Rg = 20 Ω, Cg = 5 nF, f = 10 kHz, Duty Cycle = 50%, IF = 10 mA, VCC2 = 30 V 20 Pulse Width Distortion PWD -100 Propagation Delay Difference Between Any Two Parts or Channels (tPHL - tPLH) PDD -150 100 ns 14, 17 150 ns 17, 16 Rise Time tR 50 ns Fall Time tF 50 ns DESAT Sense to 90% VO Delay tDESAT(90%) 0.15 0.3 μs CDESAT = 100pF, RF=2.1kΩ, Rg = 20 Ω, Cg = 5 nF, VCC2 = 30 V 14, 27, 34 DESAT Sense to 10% VO Delay tDESAT(10%) 1.1 1.5 μs CDESAT = 100pF, RF=2.1kΩ , Rg = 20 Ω, Cg = 5 nF, VCC2 = 30 V 15, 16, 17, 27, 34 DESAT Sense to Low Level FAULT Signal Delay tDESAT(FAULT) 0.25 0.5 μs CDESAT = 100 pF, RF = 2.1 kΩ, CF = Open, Rg = 20 Ω, Cg = 5 nF, VCC2 = 30 V 27, 34 18 27, 34 19 34 20 28, 29, 30, 31 21 CDESAT = 100 pF, RF = 2.1 kΩ, CF = 1 nF, Rg = 20 Ω, Cg = 5 nF, VCC2 = 30 V 0.8 0.25 μs CDESAT = 100pF, RF = 2.1 kΩ, Rg = 20 Ω, Cg = 5 nF, VCC2 = 30 V DESAT Sense to DESAT Low Propagation Delay tDESAT(LOW) DESAT Input Mute tDESAT(MUTE) 5 RESET to High Level FAULT Signal Delay tRESET(FAULT) 0.3 1 2.0 μs CDESAT = 100pF, RF = 2.1 kΩ, Rg = 20 Ω, Cg = 5 nF, VCC1 = 5.5V, VCC2 = 30 V 0.8 1.5 2.5 μs CDESAT = 100pF, RF = 2.1 kΩ, Rg = 20 Ω, Cg = 5 nF, VCC1 = 3.3V, VCC2 = 30 V 15 25 kV/μs TA = 25°C, IF = 10 mA VCM = 1500 V, VCC2 = 30 V, RF = 2.1 kΩ, CF = 15 pF 50 60 15 25 50 60 Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity 7 |CMH| |CML| 19 μs TA = 25°C, IF = 10 mA VCM = 1500 V, VCC2 = 30 V, RF = 2.1 kΩ, CF = 1 nF kV/μs TA = 25°C, VF = 0 V VCM = 1500 V, VCC2 = 30 V, RF = 2.1 kΩ, CF = 15 pF TA = 25°C, VF = 0 V VCM = 1500 V, VCC2 = 30 V, RF = 2.1 kΩ, CF = 1 nF 21, 26 28, 29, 30, 31 22 Table 7. Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 5000 Input-Output Resistance RI-O Input-Output Capacitance Output IC-to-Pins 9 &10 Thermal Resistance Typ. Max. Units Test Conditions Vrms RH < 50%, t = 1 min., TA = 25°C Fig. Note 24, 25 > 109 Ω VI-O = 500 V 25 CI-O 1.3 pF freq=1 MHz θ09-10 30 °C/W TA = 25°C Notes: 1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C. 2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating. 3. Maximum pulse width = 10 μs. This value is intended to allow for component tolerances for designs with IO peak minimum = 1.0 A. Derate linearly from 2.0 A at +25°C to 1.5 A at +105°C. This compensates for increased IOPEAK due to changes in VOL over temperature. 4. This supply is optional. Required only when negative gate drive is implemented. 5. Maximum pulse width = 50 μs. 6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details. 7. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 12.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero units. 8. Maximum pulse width = 1.0 ms. 9. Once VO of the ACPL-331J is allowed to go high (VCC2 - VE > VUVLO+), the DESAT detection feature of the ACPL-331J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 is increased from 0V to above VUVLO+, DESAT will remain functional until VCC2 is decreased below VUVLO-. Thus, the DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant IGBT protection. 10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details. 11. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE 12. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE 13. This load condition approximates the gate load of a 1200 V/75A IGBT. 14. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit. 15. As measured from IF to VO. 16. The difference between tPHL and tPLH between any two ACPL-331J parts under the same test conditions. 17. As measured from ANODE, CATHODE of LED to VOUT 18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. 19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply voltage dependent. 20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation (Auto Reset) topic in the application information section. 21. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). 22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V). 23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 μA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used. 24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table. 25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together. 26. Split resistors network with a ratio of 1:1 is needed at input LED1. See Figure 31. 8 IF tr tf 90% 50% V OUT 10% tPLH tPHL Figure 1. Timing Curve ____ I 0.25 OUT = -650uA -0.5 VOL - OUTPUT LOW VOLTAGE - V (VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V 0 -1 -1.5 -2 -2.5 -40 -20 0 20 40 60 80 0.2 0.15 0.1 0.05 0 -40 105 Figure 2. VOH vs. temperature _ _ _ _ 105 C ______ 25 o C --------- -40 o C 20 60 oC 80 105 _ _ _ _ 105 o C ______ 25 o C --------- -40 o C 3 VOL - OUTPUT LOW VOLTAGE - V 29 28 27 26 25 40 T A - TEMPERATURE - 4 o V OH - HIGH OUTPUT VOLTAGE DROP - V 0 Figure 3. VOL vs. temperature 30 0.0 0.2 I OH Figure 4. VOH vs. IOH 9 -20 TA - TEMPERATURE - oC 0.4 0.6 - OUTPUT HIGH CURRENT - A 0.8 1.0 2 1 0 0 0.5 IOL - OUTPUT LOW CURRENT - A Figure 5. VOL vs. IOL 1 1.5 2.65 3.25 - ---- ---- I CC2 H ICC2 - OUTPUT SUPPLY CURRENT - mA ICC2 - OUTPUT SUPPLY CURRENT - mA 3.50 _________ I CC2 L 3.00 2.75 2.50 2.25 2.00 -40 -20 0 20 40 T A - TEMPERATURE - 60 80 105 2.25 15 -0.25 7.0 VDESAT - DESAT THRESHOLD - V ICH - BLANKING CAPACITOR CHARGING CURRENT - mA 2.35 7.5 -0.30 -20 0 20 40 60 80 250 -20 0 20 40 T A - TEMPERATURE - 60 150 0 80 105 oC 300 ---------- t PLH _______tPHL -20 30 Figure 9. DESAT threshold vs. temperature 200 100 -40 -40 oC TP - PROPAGATION DELAY - ns 300 20 25 VCC2 - SUPPLY VOLTAGE - V 6.5 6.0 105 Figure 8. ICHG vs. temperature TP - PROPAGATION DELAY - ns 2.45 Figure 7. ICC2 vs. VCC2 T A -TEMPERATURE - 20 40 T A - TEMPERATURE - Figure 10. Propagation delay vs. temperature 10 2.55 -0.20 -40 CC2 H _________ I CC2 L oC Figure 6. ICC2 vs. temperature -0.35 --------- I 60 oC 80 105 ---------- t PLH _______tPHL 250 200 150 100 15 20 25 Vcc - SUPPLY VOLTAGE - V Figure 11. Propagation delay vs. supply voltage 30 300 300 250 TP - PROPAGATION DELAY - ns TP - PROPAGATION DELAY - ns ---------- t PLH _______tPHL 200 150 100 10 20 30 LOAD RESISTANCE - ohm 40 150 0 20 40 T A - TEMPERATURE - 60 80 30 40 50 2.0 ------- V CC2 =15V _____ V CC2 =30V 1.5 1.0 0.5 0.0 -40 105 -20 0 oC 20 40 60 T A - TEMPERATURE - Figure 14. DESAT sense to 90% VOUT delay vs. temperature 80 105 oC Figure 15. DESAT sense to 10% VOUT delay vs. temperature TDESAT10% - DESAT Sense to 10% Vo Delay - ms 4.0 ------- V CC2 =15V _____ V CC2 =30V 3.0 20 Figure 13. Propagation delay vs. load capacitance 200 -20 10 LOAD CAPACITANCE - nF 250 100 -40 0 TDESAT10% - DESAT Sense to 10% Vo Delay - us TDESAT90% - DESAT Sense to 90% Vo Delay - ns 100 50 Figure 12. Propagation delay vs. load resistance TDESAT10% - DESAT Sense to 10% Vo Delay - us 200 0 0 2.0 1.0 0.0 0.012 ------- V CC2 =15V _____ V CC2 =30V 0.008 0.004 0.000 10 20 30 LOAD RESISTANCE-ohm 40 Figure 16. DESAT sense to 10% VOUT delay vs. load resistance 11 ---------- t PLH _______ tPHL 50 0 10 20 30 40 LOAD CAPACITANCE-nF Figure 17. DESAT sense to 10% VOUT delay vs. load capacitance 50 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE VE 16 VLED 15 DESAT 14 0.1μF VCC2 13 15V Pulsed 7 ANODE 8 CATHODE VEE 12 IOUT VOUT 11 VCLAMP 10 VEE 9 +_ 0.1μF +_ 30V 10mA Figure 18. IOH Pulsed test circuit 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VCLAMP 10 VEE 9 0.1μF 15V Pulsed IOUT 7 ANODE 8 CATHODE 0.1μF +_ +_ 30V Figure 19. IOL Pulsed test circuit 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE 7 ANODE 8 CATHODE 10mA Figure 20. VOH Pulsed test circuit 12 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VCLAMP 10 VEE 9 0.1μF VOUT 0.1μF +_ 650μA 30V 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VCLAMP 10 VEE 9 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VCLAMP 10 VEE 9 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VCLAMP 10 VEE 9 0.1μF 100mA 7 ANODE 8 CATHODE VOUT 0.1μF +_ 30V Figure 21. VOL Pulsed test circuit 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE 7 ANODE 8 CATHODE 0.1μF ICC2 0.1μF +_ 30V 10mA Figure 22. ICC2H test circuit 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE 7 ANODE 8 CATHODE Figure 23. ICC2L test circuit 13 0.1μF ICC2 0.1μF +_ 30V 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VCLAMP 10 VEE 9 VE 16 VLED 15 DESAT 14 ICHG 7 ANODE 8 CATHODE 0.1μF 0.1μF +_ 30V 10mA Figure 24. ICHG Pulsed test circuit VS 2 VCC1 3 FAULT +_ 1 7V 0.1μF IDSCHG 4 VS 5 CATHODE 6 ANODE 7 ANODE 8 CATHODE VCC2 13 VEE 12 VOUT 11 VCLAMP 10 VEE 9 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 0.1μF +_ 30V Figure 25. IDSCHG test circuit 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE 0.1μF VOUT 20Ω 10mA, 10kHz, 50% Duty Cycle 7 ANODE 8 CATHODE Figure 26. tPLH, tPHL, tf, tr, test circuit 14 VCLAMP 10 VEE 9 5nF 0.1μF +_ 30V 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 VOUT 11 VIN RF=2.1kΩ VFAULT 0.1μF CF 5V +_ VOUT 20Ω 7 ANODE 8 CATHODE VCLAMP 10 VEE 9 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 10mA 0.1μF +_ 30V 5nF Figure 27. tDESAT fault test circuit 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 5V RF=2.1kΩ SCOPE CF=15pF or 1nF 30V 0.1μF 20Ω 0.1μF 360Ω 5nF VCM Figure 28. CMR Test circuit LED2 off 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 5V RF=2.1kΩ SCOPE CF=15pF or 1nF 30V 0.1μF 20Ω 0.1μF 360Ω Figure 29. CMR Test Circuit LED2 on 15 VCM 5nF 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 5V RF=2.1kΩ CF=15pF or 1nF 30V 0.1μF μ SCOPE 20Ω 0.1μF μ 360Ω 5nF VCM Figure 30. CMR Test circuit LED1 off 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 5V RF=2.1kΩ CF=15pF or 1nF 30V 5 CATHODE 6 ANODE 7 ANODE 8 CATHODE 0.1μF 6 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 SCOPE 20Ω 0.1μF 360Ω VCM Figure 31. CMR Test Circuit LED1 on 16 5V 5nF Split resistors network with a ratio of 1:1 13 Application Information VCC2 UVLO Product Overview Description The ACPL-331J is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT / MOSFET gate drive circuit with fault protection and feedback into one SO-16 package. Active Miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. An optically isolated power output stage drives IGBTs with power ratings of up to 100 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. An output IC provides local protection for the IGBT to prevent damage during over current, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in “watchdog” circuit, UVLO monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input control circuitry, the output power stage, and two optical channels. The output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal. Under normal operation, the LED1 directly controls the IGBT gate through the isolated output detector IC, and LED2 remains off. When an IGBT fault is detected, the output detector IC immediately begins a “soft” shutdown sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive over voltages. Simultaneously, this fault status is transmitted back to the input via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. During power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the ACPL-331J’s output low. Once the output is in the high state, the DESAT (VCE) detection feature of the ACPL-331J provides IGBT protection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection. 17 ANODE CATHODE 6, 7 D R I V E R 5, 8 LED1 11 14 VOUT DESAT DESAT 9, 12 SHIELD VEE VCLAMP VCC1 2 3 10 LED2 FAULT VS 16 1, 4 15 SHIELD VCLAMP VE VLED Figure 32. Block Diagram of ACPL-331J Recommended Application Circuit The ACPL-331J has an LED input gate control, and an open collector fault output suitable for wired ‘OR’ applications. The recommended application circuit shown in Figure 33 illustrates a typical gate drive implementation using the ACPL-331J. The following describes about driving IGBT. However, it is also applicable to MOSFET. Depending upon the MOSFET or IGBT gate threshold requirements, designers may want to adjust the VCC supply voltage (Recommended VCC = 17.5V for IGBT and 12.5V for MOSFET). The two supply bypass capacitors (0.1 μF) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5mA) power supply suffices. The desaturation diode DDESAT 600V/1200V fast recovery type, trr below 75ns (e.g. ERA34-10) and capacitor CBLANK are necessary external components for the fault detection circuitry. The gate resistor RG serves to limit gate charge current and controls the IGBT collector voltage rise and fall times. The open collector fault output has a passive pull-up resistor RF (2.1 kΩ) and a 1000 pF filtering capacitor, CF. A 47 kΩ pull down resistor RPULL-DOWN on VOUT provides a predictable high level output voltage (VOH). In this application, the IGBT gate driver will shut down when a fault is detected and fault reset by next cycle of IGBT turn on. Application notes are mentioned at the end of this datasheet. 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 ANODE 7 ANODE 8 CATHODE VE 16 0.1μF + _ VLED 15 RF 0.1μF DESAT 14 CBLANK 100 Ω DDESAT RG + _ CF VCC2 13 VEE 12 VOUT 11 Q1 R + _ VCLAMP 10 VEE + HVDC + VCE - RPULL--DOWN 9 Q2 + VCE - 3-PHASE AC - HVDC Figure 33. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp Description of Operation Normal Operation During normal operation, VOUT of the ACPL-331J is controlled by input LED current IF (pins 5, 6, 7 and 8), with the IGBT collector-to-emitter voltage being monitored through DESAT. The FAULT output is high. See Figure 34. is an internal feedback channel which brings the FAULT output low for the purpose of notifying the micro-controller of the fault condition. Fault Reset Fault Condition The DESAT pin monitors the IGBT Vce voltage. When the voltage on the DESAT pin exceeds 6.5 V while the IGBT is on, VOUT is slowly brought low in order to “softly” turn-off the IGBT and prevent large di/dt induced voltages. Also Figure 34. Fault Timing diagram activated Once fault is detected, the output will be muted for 5 μs (minimum). All input LED signals will be ignored during the mute period to allow the driver to completely soft shut-down the IGBT. The fault mechanism can be reset by the next LED turn-on after the 5us (minimum) mute time. See Figure 34. t DESAT(LOW) IF Reset done during the next LED turn-on 6.5V V DESAT t BLANK t DESAT(10%) 90% VOUT 10% t DESAT(90%) FAULT 50% t DESAT(FAULT) t DESAT(MUTE) Figure 34. Fault Timing diagram 18 t RESET(FAULT) 50% Output Control Slow IGBT Gate Discharge during Fault Condition The outputs (VOUT and FAULT) of the ACPL-331J are controlled by the combination of IF, UVLO and a detected IGBT Desat condition. Once UVLO is not active (VCC2 VE > VUVLO), VOUT is allowed to go high, and the DESAT (pin 14) detection feature of the ACPL-331J will be the primary source of IGBT protection. Once VCC2 is increased from 0V to above VUVLO+, DESAT will remain functional until VCC2 is decreased below VUVLO-. Thus, the DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant IGBT protection. When a desaturation fault is detected, a weak pull-down device in the ACPL-331J output drive stage will turn on to ‘softly’ turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below VEE + 2 Volts, at which time the large pull down device clamps the IGBT gate to VEE. DESAT Fault Detection Blanking Time Desaturation Detection and High Current Protection The ACPL-331J satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and an optically isolated fault status feedback signal into a single 16-pin surface mount package. The fault detection method, which is adopted in the ACPL-331J is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false ‘fault’ signals. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-331J limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly conservative over current threshold is not needed to protect the IGBT. The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT threshold. This time period, called the DESAT blanking time is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor. The nominal blanking time is calculated in terms of external capacitance (CBLANK), FAULT threshold voltage (VDESAT ), and DESAT charge current (ICHG) as tBLANK = CBLANK x VDESAT / ICHG. The nominal blanking time with the recommended 100pF capacitor is 100pF * 6.5 V / 240 μA = 2.7 μsec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time represents the longest time it will take for the ACPL-331J to respond to a DESAT fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after approximately 3 μsec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. The recommended 100pF capacitor should provide adequate blanking as well as fault response times for most applications. IF UVLO(VCC2-VE) DESAT Function Pin 3 (FAULT) Output VOUT ON Active Not Active High Low ON Not Active Active (with DESAT fault) Low (FAULT) Low ON Not Active Active (no DESAT fault) High (or no fault) High OFF Active Not Active High Low OFF Not Active Not Active High Low 19 Under Voltage Lockout The ACPL-331J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the ACPL-331J output low during power-up. IGBTs typically require gate voltages of 15 V to achieve their rated VCE(ON) voltage. At gate voltages below 13 V typically, the VCE(ON) voltage increases dramatically, especially at higher currents. At very low gate voltages (below 10 V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever insufficient operating supply (VCC2) is applied. Once VCC2 exceeds VUVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. As VCC2 is increased from 0 V (at some level below VUVLO+), first the DESAT protection circuitry becomes active. As VCC2 is further increased (above VUVLO+), the UVLO clamp is released. Before the time the UVLO clamp is released, the DESAT protection is already active. Therefore, the UVLO and DESAT Fault detection feature work together to provide seamless protection regardless of supply voltage (VCC2). Active Miller Clamp A Miller clamp allows the control of the Miller current during a high dV/dt situation and can eliminate the use of a negative supply voltage in most of the applications. During turn-off, the gate voltage is monitored and the clamp output is activated when gate voltage goes below 2V (relative to VEE). The clamp voltage is VOL+2.5V typ for a Miller current up to 1100mA. The clamp is disabled when the LED input is triggered again. Other Recommended Components The application circuit in Figure 33 includes an output pull-down resistor, a DESAT pin protection resistor, a FAULT pin capacitor, and a FAULT pin pullup resistor and Active Miller Clamp connection. Output Pull-Down Resistor During the output high transition, the output voltage rapidly rises to within 3 diode drops of VCC2. If the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly VCC2-3(VBE) to VCC2 within a period of several microseconds. To limit the output voltage to VCC2-3(VBE), a pull-down resistor, RPULL-DOWN between the output and VEE is recommended to sink a static current of several 650 μA while the output is high. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, Rpull-down = [VCC2-3 * (VBE)] / 650 μA. 20 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 VCC RG RPULL-DOWN Figure 35. Output pull-down resistor. DESAT Pin Protection Resistor The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substantial current out of the driver if protection is not used. To limit this current to levels that will not damage the driver IC, a 100 ohm resistor should be inserted in series with the DESAT diode. The added resistance will not alter the DESAT threshold or the DESAT blanking time. 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 100pF 100 Ω VCC RG Figure 36. DESAT pin protection. DDESAT Capacitor on FAULT Pin for High CMR Pull-up Resistor on FAULT Pin Rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. A 1000 pF capacitor should be connected between the fault pin and ground to achieve adequate CMOS noise margins at the specified CMR value of 50 kV/μs. The FAULT pin is an open collector output and therefore requires a pull-up resistor to provide a high-level signal. Also the FAULT output can be wire ‘OR’ed together with other types of protection (e.g. over-temperature, overvoltage, over-current ) to alert the microcontroller. Other Possible Application Circuit (Output Stage) 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 0.1μF 0.1μF 0.1μF Optional R2 RG Optional R1 6 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 +_ + HVDC Q1 RPULL-DOWN +_ * Q2 + VCE - + VCE - 3-PHASE AC - HVDC Figure 37. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used) VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 0.1μF 0.1μF 0.1μF Optional R2 RG Optional R1 6 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE VEE 9 +_ + HVDC Q1 RPULL-DOWN +_ * Q2 + VCE - + VCE - R3 Figure 38. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application. 21 3-PHASE AC - HVDC Thermal Model The ACPL-331J is designed to dissipate the majority of the heat through pins 1, 4, 5 & 8 for the input IC and pins 9 & 12 for the output IC. (There are two VEE pins on the output side, pins 9 and 12, for this purpose.) Heat flow through other pins or through the package directly into ambient are considered negligible and not modeled here. In order to achieve the power dissipation specified in the absolute maximum specification, it is imperative that pins 5, 9, and 12 have ground planes connected to them. As long as the maximum power specification is not exceeded, the only other limitation to the amount of power one can dissipate is the absolute maximum junction temperature specification of 125°C. The junction temperatures can be calculated with the following equations: Tji = Pi (θi5 + θ5A) + TA Tjo = Po (θo9,12 + θ9,12A) + TA Tjo Tji Tl9, 12 = 30°C/W TI1 = 60°C/W TP9, 12 TP1 T1A = 50°C/W* T9, 12A = 50°C/W* TA where Pi = power into input IC and Po = power into output IC. Since θ5A and θ9,12A are dependent on PCB layout and airflow, their exact number may not be available. Therefore, a more accurate method of calculating the junction temperature is with the following equations: Tji = Pi θi5 + TP5 Tjo = Po θo9,12 + TP9,12 These equations, however, require that the pin 5 and pins 9, 12 temperatures be measured with a thermal couple on the pin at the ACPL-331J package edge. If the calculated junction temperatures for the thermal model in Figure 39 is higher than 125°C, the pin temperature for pins 9 and 12 should be measured (at the package edge) under worst case operating environment for a more accurate estimate of the junction temperatures. Tji = junction temperature of input side IC Tjo = junction temperature of output side IC TP5 = pin 5 temperature at package edge TP9,12 = pin 9 and 12 temperature at package edge θI5 = input side IC to pin 5 thermal resistance θo9,12 = output side IC to pin 9 and 12 thermal resistance θ5A = pin 5 to ambient thermal resistance θ9,12A = pin 9 and 12 to ambient thermal resistance *The θ5A and θ9,12A values shown here are for PCB layouts with reasonable air flow. This value may increase or decrease by a factor of 2 depending on PCB layout and/or airflow. Figure 39. ACPL-331J Thermal Model Related Application Notes AN5314 – Active Miller Clamp AN5324 - Desaturation Fault Detection AN5315 – “Soft” Turn-off Feature AN1043 – Common-Mode Noise : Sources and Solutions AN02-0310EN - Plastics Optocoupler Product ESD and Moisture Sensitivity For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-0119EN - October 25, 2012