2.0 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback Technical Data HCPL-316J Features • “Soft” IGBT Turn-off • Integrated Fail-Safe IGBT Protection – Desat (VCE ) Detection – Under Voltage Lock-Out Protection (UVLO) with Hysterisis • User Configurable: Inverting, Non-inverting, Auto-Reset, Auto-Shutdown • Drive IGBTs up to IC = 150 A, VCE = 1200 V • Optically Isolated, FAULT Status Feedback • SO-16 Package • CMOS/TTL Compatible • 500 ns Max. Switching Speeds • Wide Operating VCC Range: 15 to 30 Volts • -40°C to +100 °C Operating Temperature Range • 15 kV/µs Min. Common Mode Rejection (CMR) at VCM = 1500 V • Regulatory Approvals: UL, CSA, IEC/EN/DIN EN 607475-2 (891 Vpeak Working Voltage) Fault Protected IGBT Gate Drive +HV ISOLATION BOUNDARY ISOLATION BOUNDARY ISOLATION BOUNDARY HCPL - 316J HCPL - 316J HCPL - 316J 3-PHASE INPUT M HCPL - 316J HCPL - 316J ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY –HV FAULT MICRO-CONTROLLER Agilent’s 2.0 Amp Gate Drive Optocoupler with Integrated Desaturation (VCE) Detection and Fault Status Feedback makes IGBT VCE fault protection compact, affordable, and easy-to-implement while satisfying worldwide safety and regulatory requirements. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 Typical Fault Protected IGBT Gate Drive Circuit The HCPL-316J is an easy-to-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-toimplement. Features such as user configurable inputs, integrated VCE detection, under voltage lockout (UVLO), “soft” IGBT turn-off and isolated fault feedback provide maximum design flexibility and circuit protection. HCPL-316J 1 VIN+ VE 16 2 VIN- VLED2+ 15 3 VCC1 DESAT 14 * CBLANK 100 Ω + – µC RF 4 GND1 5 VCC2 13 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1- VEE 9 DDESAT + + – * VF – + RG VCE – – * + + RPULL-DOWN VCE – * THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED. Figure 1. Typical Desaturation Protected Gate Drive Circuit, Non-Inverting. Description of Operation during Fault Condition 1. DESAT terminal monitors the IGBT VCE voltage through DDESAT. 2. When the voltage on the DESAT terminal exceeds 7 volts, the IGBT gate voltage (VOUT) is slowly lowered. 3. FAULT output goes low, notifying the microcontroller of the fault condition. 4. Microcontroller takes appropriate action. Output Control The outputs (VOUT and FAULT) of the HCPL-316J are controlled by the combination of VIN, UVLO and a detected IGBT Desat condition. As indicated in the below table, the HCPL-316J can be configured as inverting or non-inverting using the VIN+ or VIN- inputs respectively. When an inverting configuration is desired, VIN+ must be held high and VINtoggled. When a non-inverting configuration is desired, V INmust be held low and VIN+ toggled. Once UVLO is not active (VCC2 - V E > VUVLO ), VOUT is allowed to go high, and the VIN+ VIN- UVLO (VCC2 - VE) X X Low X High X X X High Low Active X X X Not Active DESAT (pin 14) detection feature of the HCPL-316J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection. Desat Condition Detected on Pin 14 X Yes X X No Pin 6 (FAULT) Output X Low X X High VOUT Low Low Low Low High 3 Product Overview Description The HCPL-316J is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit with fault protection and feedback into one SO-16 package. TTL input logic levels allow direct interface with a microcontroller, and an optically isolated power output stage drives IGBTs with power ratings of up to 150 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. An VLED1+ output IC provides local protection for the IGBT to prevent damage during overcurrents, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in “watchdog” circuit monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. designed on a bipolar process, while the output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal. Both optical channels are completely controlled by the input and output ICs respectively, making the internal isolation boundary transparent to the microcontroller. Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input control circuitry, the output power stage, and two optical channels. The input Buffer IC is Under normal operation, the input gate control signal directly controls the IGBT gate through the isolated output detector IC. LED2 remains off and a fault latch in the input buffer IC is disabled. When an IGBT fault is detected, the output detector IC immediately begins a “soft” shutdown sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive overvoltages. Simultaneously, this fault status is transmitted back to the input buffer IC via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. VLED1- 7 8 13 INPUT IC VIN+ VIN- 12 1 LED1 2 D R I V E R UVLO 11 14 VCC1 VOUT DESAT 3 DESAT 9,10 SHIELD LED2 RESET FAULT VCC2 VC 16 5 FAULT 6 SHIELD OUTPUT IC 4 GND1 15 VLED2+ VEE VE During power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the HCPL-316J’s output low. Once the output is in the high state, the DESAT (VCE ) detection feature of the HCPL-316J provides IGBT protection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection. 4 Package Pin Out 1 VIN+ VE 16 2 VIN- VLED2+ 15 3 VCC1 DESAT 14 4 GND1 VCC2 13 5 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1- VEE 9 Pin Descriptions Symbol Description VIN+ Non-inverting gate drive voltage output (VOUT) control input. VINInverting gate drive voltage output (VOUT) control input. VCC1 Positive input supply voltage. (4.5 V to 5.5 V) GND1 RESET Input Ground. FAULT reset input. A logic low input for at least 0.1 µs, asynchronously resets FAULT output high and enables V IN. Synchronous control of RESET relative to VIN is required. RESET is not affected by UVLO. Asserting RESET while VOUT is high does not affect V OUT. FAULT Fault output. FAULT changes from a high impedance state to a logic low output within 5 µs of the voltage on the DESAT pin exceeding an internal reference voltage of 7 V. FAULT output remains low until RESET is brought low. FAULT output is an open collector which allows the FAULT outputs from all HCPL-316Js in a circuit to be connected together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller. LED 1 anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only) LED 1 cathode. This pin must be connected to ground. VLED1+ VLED1- Symbol Description VE Common (IGBT emitter) output supply voltage. VLED2+ LED 2 anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only) DESAT Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 7 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 µs. See Note 25. VCC2 Positive output supply voltage. VC Collector of output pull-up triple-darlington transistor. It is connected to VCC2 directly or through a resistor to limit output turn-on current. VOUT VEE Gate drive voltage output. Output supply voltage. 5 Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-316J#XXXX No Option = 16-Lead, Surface Mt. package, 45 per tube. 500 = Tape and Reel Packaging Option, 850 per reel. XXXE = Lead Free Option. Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “–” Option data sheets available. Contact Agilent sales representative, authorized distributor, or visit our WEB site at http://www.agilent.com/view/optocouplers. Package Outline Drawings 16-Lead Surface Mount Dimensions in inches (millimeters) 0.018 (0.457) LAND PATTERN RECOMMENDATION 16 15 14 13 12 11 10 9 TYPE NUMBER DATE CODE A 316J YYWW Notes: Initial and continued variation in the color of the HCPL-316J’s white mold compound is normal and does note affect device performance or reliability. Floating Lead Protrusion is 0.25 mm (10 mils) max. 0.050 (1.270) 0.458 (11.63) 0.295 ± 0.010 (7.493 ± 0.254) 0.085 (2.16) 1 2 3 4 5 6 7 8 0.406 ± 0.10 (10.312 ± 0.254) 0.025 (0.64) 0.345 ± 0.010 (8.986 ± 0.254) 9° 0.018 (0.457) 0.138 ± 0.005 (3.505 ± 0.127) 0–8° 0.025 MIN. 0.408 ± 0.010 (10.160 ± 0.254) ALL LEADS TO BE COPLANAR ± 0.002 0.008 ± 0.003 (0.203 ± 0.076) STANDOFF Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, V CC2 - VEE = 30 V, VE - VEE = 0 V, and TA = +25°C. Parameter Symbol Min. Typ. Max. Units Input-Output Momentary VISO 3750 Vrms Withstand Voltage Resistance (Input - Output) RI-O >109 Ω Capacitance (Input - Output) CI-O 1.3 pF Output IC-to-Pins 9 &10 θO9-10 30 °C/W Thermal Resistance Input IC-to-Pin 4 Thermal Resistance θI4 60 Test Conditions Note RH < 50%, t = 1 min., 1, 2, TA = 25°C 3 VI-O = 500 Vdc 3 f = 1 MHz TA = 100°C 6 Solder Reflow Thermal Profile 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK TEMP. 245°C PEAK TEMP. 240°C PEAK TEMP. 230°C 200 2.5°C ± 0.5°C/SEC. SOLDERING TIME 200°C 30 SEC. 160°C 150°C 140°C 30 SEC. 3°C + 1°C/–0.5°C 100 PREHEATING TIME 150°C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 50 0 100 150 200 TIME (SECONDS) Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 260 +0/-5 °C 217 °C RAMP-UP 3 °C/SEC. MAX. 150 - 200 °C RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. 25 t 25 °C to PEAK TIME NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C 250 7 Regulatory Information The HCPL-316J has been approved by the following organizations: IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b** VIORM x 1.875 = VPR, 100% Production Test with t m = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a** VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage** (Transient Overvoltage tini = 10 sec) Safety-limiting values - maximum values allowed in the event of a failure, also see Figure 2. Case Temperature Input Power Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic Unit VIORM I - IV I - III I - II 55/100/21 2 891 VPEAK VPR 1670 VPEAK VPR 1336 VPEAK VIOTM 6000 VPEAK TS P S, INPUT PS, OUTPUT RS 175 400 1200 >109 °C mW mW Ω * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802. ** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles. 1400 PS, OUTPUT PS, INPUT PS – POWER – mW 1200 1000 800 600 400 200 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C Figure 2. Dependence of Safety Limiting Values on Temperature. 8 Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap L(101) 8.3 mm Measured from input terminals to output (Clearance) terminals, shortest distance through air. Minimum External L(102) 8.3 mm Measured from input terminals to output Tracking (Creepage) terminals, shortest distance path along body. Minimum Internal Plastic 0.5 mm Through insulation distance conductor to Gap (Internal Clearance) conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI >175 Volts DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Storage Temperature Ts -55 125 Operating Temperature TA -40 100 Output IC Junction Temperature TJ 125 Peak Output Current |Io(peak)| 2.5 Fault Output Current IFAULT 8.0 Positive Input Supply Voltage VCC1 -0.5 5.5 Input Pin Voltages VIN+, VIN- and VRESET -0.5 VCC1 Total Output Supply Voltage (VCC2 - VEE) -0.5 35 Negative Output Supply Voltage (VE - VEE) -0.5 15 Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE) Gate Drive Output Voltage Vo(peak) -0.5 VCC2 Collector Voltage VC VEE + 5 V VCC2 DESAT Voltage VDESAT VE VE + 10 Output IC Power Dissipation PO 600 Input IC Power Dissipation PI 150 Solder Reflow Temperature Profile See Package Outline Drawings section Units °C A mA Volts Note 4 5 6 mW 4 Recommended Operating Conditions Parameter Operating Temperature Input Supply Voltage Total Output Supply Voltage Negative Output Supply Voltage Positive Output Supply Voltage Collector Voltage Symbol TA VCC1 (VCC2 - VEE) (VE - VEE) (VCC2 - VE) VC Min. -40 4.5 15 0 15 VEE + 6 Max. +100 5.5 30 15 30 - (VE - VEE) VCC2 Units °C Volts Note 28 9 6 9 Electrical Specifications (DC) Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Logic Low Input Voltages Symbol VIN+L, VIN-L, VRESETL Min. Logic High Input Voltages VIN+H, VIN-H, VRESETH 2.0 Logic Low Input Currents IIN+L, IIN-L, IRESETL -0.5 -0.4 FAULT Logic Low Output Current IFAULTL 5.0 12 FAULT Logic High Output Current IFAULTH -40 High Level Output Current IOH -0.5 -2.0 -1.5 Low Level Output Current IOL 0.5 2.0 2.3 Low Level Output Current during Fault Condition IOLF 90 160 230 mA High Level Output Voltage VOH VC - 3.5 VC -2.9 VC - 2.5 VC - 2.0 V Low Level Output Voltage VOL 0.17 VC - 1.5 VC - 1.2 VC 0.5 High Level Input Supply Current ICC1H 17 22 mA Low Level Input Supply Current ICCIL 6 11 VIN+ = VIN- = 0 V, VCC1 = 5.5 V Output Supply Current ICC2 2.5 5 VOUT open Low Level Collector Current ICL 0.3 1.0 IOUT = 0 High Level Collector Current ICH 0.3 1.3 IEL -0.7 3.0 0 IOUT = 0 IOUT = -650 µA VE Low Level Supply Current 1.8 -0.4 VE High Level Supply Current IEH -0.5 -0.14 0 Blanking Capacitor Charging Current ICHG -0.13 -0.25 -0.33 -0.18 -0.25 -0.33 Blanking Capacitor Discharge Current IDSCHG 10 50 UVLO Threshold VUVLO+ 11.6 12.3 13.5 11.1 12.4 VOUT < 5 V 7.5 VCC2 -VE >VUVLO - VUVLO- Typ. UVLO Hysteresis (VUVLO+ VUVLO-) 0.4 1.2 DESAT Threshold V DESAT 6.5 7.0 Max. 0.8 Units V mA Test Conditions Fig. Note VIN = 0.4 V VFAULT = 0.4 V 30 µA VFAULT = VCC1 31 A VOUT = VCC2 - 4 V VOUT = VCC2 - 15 V V 3, 8, 7 5 VOUT = VEE + 2.5 V VOUT = VEE + 15 V 32 4, 9, 33 7 5 VOUT - VEE = 14 V 5, 34 8 IOUT = -100 mA IOUT = -650 µA IOUT = 0 IOUT = 100 mA 6, 8, 9, 10, 35 11 VIN+ = VCC1 = 5.5 V, VIN- = 0 V 7, 9, 36 26 10, 37, 38 11,12, 39,40 11 15, 59 27 15, 58 15, 57 14, 61 27 14, 40 25 VDESAT = 0 - 6 V VDESAT = 0 - 6 V, TA = 25°C - 100°C VDESAT = 7 V 13, 41 11, 12 VOUT > 5 V 43 42 9, 11, 13 9, 11, 14 16, 44 11 10 Switching Specifications (AC) Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter VIN to High Level Output Propagation Delay Time Symbol tPLH Min. 0.10 Typ. 0.30 Max. 0.50 VIN to Low Level Output Propagation Delay Time tPHL 0.10 0.32 0.50 PWD -0.30 0.02 (tPHL - tPLH) PDD -0.35 Pulse Width Distortion Propagation Delay Difference Between Any Two Parts 10% to 90% Rise Time Units µs Test Conditions Fig. Note Rg = 10 Ω 17,18,19, 15 Cg = 10 nF, 20,21,22, f = 10 kHz, Duty Cycle = 50% 45,54, 55 0.30 16,17 0.35 17, 18 tr 0.1 90% to 10% Fall Time DESAT Sense to 90% VOUT Delay tf tDESAT(90%) 0.1 0.3 0.5 Rg = 10 Ω, Cg = 10 nF 23,56 DESAT Sense to 10% VOUT Delay tDESAT(10%) 2.0 3.0 VCC2 - VEE = 30 V 24,28, 46,56 DESAT Sense to Low Level FAULT Signal Delay tDESAT(FAULT) 1.8 5 DESAT Sense to DESAT Low Propagation Delay tDESAT(LOW) 0.25 RESET to High Level FAULT Signal Delay tRESET(FAULT) 3 RESET Signal Pulse Width PWRESET 0.1 UVLO to VOUT High Delay t UVLO ON 7 45 20 VCC2 = 1.0 ms 4.0 19 25, 47, 56 20 56 21 26, 27, 56 22 49 13 ramp UVLO to VOUT Low Delay tUVLO OFF 6.0 Output High Level Common Mode Transient Immunity |CMH| 15 30 Output Low Level Common Mode Transient Immunity |CML | 15 30 14 kV/µs TA = 25°C , VCM = 1500 V, VCC2 = 30 V TA = 25°C, VCM = 1500 V, VCC2 = 30 V 50,51, 52,53 23 24 11 Notes: 1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/ EN/DIN EN 60747-5-2 Insulation Characteristic Table, if applicable. 2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table. 3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 4. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating. 5. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on IOH peak. Derate linearly from 3.0 A at +25°C to 2.5 A at +100°C. This compensates for increased I OPEAK due to changes in VOL over temperature. 6. This supply is optional. Required only when negative gate drive is implemented. 7. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%. 8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details. 9. 15 V is the recommended minimum operating positive supply voltage (V CC2 - VE ) to ensure adequate margin in excess of the maximum V UVLO+ threshold of 13.5 V. For High Level Output Voltage testing, V OH is measured with a dc load current. When driving capacitive loads, V OH will approach VCC as IOH approaches zero units. 10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 11. Once V OUT of the HCPL-316J is allowed to go high (V CC2 - V E > V UVLO), the DESAT detection feature of the HCPL-316J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until V UVLO- < 12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection. 12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details. 13. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE. 14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE. 15. This load condition approximates the gate load of a 1200 V/75A IGBT. 16. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit. 17. As measured from VIN+, VIN- to VOUT . 18. The difference between t PHL and tPLH between any two HCPL-316J parts under the same test conditions. 19. Supply Voltage Dependent. 20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. 21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. 22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 µs is the guaranteed minimum FAULT signal pulse width when the HCPL-316J is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the end of this data sheet for further details. 23. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3K Ω pull-up resistor is needed in fault detection mode. 24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V). 25. Does not include LED2 current during fault or blanking capacitor discharge current. 26. To clamp the output voltage at VCC - 3 VBE , a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used. 27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE. 28. In most applications VCC1 will be powered up first (before VCC2 ) and powered down last (after VCC2 ). This is desirable for maintaining control of the IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down. 12 7 IOL – OUTPUT LOW CURRENT 1.8 1.6 1.4 1.2 1.0 -40 -20 0 20 40 60 80 6 5 VOUT = VEE + 15 V VOUT = VEE + 2.5 V 4 3 2 1 0 -40 -20 100 Figure 3. IOH vs. Temperature. 60 40 80 100 -1 -2 -3 20 40 60 80 0.20 IOUT = 100 mA 0.15 0.10 0.05 0 -40 -20 100 Figure 6. V OH vs. Temperature. 0 20 40 60 80 100 ICC1 – SUPPLY CURRENT – mA 4 3 2 1 0.5 1.0 1.5 2.0 IOL – OUTPUT LOW CURRENT – A Figure 9: VOL vs. I OL. 50 25 2.5 0 5 10 15 20 25 30 15 ICC1H ICC1L 10 5 0 -40 -20 0 20 40 60 80 TA – TEMPERATURE – °C Figure 10. ICC1 vs. Temperature. +100°C +25°C -40°C 28.8 28.6 28.4 28.2 28.0 27.8 27.6 27.4 0 0.2 0.4 0.8 0.6 1.0 Figure 8. VOH vs. IOH . 20 +100°C +25°C -40°C -40°C 25°C 100°C 75 IOH – OUTPUT HIGH CURRENT – A Figure 7. V OL vs. Temperature. 6 0 0.1 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C 5 125 29.0 VOH – OUTPUT HIGH VOLTAGE – V IOUT = -650 µA IOUT = -100 mA 0 150 Figure 5. IOLF vs. VOUT. 0.25 0 -4 -40 -20 175 VOUT – OUTPUT VOLTAGE – V Figure 4. IOL vs. Temperature. VOL – OUTPUT LOW VOLTAGE – V (VOH -VCC) – HIGH OUTPUT VOLTAGE DROP – V 20 200 TA – TEMPERATURE – °C TA – TEMPERATURE – °C VOL – OUTPUT LOW VOLTAGE – V 0 100 ICC2 – OUTPUT SUPPLY CURRENT – mA IOH – OUTPUT HIGH CURRENT – A 2.0 IOLF – LOW LEVEL OUTPUT CURRENT DURING FAULT CONDITION – mA Performance Plots 2.6 2.5 2.4 ICC2H ICC2L 2.3 2.2 -40 -20 0 20 40 60 80 TA – TEMPERATURE – °C Figure 11: ICC2 vs. Temperature. 100 -0.15 2.55 2.50 2.45 ICC2H ICC2L 2.40 2.35 15 20 25 0.50 IE -VE SUPPLY CURRENT – mA 2.60 ICHG – BLANKING CAPACITOR CHARGING CURRENT – mA -0.20 -0.25 -0.30 -40 -20 30 80 2 -40°C +25°C +100°C 1 0 0.5 1.0 1.5 2.0 0.35 6.5 6.0 -40 -20 0 20 40 60 80 PROPAGATION DELAY – µs 0.35 0.30 0.25 25 VCC – SUPPLY VOLTAGE – V Figure 18. Propagation Delay vs. Supply Voltage. 30 0.40 60 80 100 0.4 0.3 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 17. Propagation Delay vs. Temperature. 0.50 VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V 0.35 0.30 0.25 -50 40 tPHL tPLH 0.2 -40 -20 100 0.45 tPHL tPLH 20 0.5 Figure 16. DESAT Threshold vs. Temperature. 0.40 0 Figure 14. IE vs. Temperature. TA – TEMPERATURE – °C Figure 15. I C vs. I OUT. 20 0.40 TA – TEMPERATURE – °C 7.0 IOUT (mA) 0.20 15 0.45 0.30 -40 -20 100 TP – PROPAGATION DELAY – µs VDESAT – DESAT THRESHOLD – V IC (mA) 60 7.5 3 TP – PROPAGATION DELAY – µs 40 Figure 13. ICHG vs. Temperature. 4 0 20 IEH IEL TA – TEMPERATURE – °C VCC2 – OUTPUT SUPPLY VOLTAGE – V Figure 12. ICC2 vs. VCC2. 0 PROPAGATION DELAY – µs ICC2 – OUTPUT SUPPLY CURRENT – mA 13 0 50 TEMPERATURE – °C Figure 19. V IN to High Propagation Delay vs. Temperature. 100 0.45 VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V 0.40 0.35 0.30 0.25 -50 0 50 TEMPERATURE – °C Figure 20. V IN to Low Propagation Delay vs. Temperature. 100 14 0.40 0.45 0.40 tPLH tPHL tPLH tPHL 0.25 DELAY – µs 0.30 0.30 0 20 60 40 80 0.20 100 0 10 20 30 40 0.25 -50 50 LOAD RESISTANCE – Ω LOAD CAPACITANCE – nF Figure 21. Propagation Delay vs. Load Capacitance. 2.4 DELAY – µs 2.5 2.0 100 50 Figure 23. DESAT Sense to 90% Vout Delay vs. Temperature. 0.008 2.6 VCC2 = 15 V VCC2 = 30 V 0 TEMPERATURE – °C Figure 22. Propagation Delay vs. Load Resistance. 3.0 DELAY – µs 0.35 0.30 0.25 VEE = 0 V VEE = -5 V VEE = -10 V VEE = -15 V VCC2 = 15 V VCC2 = 30 V 0.006 DELAY – ms 0.20 0.40 0.35 DELAY – µs DELAY – µs 0.35 2.2 2.0 1.5 0.004 0.002 1.8 1.0 -50 0 50 1.6 -50 100 TEMPERATURE – °C 0 12 VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V VCC2 = 15 V VCC2 = 30 V 10 DELAY – µs 0.0025 0.0020 8 6 0.0015 20 30 40 LOAD RESISTANCE – Ω Figure 27. DESAT Sense to 10% Vout Delay vs. Load Resistance. 50 4 -50 0 50 100 0 0 10 20 30 40 50 LOAD CAPACITANCE – nF Figure 25. DESAT Sense to Low Level Fault Signal Delay vs. Temperature. 0.0030 DELAY – µs 100 TEMPERATURE – °C Figure 24. DESAT Sense to 10% Vout Delay vs. Temperature. 0.0010 10 50 150 TEMPERATURE – °C Figure 28. RESET to High Level Fault Signal Delay vs. Temperature. Figure 26. DESAT Sense to 10% Vout Delay vs. Load Capacitance. 15 Test Circuit Diagrams VLED2+ VIN+ VE VIN- VLED2+ VCC1 DESAT VCC1 DESAT GND1 VCC2 GND1 VCC2 RESET VC FAULT VOUT IFAULT 0.1 µF 5V VEE VLED1- VEE VLED1- VEE Figure 31. IFAULTH Test Circuit. VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 VC VOUT VLED1+ VEE VLED1- VEE 0.1 µF 30 V 0.1 µF 15 V PULSED + – + – 30 V IOUT VIN+ VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 0.1 µF 0.1 µF Figure 32. IOH Pulsed Test Circuit. RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE VE 0.1 µF VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE 5V 30 V 0.1 µF + – IOUT 30 V + – 14 V Figure 34. IOLF Test Circuit. 30 V 0.1 µF 0.1 µF + – IOUT 30 V 15 V PULSED + – Figure 33. I OL Pulsed Test Circuit. + – + – VOUT VLED1+ FAULT 5V FAULT VEE RESET 0.1 µF VC IFAULT + – + – RESET VLED1+ VIN+ 5V + – 5V Figure 30. IFAULTL Test Circuit. 0.1 µF 0.1 µF 10 mA 0.1 µF + – 0.1 µF VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE Figure 35. V OH Pulsed Test Circuit. 0.1 µF + – – + VE VIN- + – 0.4 V + – VIN+ + – 4.5 V 0.1 µF 30 V 0.1 µF + – VOUT 30 V 2A PULSED 0.1 µF 16 VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VOUT VLED1+ VEE VLED1- VEE 5.5 V 30 V 30 V VOUT 0.1 µF VIN+ VE VIN- VLED2+ VCC1 DESAT 0.1 µF 5V + – ICC1 + – VCC2 VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE VIN+ VE VIN- VLED2+ VCC1 DESAT 0.1 µF 30 V VCC2 GND1 RESET VC RESET VC FAULT VOUT FAULT VOUT VLED1+ VEE VLED1+ VEE VLED1- VEE VLED1- VEE Figure 38. ICC1L Test Circuit. VIN- VE ICC2 GND1 VIN+ VIN+ Figure 37. I CC1H Test Circuit. VE VLED2+ VCC1 DESAT GND1 VCC2 0.1 µF 0.1 µF 5V 30 V ICC2 RESET VC FAULT VOUT VLED1+ VLED1- 0.1 µF + – VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 VC FAULT VOUT VEE VLED1+ VEE VEE VLED1- VEE + – Figure 40. ICC2L Test Circuit. + – 0.1 µF ICHG RESET 0.1 µF 0.1 µF 30 V Figure 39. I CC2H Test Circuit. + – 5.5 V ICC1 + – Figure 36. VOL Test Circuit. 0.1 µF + – 0.1 µF 100 mA VC FAULT 0.1 µF 30 V Figure 41. ICHG Pulsed Test Circuit. 0.1 µF + – + – 0.1 µF + – 5V VE + – VIN+ 0.1 µF 30 V 0.1 µF + – 0.1 µF 30 V 17 VE VCC1 DESAT GND1 VCC2 RESET IDSCHG 0.1 µF + – 5V 30 V 0.1 µF + – GND1 VCC2 VEE VLED1- VEE VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT SWEEP 0.1 µF 0.1 µF 15 V + – VIN- VIN + – VE 0.1 µF 5V + – 15 V 0.1 µF 3k VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1+ VEE VLED1- VEE VLED1- VEE Figure 44. DESAT Threshold Test Circuit. 0.1 µF VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE Figure 46. tDESAT(10%) Test Circuit. 0.1 µF 30 V 0.1 µF 0.1 µF VOUT + – 30 V 10 Ω 10 nF Figure 45. tPLH, t PHL, t r, tf Test Circuit. VIN 0.1 µF 0.1 µF + – VIN+ VOUT Figure 43. UVLO Threshold Test Circuit. + – VIN+ SWEEP + – VC VEE 30 V 0.1 µF Figure 42. IDSCHG Test Circuit. 3k DESAT VLED1+ VLED1- 5V VCC1 VEE VLED1+ + – VLED2+ VOUT VOUT 0.1 µF VIN- FAULT FAULT 0.1 µF VE RESET VC 10 mA VIN+ + – 30 V VOUT 10 Ω 10 nF 0.1 µF 5V 0.1 µF + – 3k VFAULT 30 V VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC F