54ABT646 Octal Transceivers and Registers with TRI-STATE ® Outputs General Description Features The ’ABT646 consists of bus transceiver circuits with TRI-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. n Independent registers for A and B buses n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9457701 Ordering Code Military Package Number Package Description 54ABT646J-QML J24A 24-Lead Ceramic Dual-In-Line 54ABT646W-QML W24C 24-Lead Cerpack 54ABT646E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100209 www.national.com 54ABT646 Octal Transceivers and Registers with TRI-STATE Outputs July 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100209-4 DS100209-3 Pin Descriptions Pin Description Names A0–A7 Data Register A Inputs/ TRI-STATE Outputs B0–B7 Data Register B Inputs/ TRI-STATE Outputs CPAB, Clock Pulse Inputs CPBA www.national.com SAB, SBA Select Inputs OE Output Enable Input DIR Direction Control Input 2 Connection Diagrams (Continued) Storage from Bus to Register Real Time Transfer A-Bus to B-Bus DS100209-7 FIGURE 3. DS100209-5 FIGURE 1. Transfer from Register to Bus Real Time Transfer B-Bus to A-Bus DS100209-8 FIGURE 4. DS100209-6 FIGURE 2. Inputs Data I/O (Note 1) Function OE DIR CPAB CPBA SAB SBA A0–A7 B0–B7 H X H or L H or L X X H X N X X X H X X N X X Clock Bn Data into B Register L H X X L X An to Bn — Real Time (Transparent Mode) L H N X L X L H H or L X H X L H N X H X Clock An Data into A Register and Output to Bn L L X X X L Bn to An — Real Time (Transparent Mode) L L X N X L L L X H or L X H B Register to An (Stored Mode) L L X N X H Clock Bn Data into B Register and Output to An Isolation Input Input Input Output Clock An Data into A Register Clock An Data into A Register A Register to Bn (Stored Mode) Output Input Clock Bn Data into B Register H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. 3 www.national.com Logic Diagram DS100209-9 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 4 Absolute Maximum Ratings (Note 2) Over Voltage Latchup (I/O) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current 10V Recommended Operating Conditions −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to +5.5V −0.5V to VCC Note 3: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) −500 mA DC Electrical Characteristics Symbol Parameter ABT646 Min Typ VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 2.0 54ABT 2.5 54ABT 2.0 VOL Output LOW Voltage VID Input Leakage Test IIH Input HIGH Current Units 54ABT VCC V 0.8 V −1.2 V Recognized HIGH Signal Min V Min 0.55 Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −24 mA, (An, Bn) IOL = 48 mA, (An, Bn) V Min V 0.0 µA Max 7 µA Max VIN = 7.0V (Non-I/O Pins) 100 µA Max VIN = 5.5V (An, Bn) −5 µA Max VIN = 0.5V (Non-I/O Pins) (Note 5) VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); OE = 2.0V VOUT = 0.5V (An, Bn); OE = 2.0V 4.75 5 5 IBVI Conditions Max −5 IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 5) VIN = VCC (Non-I/O Pins) IIH + IOZH Output Leakage Current 50 µA 0V–5.5V IIL + IOZL Output Leakage Current −50 µA 0V–5.5V IOS Output Short-Circuit Current −275 mA Max ICEX Output HIGH Leakage Current 50 µA Max IZZ Bus Drainage Test 100 µA 0.0V ICCH Power Supply Current 250 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max Outputs TRI-STATE; All Others GND ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V All Other Outputs at VCC or GND ICCD Dynamic ICC (Note 5) 0.18 mA/MHz Max Outputs Open OE and DIR = GND, Non-I/O = GND or VCC (Note 4) One Bit toggling, 50% duty cycle No Load −100 5 VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND www.national.com DC Electrical Characteristics (Continued) Note 4: For 8-bit toggling, ICCD < 1.4 mA/MHz. Note 5: Guaranteed but not tested. AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Fig. Units No. CL = 50 pF Min Max fmax Max Clock Frequency 125 tPLH Propagation Delay 2.2 8.8 tPHL Clock to Bus 1.7 8.8 tPLH Propagation Delay 1.5 7.9 tPHL Bus to Bus 1.5 7.9 tPLH Propagation Delay 1.5 8.1 tPHL SBA or SAB to An to Bn 1.5 8.9 tPZH Enable Time 1.0 7.3 tPZL OE to An or Bn 1.9 8.8 tPHZ Disable Time 1.5 9.3 tPLZ OE to An or Bn 1.5 9.3 tPZH Enable Time 1.0 7.7 tPZL DIR to An or Bn 2.2 9.5 tPHZ Disable Time 1.5 8.7 tPLZ DIR to An or Bn 1.5 9.2 MHz ns Figure 8 ns Figure 8 ns Figure 8 ns Figure 10 ns Figure 10 ns Figure 10 ns Figure 10 AC Operating Requirements Symbol 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Fig. Units No. 3.5 ns Figure 11 1.0 ns Figure 11 4.0 ns Figure 9 Parameter CL = 50 pF Min tS(H) Setup Time, HIGH tS(L) or LOW Bus to Clock tH(H) Hold Time, HIGH tH(L) or LOW Bus to Clock tW(H) Pulse Width, tW(L) HIGH or LOW Max Capacitance Symbol Parameter Typ Units CIN Input Capacitance 5 pF CI/O (Note 6) Output Capacitance 11 pF Note 6: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 6 Conditions TA = 25˚C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) Capacitance (Continued) tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus DS100209-18 tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus DS100209-19 tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus DS100209-20 tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus DS100209-21 tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus DS100209-22 DS100209-23 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 www.national.com Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Bus tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Bus DS100209-24 tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100209-25 tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Bus DS100209-26 DS100209-27 tPZH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus tPHZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus DS100209-28 DS100209-29 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 8 Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus tPLZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Bus DS100209-30 tPZL vs Load Capacitance 8 Outputs Switching, TA = 25˚C OE to Bus DS100209-31 tPZH vs Load Capacitance 8 Outputs Switching, TA = 25˚C OE to Bus DS100209-32 DS100209-33 tPLH and tPHL vs Number Output Switching VCC = 5.0V, TA = 25˚C CL = 50 pF, Clock to Bus DS100209-34 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 9 www.national.com Capacitance (Continued) ICC vs Frequency, Average, TA = 25˚C, VCC = 5.5V All Outputs Unloaded/Unterminated; All Outputs Switching in phase @50% Duty Cycle DS100209-35 tSET LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock tSET HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock DS100209-36 tHOLD LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock DS100209-37 tHOLD HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Clock DS100209-38 DS100209-39 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 10 AC Loading DS100209-10 *Includes jig and probe capacitance FIGURE 5. Standard AC Test Load DS100209-11 FIGURE 9. Propagation Delay, Pulse Width Waveforms DS100209-12 FIGURE 6. Test Input Signal Levels Input Pulse Requirements DS100209-13 FIGURE 10. TRI-STATE Output HIGH and LOW Enable and Disable Times Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 7. Test Input Signal Requirements DS100209-15 FIGURE 11. Setup Time, Hold Time and Recovery Time Waveforms DS100209-14 FIGURE 8. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 11 www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-in-Line Package (D) NS Package Number J24A 13 www.national.com 54ABT646 Octal Transceivers and Registers with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak Package (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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