NSC 74ABT16952CSSC

74ABT16952
16-Bit Registered Transceiver with TRI-STATEÉ Outputs
General Description
Features
The ’ABT16952 is a 16-bit registered transceiver. Two 8-bit
back to back registers store data flowing in both directions
between two bidirectional buses. Separate clock, clock enable and TRI-STATEÉ output enable signals are provided
for each register. The output pins are guaranteed to source
32 mA (24 mA mil.) and to sink 64 mA (48 mA mil).
Y
Y
Y
Y
Y
Commercial
Separate clock, clock enable and TRI-STATE output
enable provided for each register
A and B output sink capability of 64 mA source capability of 32 mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Package Number
Package Description
74ABT16952CSSC (Note 1)
MS56A
56-Lead (0.300× Wide) Molded Shrink Small Outline, JEDEC (SSOP)
74ABT16952CMTD (Notes 1, 2)
MTD56
56-Lead Molded Thin Shrink Small Outline, JEDEC (TSSOP)
Note 1: Devices also available in 13× reel. Use suffix e SSCX and MTDX.
Note 2: Contact factory for package availability.
Pin Descriptions
Pin Names
A0 – A16
B0 – B16
CPABn, CPBAn
CEAn, CEBn
OEABn, OEBAn
Connection Diagram
Description
Pin Assignment
for SSOP
Data Register A Inputs/
B-Register TRI-STATE Outputs
Data Register B Inputs/
A-Register TRI-STATE Outputs
Clock Pulse Inputs
Clock Enable
Output Enable Inputs
TL/F/11647 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation
TL/F/11647
RRD-B30M96/Printed in U. S. A.
http://www.national.com
74ABT16952 16-Bit Registered Transceiver with TRI-STATE Outputs
September 1996
Pin Descriptions (Continued)
Register Function Table (Applies to A or B Register)
Output Control
Internal
Q
Output
H
X
Z
Disable Outputs
L
L
L
H
L
H
Enable Outputs
OE
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Inputs
CE
Internal
Q
Function
CP
X
X
H
NC
Hold Data
L
H
L
L
L
L
L
H
Load Data
Function
D
Z
L
NC
e HIGH Impedance
e LOW-to-HIGH Transition
e No Change
Block Diagram
TL/F/11647 – 2
n for either byte 1 or byte 2
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2
Absolute Maximum Ratings (Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
VCC Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disable or Power-Off State
in the HIGH State
b 65§ C to a 150§ C
b 55§ C to a 125§ C
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
b 55§ C to a 150§ C
twice the rated IOL (mA)
b 500 mA
10V
Recommended Operating
Conditions
b 0.5V to a 7.0V
b 0.5V to a 7.0V
b 30 mA to a 5.0 mA
Free Air Ambient Temperature
Commercial
Supply Voltage
Commercial
Minimum Input Edge Rate
Data Input
Enable Input
Clock Input
b 0.5V to a 5.5V
b 0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
b 40§ C to a 85§ C
a 4.5V to a 5.5V
(DV/Dt)
50 mV/ns
20 mV/ns
100 mV/ns
DC Electrical Characteristics
Symbol
ABT16952
Parameter
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
74ABT
74ABT
VOL
Output LOW Voltage
74ABT
VID
Input Leakage Test
IIH
Input HIGH Current
IBVI
Input HIGH Current
Breakdown Test
IBVIT
Input HIGH Current
Breakdown Test (I/O)
IIL
Input LOW Current
IIH a IOZH
Typ
Max
2.0
Units
VCC
Conditions
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
b 1.2
V
Min
2.5
2.0
IIN e b18 mA (Non I/O Pins)
IOH e b3 mA (An, Bn)
IOH e b32 mA (An, Bn)
0.55
IOL e 64 mA (An, Bn)
V
0.0
IID e 1.9 mA (Non-I/O Pins)
All Other Pins Grounded
5
mA
Max
VIN e 2.7V (Non-I/O Pins) (Note 2)
VIN e VCC (Non-I/O Pins)
7
mA
Max
VIN e 7.0V (Non-I/O Pins)
100
mA
Max
VIN e 5.5V (An, Bn)
b5
mA
Max
VIN e 0.5V (Non-I/O Pins) (Note 2)
VIN e 0.0V (Non-I/O Pins)
Output Leakage Current
50
mA
0V – 5.5V
VOUT e 2.7V (An, Bn);
OEA or OEB e 2.0V
IIL a IOZL
Output Leakage Current
b 50
mA
0V – 5.5V
VOUT e 0.5V (An, Bn);
OEA or OEB e 2.0V
IOS
Output Short-Circuit Current
b 275
mA
Max
VOUT e 0V (An, Bn)
ICEX
Output HIGH Leakage Current
50
mA
Max
VOUT e VCC (An, Bn)
IZZ
Bus Drainage Test
100
mA
0.0V
VOUT e 5.5V (An, Bn);
All Others GND
ICCH
Power Supply Current
1.0
mA
Max
All Outputs HIGH
ICCL
Power Supply Current
60
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
ICCT
Additional ICC/Input
4.75
b 100
3
1.0
mA
Max
Outputs TRI-STATE;
All Others GND
2.5
mA
Max
VI e VCC b 2.1V; All Others
at VCC or GND
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DC Electrical Characteristics
Symbol
ICCD
ABT16952
Parameter
Dynamic ICC
(Note 2)
(Continued)
Min
Typ
Max
Units
VCC
mA/MHz
Max
No Load
0.18
Conditions
Outputs Open
OEA or OEB e GND,
Non-I/O e GND or VCC
One Bit toggling, 50% duty cycle
(Note 1)
Note 1: For 8-bit toggling, ICCD k 1.4 mA/MHz.
Note 2: Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
74ABT
74ABT
TA e a 25§ C
VCC e a 5.0V
CL e 50 pF
TA e b40§ C to a 85§ C
VCC e 4.5V to 5.5V
CL e 50 pF
Min
Max
Min
Units
Max
fmax
Max Clock
Frequency
tPLH
tPHL
Propagation Delay
CPABn or CPBAn to
An or Bn
1.5
1.5
5.3
5.3
1.5
1.5
5.3
5.3
ns
tPZH
tPZL
Output Enable Time
OEABn or OEBAn to
An or Bn
1.5
1.5
5.5
5.5
1.5
1.5
5.5
5.5
ns
tPHZ
tPLZ
Output Disable Time
OEABn or OEBAn to
An or Bn
1.5
1.5
6.0
6.0
1.5
1.5
6.0
6.0
ns
200
200
MHz
AC Operating Requirements
Symbol
Parameter
74ABT
74ABT
TA e a 25§ C
VCC e a 5.0V
CL e 50 pF
TA e b40§ C to a 85§ C
VCC e 4.5V to 5.5V
CL e 50 pF
Min
Max
Min
Units
Max
ts(H)
ts(L)
Setup Time, HIGH
or LOW An or Bn
to CPABn or CPBAn
2.5
2.5
2.5
2.5
ns
th(H)
th(L)
Hold Time, HIGH
or LOW An or Bn
to CPABn or CPBAn
1.5
1.5
1.5
1.5
ns
ts(H)
ts(L)
Setup Time, HIGH
or LOW CEAn or CEBn
to CPABn or CPBAn
2.5
2.5
2.5
2.5
ns
th(H)
th(L)
Hold Time, HIGH
or LOW CEAn or CEBn
to CPABn or CPBAn
1.5
1.5
1.5
1.5
ns
tw(H)
tw(L)
Pulse Width,
HIGH or LOW
to CPABn or CPBAn
3.0
3.0
3.0
3.0
ns
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4
Capacitance
Symbol
Parameter
Typ
Units
Conditions
TA e 25§ C
CIN
Input Capacitance
5
pF
VCC e 0V (Non I/O Pins)
CI/O (Note 1)
Output Capacitance
11
pF
VCC e 5.0V (An, Bn)
Note 1: CI/O is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012.
AC Loading
TL/F/11647 – 3
*Includes jig and probe capacitance
TL/F/11647 – 4
FIGURE 1. Standard AC Test Load
FIGURE 2a. Test Input Signal Levels
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 2b. Input Signal Requirements
TL/F/11647 – 5
FIGURE 3. Propagation Delay Waveforms for
Inverting and Non-Inveting Functions
TL/F/11647 – 6
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
5
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AC Loading (Continued)
TL/F/11647–7
FIGURE 5. TRI-STATE Output HIGH
and LOW Enable and Disable Times
TL/F/11647 – 8
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/11647 – 9
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6
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead SSOP (0.300× Wide) (SS)
74ABT16952CSSC or 74ABT16952CSSCX
NS Package Number MS56A
7
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74ABT16952 16-Bit Registered Transceiver with TRI-STATE Outputs
Physical Dimensions millimeters (Continued)
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
74ABT16952CMTD
NS Package Number MTD56
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