Low-Noise Matched Transistor Array ICs THAT 300 Series FEATURES APPLICATIONS • 4 Matched NPN Transistors • Low Noise Front Ends º 300 typical hfe of 100 º 300A minimum hfe of 150 º 300B minimum hfe of 300 • Microphone Preamplifiers • 4 Matched PNP Transistors º 320 typical hfe of 75 • 2 Matched PNP and 2 Matched NPN Transistors • Log/Antilog Amplifiers º 340 PNP typical hfe of 75 º 340 NPN typical hfe of 100 • Low Voltage Noise • Current Sources º 0.75 nV/ √Hz (PNP) º 0.8 nV/ √Hz (NPN) • High Speed • Current Mirrors º fT = 350 MHz (NPN) º fT = 325 MHz (PNP) • 500 μV matching between devices • Dielectrically Isolated for low crosstalk and high DC isolation • 36V VCEO • Multipliers Description The THAT 300, 320 and 340 are large geometry, 4-transistor, monolithic NPN and/or PNP arrays. They exhibit both high speed and low noise, with excellent parameter matching between transistors of the same gender. Typical base-spreading resistance is 25 Ω for the PNP devices (30 Ω for the low-gain NPNs), so their resulting voltage noise is under 1 nV/√Hz. This makes the 300 series ideally suited for low-noise amplifier input stages, log amplifiers, and many other applications. The four-NPN transistor array is available in versions selected for hfe with minimums of 150 (300A) or 300 (300B). Fabricated in a dielectrically isolated, complementary bipolar process, each transistor is electrically insulated from the others by a layer of insulating oxide (not the reverse-biased PN junctions Part Number 300P14-U 300S14-U used in conventional arrays). As a result, they exhibit inter-device crosstalk and DC isolation similar to that of discrete transistors. The resulting low collector-to-substrate capacitance produces a typical NPN fT of 350 MHz (325 MHz for the PNPs). Substrate biasing is not required for normal operation, though the substrate should be ac-grounded to optimize speed and minimize crosstalk. An eight-transistor bare-die array with similar performance characteristics (the THAT 380G) is also available from THAT Corporation. Please contact us directly or through your local distributor for more information. Military-grade temperature range packages are available from TT Semiconductor (see www.ttsemiconductor.com for more information). Configuration 4-Matched NPN Transistors, Beta = 60 min. 300AS14-U 4-Matched NPN Transistors, Beta = 150 min. 300BS14-U 4-Matched NPN Transistors, Beta = 300 min. 320P14-U 320S14-U 340P14-U 340S14-U 4-Matched PNP Transistors 2-Matched NPN Transistors and 2-Matched PNP Transistors Table 1. Ordering Information THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright © 2010, THAT Corporation. Document 600041 Rev 02 Package DIP14 SO14 SO14 SO14 DIP14 SO14 DIP14 SO14 Document 600041 Rev 02 Page 2 of 5 THAT 300 1 2 Q1 4 SUB SUB 5 6 Q3 THAT 320 14 1 13 2 Q1 Q2 3 12 3 11 4 10 5 9 6 SUB Q4 Q3 8 7 THAT 300 Series Transistor Array ICs THAT 340 1 13 2 14 13 Q1 Q2 SUB 12 3 11 4 10 5 9 6 Q2 12 SUB SUB 9 Q3 Q4 7 8 Figure 2. 320 Pinout 11 10 Q4 7 Figure 1. 300 Pinout 14 8 Figure 3. 340 Pinout SPECIFICATIONS 1 Absolute Maximum Ratings 2,3 NPN Collector-Emitter Voltage (BVCEO) NPN Collector-Base Voltage (BVCBO) PNP Collector-Emitter Voltage (BVCEO) PNP Collector-Base Voltage (BVCBO) Collector-Substrate Voltage (BVCS) 36 V 36V –36 V –36 V ± 100 V Collector Current Emitter Current Operating Temperature Range (TOP) Maximum Junction Temperature (TJMAX) Storage Temperature (TST) 30 mA 30 mA -40 to +85 °C +125 °C -45 to +125 °C NPN Electrical Characteristics 2 Parameter Symbol Conditions 300 / 340(Q1,Q2) Min Typ Max Min 300A Typ Max Min 300B Typ Max Units hfe VCB = 10 V, IC = 1 mA IC = 10 µA 60 — 100 100 — — 150 — — — — — 300 — — — — — NPN Current Gain Matching Δhfe VCB = 10V, IC = 1mA — 4 — — 4 — — 4 — % NPN Noise Voltage Density eN VCB = 10V, IC = 1 mA, 1kHz — 0.8 — — 0.9 — — 1 — nV√Hz NPN Gain-Bandwidth Product fT IC = 1 mA, VCB = 10V — 350 — — 350 — — 350 — MHz NPN ΔVBE 300: |VBE1-VBE2| ; |VBE3-VBE4| 340: |VBE1-VBE2| VOS IC = 1 mA IC = 10 mA — — 0.5 0.5 3 — — — 0.5 0.5 3 — — — 0.5 0.5 3 — mV mV NPN ΔIB 300: |IB1-IB2| ; |IB3-IB4| 340: |IB1-IB2| IOS IC = 1 mA IC = 10 μA — — 500 5 1500 — — — 200 2 600 — — — 100 1 300 — nA nA NPN Collector-Base Leakage Current ICBO VCB = 25 V — 25 — — 25 — — 25 — pA NPN Bulk Resistance rBE VCB = 0V, 10 μA < IC < 10mA — 2 — — 2 — — 2 — Ω NPN Base Spreading Resistance rbb VCB = 10 V, IC = 1 mA — 30 — — TBD — — TBD — Ω NPN Collector Saturation Voltage VCE(SAT) IC = 1 mA, IB = 100μA — 0.05 — — 0.05 — — 0.05 — V NPN Current gain THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright © 2010, THAT Corporation. All rights reserved. THAT 300 Series Transistor Array ICs Page 3 of 5 Document 600041 Rev 02 SPECIFICATIONS 1 (Cont’d) NPN Electrical Characteristics 2 (cont’d) Parameter Symbol Conditions 300 / 340(Q1,Q2) Min Typ Max Min 300A Typ Max Min 300B Typ Max Units NPN Output Capacitance COB VCB = 10V, IE = 0mA, 100kHz — 3 — — 3 — — 3 — pF NPN Breakdown Voltage BVCEO IC = 10 μAdc, IB = 0 36 40 — 36 40 — 36 40 — V Input Capacitance CEBO IC = 0 mA, VEB = 0 V — 5 — — 5 — — 5 — pF PNP Electrical Characteristics 2 Parameter Symbol Conditions Min Typ Max hfe VCB = -10 V IC = -1 mA IC = -10 μA 50 — 75 75 — — PNP Current Gain Units PNP Current Gain Matching Δhfe VCB = -10 V, IC = -1 mA — 5 — % PNP Noise Voltage Density eN VCB = -10 V, IC = -1 mA, 1 kHz — 0.75 — nV√Hz PNP Gain-Bandwidth Product fT IC = -1 mA, VCB = -10 V — 325 — MHz PNP ΔVBE 320: |VBE1-VBE2| ; |VBE3-VBE4| 340: |VBE1-VBE2| VOS IC = -1 mA IC = -10 μA — — 0.5 0.5 3 — mV mV PNP ΔIB 320: |IB1-IB2| ; |IB3-IB4| 340: |IB1-IB2| IOS IC = -1 mA IC = -10 μA — — 700 7 1800 — nA nA VCB = -25 V — –25 — pA PNP Collector-Base Leakage Current ICBO PNP Bulk Resistance rBE VCB = 0 V, -10μA > IC> -10 mA — 2 — Ω PNP Base Spreading Resistance rbb VCB = -10 V, IC = -1 mA — 25 — Ω PNP Collector Saturation Voltage VCE(SAT) IC = -1 mA, IB = -100 μA — –0.05 — V PNP Output Capacitance COB VCB = -10 V, IE = 0 mA, 100 kHz — 3 — pF PNP Breakdown Voltage BVCEO IC = -10 mAdc, IB = 0 -36 -40 — V Input Capacitance CEBO IC = 0 mA, VEB = 0 V — 6 — pF 1. All specifications are subject to change without notice. 2. Unless otherwise noted, TA = 25ºC. 3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this sp ecification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright © 2010, THAT Corporation. All rights reserved. Document 600041 Rev 02 Page 4 of 5 THAT 300 Series Transistor Array ICs Packaging and Soldering Information The THAT 300, 320 and 340 are available in 14-pin PDIP and 14-pin surface mount (SOIC) packages. Package dimensions are shown below. The 300-series packages are entirely lead-free. The lead-frames are copper, plated with successive layers of nickel, palladium, and gold. This approach makes it possible to solder these devices using lead-free and leadbearing solders. Neither the lead-frames nor the plastic mold compounds used in the 300-series contains any hazardous substances as specified in the European Union's Directive on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment 2002/95/EG of January 27, 2003. The surface-mount package is suitable for use in a 100% tin solder process. Package Characteristics Parameter Symbol Conditions Typ See Fig. 4 for dimensions 14 Pin PDIP DIP package soldered to board 100 Through-hole package θJA Thermal Resistance Environmental Regulation Compliance θJA See Fig. 5 for dimensions 14 Pin SOP SO package soldered to board 100 Soldering Reflow Profile Moisture Sensitivity Level ºC/W Complies with January 27, 2003 RoHS requirements Surface mount package Thermal Resistance Units ºC/W JEDEC JESD22-A113-D (250 ºC) MSL Above-referenced JEDEC soldering profile 1 Environmental Regulation Compliance Complies with RoHS requirements 0.750±0.004 (19.05±0.10) 0.050 (1.27) Typ 0.25±.004 (6.35±0.10) 1 0.157 0.245 (3.99) (6.2) Max Max 0.30 ±0.02 (7.62 ±0.5) 0.060 (1.52) Typ. 0.125±0.004 (3.18±0.10) 1 0.018 (0.46) Max 0.018 (0.46) 0.010 (0.25) 0.344 (8.74) Max 0.10 Typ. (2.54) 0.069 (1.75) Max 0.010 (0.25) Max 0.075 (1.91) Figure 4. Dual-In-Line Package Outline Figure 5. Surface-Mount Package Outline THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright © 2010, THAT Corporation. All rights reserved. THAT 300 Series Transistor Array ICs Page 5 of 5 Document 600041 Rev 02 THAT Corporation believes all the information furnished in this data sheet is accurate and reliable. However we assume no responsibility for its use nor for any infringements of third-party intellectual property which may result from its use. LIFE SUPPORT POLICY THAT Corporation ICs are not designed for use in life support equipment where a malfunction of our ICs might reasonably result in injury or death. Customers who use or sell our ICs for such life suport application do so at their own risk, and shall hold THAT Corporation harmless from any and all claims, damages, suits, or expenses resulting from such use or sale. CAUTION: THIS IS AN ESD (ELECTROSTATIC DISCHARGE) SENSITIVE DEVICE Electrostatic charges in the range of several kV can accumulate on the human body as well as test and assembly equipment. This device can be damaged by the currents generated by electrostatic discharge from bodies and equipment. Moreover, the transistors in this device are unprotected in order to maximize performance and flexibility. Accordingly, they are more sensitive to ESD damage than many other ICs which include protection devices at their inputs. Note that all of the pins are susceptible. Use ESD-preventative measures when storing and handling this device. Unused devices should be stored in conductive packaging. Packaging should be discharged to the destination socket before the devices are removed from their packages. ESD damage can occur to these devices even after they are installed in a board-level assembly. Circuits should include specific and appropriate ESD protection. Revision History Revision ECO Date Changes 00 — April 2004 Release 01 2393 April 2010 Changed Max. Operating Temperature from 70 °C to 85 °C. 2 02 2460 Sept. 2010 -Added high hfe versions Models 300A and 300B with accompanying specifications and information. -Revised Features, Applications, and Description sections -Revised Maximum Rating section -Added NPN Breakdown Voltage spec. -Added PNP Breakdown Voltage spec. -Added Packaging Characteristics Table. -Revised disclaimer text — THAT and c are registered trademarks of THAT Corporation. THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright © 2010, THAT Corporation. All rights reserved. Page 1 2 3 3 4 5