PIXART ADNS-3080

ADNS-3080
High-Performance Optical Mouse Sensor
Data Sheet
Description
Features
The ADNS-3080 is a high performance addition to PixArt
Imaging popular ADNS family of optical mouse
sensors.
 High speed motion detection – up to 40 ips and 15g
The ADNS-3080 is based on a new, faster architecture with
improved navigation. The sensor is capable of sensing high
speed mouse motion - up to 40 inches per second and
acceleration up to 15g – for increased user precision and
smoothness.
 Programmable frame rate over 6400 frames per
second
The ADNS-3080 along with the ADNS-2120-001 trim lens,
ADNS-2220-001 assembly clip and HLMP-EG3E-xxxxx led
form a complete, compact optical mouse tracking system.
There are no moving parts, which means high reliability and
less maintenance for the end user. In addition, precision
optical alignment is not required, facilitating high volume
assembly.
 New architecture for greatly improved optical
navigation technology
 SmartSpeed self-adjusting frame rate for optimum
performance
 Serial port burst mode for fast data transfer
 400 or 1600 cpi selectable resolution
 Single 3.3 volt power supply
 Four-wire serial port along with Chip Select, Power
Down, and Reset pins
Applications
The sensor is programmed via registers through a four-wire
serial port. It is packaged in a 20-pin staggered dual inline
package (DIP).
 Mice for game consoles and computer games
Theory of Operation
 Trackballs
The ADNS-3080 is based on Optical Navigation Technology, which measures changes in position by optically
acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of
movement.
 Integrated input devices
 Mice for desktop PC’s, Workstations, and portable
PC’s
It contains an Image Acquisition System (IAS), a Digital
Signal Processor (DSP), and a four-wire serial port.
The IAS acquires microscopic surface images via the lens
and illumination system. These images are processed
by the DSP to determine the direction and distance of
motion. The DSP calculates the Δx and Δy relative displacement values.
An external microcontroller reads the Δx and Δy information from the sensor serial port. The microcontroller then
translates the data into PS2 or USB signals before sending
them to the host PC or game console.
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PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
High-Performance Optical Mouse Sensor
Pinout
Pin
Name
Description
1
NCS
Chip select (active low input)
2
MISO
Serial data output
(Master In/Slave Out)
2
20
1
19
SCLK
Serial clock input
3
4
MOSI
Serial data input
(Master Out/Slave In)
4
17
LED_CTRL
LED control output
5
6
RESET
Reset input
6
7
NPD
Power down (active low input)
7
8
OSC_OUT
Oscillator output
9
GUARD
Oscillator gnd for PCB guard
(optional)
9
10
OSC_IN
Oscillator input
11
NC
No connect
12
OPTP
Connect to VDD3
13
REFC
Reference capacitor
14
REFB
Reference capacitor
15
VDD3
Supply voltage
16
GND
Ground
17
VDD3
Supply voltage
18
NC
No connect
19
GND
Ground
20
NC
No connect
Date Code
16
5
10
Product Number
18
3
15
Lot Code
14
13
8
12
11
Item
Marking
Remarks
Product Number
A3080
Date Code
XYYWWZ
X = Subcon Code
YYWW = Date Code
Z = Sensor Die Source
Lot Code
VVV
Numeric
Figure 1. Package outline drawing (top view)
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High-Performance Optical Mouse Sensor
Pin #1
Features for
Illustration only
(1.21)
0.048
(4.86)
0.191
Product Number
Date Code
Lot Code
22.30
0.878
9.10
0.358
(6.43)
0.253
12.85
(At Shoulder)
0.506
7.05
3.18
0.99
0.278
0.125
0.039
90 ± 3q
2.00
Lead Pitch
0.079
Lead Offset 1.00
0.039
Lead Width
4.55
0.179
0.50
0.020
7.28 ± 0.03
0.287 ± 0.001
1.82 ± 0.03
0.071 ± 0.001
∅ 5.60 ± 0.03
0.220 ± 0.001
A
A
∅ 1.05 ± 0.03
0.25
0.010
12.85 ± 0.74 (At Lead Tip)
0.506 ± 0.029
0.3
Chamfer
0.012
Kapton Tape
6.025
0.237
13.38
0.527
2.25 ± 0.03
0.089 ± 0.001
(3.67)
0.144
( 1.5~ Draft)
Section A-A
Pin #1
0.041 ± 0.001
Notes:
1. Dimensions in millimeters / inches.
2. Dimensional tolerance: ±0.1mm.
3. Coplanarity of leads: 0.1mm.
4. Lead pitch tolerance: ±0.15mm.
5. Non-cumulative pitch tolerance: ±0.15mm.
6. Angular tolerance: ±3.0q
7. Maximum flash: 0.2mm.
8. Chamfer (25 x 2) on the taper side of the lead.
9. () These dimensions are for reference only and should
not be used to mechanically reference the sensor.
10. Document Number: LED_Spts_20A_Pkg_001.
Figure 2. Package outline drawing
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.
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High-Performance Optical Mouse Sensor
Overview of Optical Mouse Sensor Assembly
2D Assembly Drawing of ADNS-3080
Shown with ADNS-2120-001 trim lens, ADNS-2220-001
assembly clip and HLMP-EG3E-xxxxx led.
PixArt Imaging provides an IGES file drawing describing the base plate molding features for lens and PCB
alignment.
The components interlock as they are mounted onto
defined features on the base plate.
The ADNS-3080 sensor is designed for mounting on a
through hole PCB, looking down. There is an aperture
stop and features on the package that align to the lens.
The ADNS-2120-001 trim lens provides optics for the
imaging of the surface as well as illumination of the
surface at the optimum angle. Features on the lens
align it to the sensor, base plate, and clip with the LED.
The lens also has a large round flange to provide a long
creepage path for any ESD events that occur at the
opening of the base plate.
The ADNS-2220-001 clip holds the LED in relation to
the lens. The LED must be inserted into the clip and the
LED’s leads formed prior to loading on the PCB. The clip
interlocks the sensor to the lens, and through the lens to
the alignment features on the base plate.
The HLMP-EG3E-xxxxx LED is recommended for illumination. If used with the bin table, sufficient illumination can
be guaranteed.
43.13
1.698
42.53
1.674
39.06
1.538
29.50
1.161
1.50
0.059
1.00
0.039
2X ∅ 3.55
0.140
28.13
1.107
1.22 3.22
0.048 0.127
12.60
0.496
11.38
0.448
0
1.28
0.050
5.06
0.199
Clear Zone
0
20X ∅ 0.80 Recommended
0.031
Dimensions in millimeters / inches
Figure 3. Recommended PCB mechanical cutouts and spacing
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7.60
0.299
13.88
0.546
15.88
0.625
PixArt Imaging Inc.
High-Performance Optical Mouse Sensor
43.96
1.731
Base Plate
19.10
0.752
Gap between sensor
lead and lens gate
0.119
0.005
Top of PCB to top
of lens flange
3.75
0.148
Plastic Spring
Clip
3.00 Top of PCB to top
0.118 of lens gate
15.90
0.626
Sensor
Surface
16.61
0.654
12.61
0.496
7.45
0.293
PCB
Bottom of sensor 1.98
to top of PCB
0.078
Base Plate
Alignment Post
Dimensions in millimeters / inches
Figure 4. 2D Assembly drawing of ADNS-3080 (top and side view)
NOTE: These new 1JY"SU*NBHJOH optical mouse sensors, lenses and clips have different physical configurations
that require a different PCB mounting method to optimize the navigation performance.
Refer Application Notes AN 5035 for further information.
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High-Performance Optical Mouse Sensor
PCB Assembly Considerations
HLMP-EG3E-xxxxx (LED)
ADNS-2220-001 (Clip)
ADNS-3080 (Sensor)
Customer supplied PCB
ADNS-2120-001 (Trim Lens)
Customer supplied base plate
with recommended alignment
features per IGES drawing.
Figure 5. Exploded view drawing
1. Insert the sensor and all other electrical components
into PCB.
2. Insert the LED into the assembly clip and bend the
leads 90 degrees.
3. Insert the LED/clip assembly into PCB.
4. This sensor package is only qualified for wave-solder
process.
5. Wave Solder the entire assembly in a no-wash solder
process utilizing solder fixture. The solder fixture is
needed to protect the sensor during the solder process. It also sets the correct sensor-to -PCB distance as
the lead shoulders do not normally rest on the PCB
surface. The fixture should be designed to expose
the sensor leads to solder while shielding the optical
aperture from direct solder contact.
6. Place the lens onto the base plate.
7. Remove the protective kapton tape from optical aperture of the sensor. Care must be taken to keep contaminants from entering the aperture. During mouse
assembly process, it is recommended that the PCB is
held vertically when kapton tapes are being removed.
8. Insert PCB assembly over the lens onto the base plate
aligning post to retain PCB assembly. The sensor aperture ring should self-align to the lens.
9. The optical position reference for the PCB is set by the
base plate and lens. Note that the PCB motion due to
button presses must be minimized to maintain optical
alignment.
10. Install mouse top case. There MUST be a feature in the
top case to press down.
OSC_IN
NCS
RESONATOR
MOSI
MISO
OSC_OUT
REFB
IMAGE
PROCESSOR
LED_CTRL
CTRL
RESET
VOLTAGE REGULATOR
AND POWER CONTROL
SCLK
Serial Port
OSCILLATOR
REFC
REFERENCE
VOLTAGE
FILTER NODE
OPTP
NPD
V DD3
3.3 V POWER
GND
Figure 6. Block diagram of ADNS-3080 optical mouse sensor
6
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High-Performance Optical Mouse Sensor
Design considerations for improving ESD Performance
The flange on the lens has been designed to increase
the creepage and clearance distance for electrostatic discharge. The table below shows typical values
assuming base plate construction per the PixArt
Imaging supplied IGES file and ADNS-2120-001 trim lens
flange.
Typical Distance
Millimeters
Creepage
16.0
Clearance
2.1
For improved ESD performance, the lens flange can be
sealed (i.e. glued) to the base plate. Note that the lens
material is polycarbonate and therefore, cyanoacrylate
based adhesives or other adhesives that may damage the
lens should NOT be used.
Clip
LED
Sensor
PCB
Lens/Light Pipe
Base Plate
Surface
Figure 7. Cross section of PCB assembly
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High-Performance Optical Mouse Sensor
LP2950ACZ-3.3
3 Vin
Vo 1
GND
2
+
0.1uF
0.1uF
4.7uF
4.7uF
V DD V DD Internal
Image
16 GND
Sensor
19
GND
Vcc
GND
Vcc
SHLD
D-
11
Vreg
17 P1.7
18
P1.5
CYPRESS
CY7C63743A-PC
1.3 KΩ
3
Vcc
Scroll Wheel
Encoder
ALPS
EC10E
QA
QB
7
P0.7* 21
3
P0.6 22
2
P0.5* 23
4
P0.4* 24
1
P0.2 3
10 KΩ
6
P0.3 4
10 KΩ
7
1
2
P1.0
P1.2
P1.1
20KΩ
5
LED_CTRL
MISO
MOSI
REFC
13
+
NCS
REFB
RESET
NPD
OSC_IN
20KΩ
OSC_OUT
L
M
Buttons
R
VSS 9
XTALOUT
13
5
14
11 18
OPTP
2.2
uF
10
9
24 MHz
8
Ceramic Resonator
Murata
CSALS 24 M 0X 53 -B 0
TDK FCR 24. 0 M 2G
6
20
187Ω
1/8 W
SURFACE
GUARD
P1.4
HLMP-EG3E-xxxxx
BS170
SCLK
NC
15
D-
D+
NC
16
D+
Vpp
NC
10
ADNS
2120
Lens
15
17
+
14
Vcc
Vcc
0.1uF
ADNS-3080
0.1
uF
12
Vo 3.3V
20
XTALIN
12
6 MHz
(Optional)
20kΩ
Notes:
- All capacitors close to chip
- 24MHz and 6MHz oscillators close to chip
- * Outputs configured as open drain
20kΩ
Figure 8. Schematic Diagram for USB, PS/2 mouse application with ADNS-3080
Notes
• Caps for pins 15 and 17 MUST have trace lengths LESS than 5 mm to nearest ground pin.
• Pins 15 and 17 caps MUST use pin 16 GND.
• Pin 9, if used, should not be connected to PCB GND to reduce potential RF emissions.
• The 0.1 uF caps must be ceramic.
• Caps should have less than 5 nH of self inductance.
• Caps should have less than 0.2 Ω ESR.
• NC pins should not be connected to any traces.
• Surface mount parts are recommended.
• Care must be taken when interfacing a 5V microcontroller to the ADNS-3080. Serial port inputs on the sensor should be connected to opendrain outputs from the microcontroller or use an active drive level shifter. NPD and RESET should be connected to 5V microcontroller outputs
through a resistor divider or other level shifting technique.
• VDD3 and GND should have low impedance connections to the power supply.
• Capacitors connected to pin 15 and 17 should be connected to pin 16 and then to pin 19.
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High-Performance Optical Mouse Sensor
Enabling the SROM
Regulatory Requirements
For best tracking performance,SROM is required to
be loaded into ADNS-3080. This architecture enables
immediate adoption of new features and improved performance algorithms. The external program is supplied
by PixArt Imaging as a file which may be burned
into a programmable device. A micro-controller with
sufficient memory may be used. On power-up and reset,
the ADNS-3080 program is downloaded into volatile
memory using the burst-mode procedure described in
the Synchronous Serial Port section. The program size
is 1986 x 8 bits.
 Passes FCC B and worldwide analogous emission limits
when assembled into a mouse with shielded cable and
following PixArt Imaging’ recommendations.
 Passes IEC-1000-4-3 radiated susceptibility level when
assembled into a mouse with shielded cable and following PixArt Imaging’ recommendations.
 Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with shielded cable and following
PixARt Imaging ’ recommendations.
 UL flammability level UL94 V-0.
 Provides sufficient ESD creepage/clearance distance
to avoid discharge up to 15kV when assembled into a
mouse according to usage instructions above.
Sensor
Lens
2.40
0.094
Object Surface
Figure 9. Distance from lens reference plane to surface
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High-Performance Optical Mouse Sensor
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Storage Temperature
TS
Operating Temperature
TA
Typical
Maximum
Units
-40
85
oC
-15
55
oC
260
oC
3.7
V
2
kV
All pins, human body model
MIL 883 Method 3015
VDD3+0.5
V
NPD, NCS, MOSI, SCLK, RESET,
OSC_IN, OSC_OUT, REFC.
20
mA
LED_CTRL, MISO
Lead Solder Temp
Supply Voltage
VDD3
-0.5
ESD
Input Voltage
VIN
Output current
Iout
-0.5
Notes
For 10 seconds,
1.6mm below seating plane.
Recommended Operating Conditions
Parameter
Symbol
Minimum
Operating Temperature
TA
0
Power supply voltage
VDD3B
3.10
Power supply rise time
VRT
1
Supply noise
(Sinusoidal)
VNB
Oscillator capable
Frequency
fCLK
Serial Port Clock
Frequency
Typical
3.30
Maximum
Units
40
°C
3.60
Volts
Notes
us
0 to 3.0V
30
80
mV p-p
10kHz- 300KHZ
300KHz-50MHz
25
MHz
Set by ceramic resonator
fSCLK
2
500
MHz
kHz
Active drive, 50% duty cycle
Open drain drive with pull-ups on,
50 pF load
Resonator Impedance
XRES
55
W
Distance from lens
reference plane to
surface
Z
2.3
2.5
mm
Results in ±0.2 mm DOF,
See drawing below
Speed
S
0
40
in/sec
@ 6469fps
Acceleration
A
15
g
@ 6469fps
Light level onto IC
IRRINC
20
24
100
120
6,000
7,200
6,000
7,200
mW/m2
l = 639 nm, FR=1500 fps
l = 875 nm, FR=1500 fps
l = 639 nm, FR=6469 fps
l = 875 nm, FR=6469 fps
Frame Rate
FR
2000
6469
Frames/s
See Frame_Period register section
LED Drive Current
ILED
10
mA
HLMP-EG3E-xxxxx, bin N and
brighter.
Maximum frame rate may not be
maintained on dark surfaces at the
minimum LED drive current
23
24
2.4
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High-Performance Optical Mouse Sensor
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz.
Parameter
Symbol
VDD to RESET
Min.
Typical
Max.
Units
Notes
tOP
250
s
From VDD = 3.0V to RESET sampled
Data delay
after RESET
tPU-RESET
35
ms
From RESET falling edge to valid motion data at
2000 fps and shutter bound 8290.
Input delay
after reset
TIN-RST
500
s
From RESET falling edge to inputs active (NPD,
MOSI, NCS, SCLK)
Power Down
tPD
2.1
ms
From NPD falling edge to initiate the power down
cycle at 500fps (tpd = 1 frame period + 100ms )
Wake from NPD
tPUPD
75
ms
From NPD rising edge to valid motion data at
2000 fps and shutter bound 8290. Max assumes
surface change while NPD is low.
Data delay
after NPD
tCOMPUTE
3.1
ms
From NPD rising edge to all registers contain data
from new images at 2000fps (see Figure 10) .
RESET pulse width
tPW-RESET
MISO rise time
tr-MISO
40
200
ns
CL = 50pF
MISO fall time
tf-MISO
40
200
ns
CL = 50pF
MISO delay
afterSCLK
tDLY-MISO
120
ns
From SCLK falling edge to MISO data valid, no
load conditions
MISO hold time
thold-MISO
250
ns
Data held until next falling SCLK edge
MOSI hold time
thold-MOSI
200
ns
Amount of time data is valid after SCLK rising
edge
MOSI setup time
tsetup-MOSI
120
ns
From data valid to SCLK rising edge
SPI time between
write commands
tSWW
50
s
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second data byte.
SPI time between
write and read
commands
tSWR
50
s
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second address
byte.
SPI time between
tSRW
read and subsequent tSRR
commands
250
ns
From rising SCLK for last bit of the first data byte,
to falling SCLK for first bit of the second address
byte.
SPI read
address-data
delay
tSRAD
50
s
From rising SCLK for last bit of the address byte,
to falling SCLK for first bit of data being read. All
registers except Motion & Motion_Burst
SPI motion read
address-data
delay
tSRAD-MOT
75
s
From rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. Applies
to 0x02 Motion, and 0x50 Motion_Burst, registers
NCS to SCLK active
tNCS-SCLK
120
ns
From NCS falling edge to first SCLK rising edge
SCLK to NCS inactive
tSCLK-NCS
120
ns
From last SCLK falling edge to NCS rising edge,
for valid MISO data transfer
NCS to MISO high-Z
tNCS-MISO
ns
From NCS rising edge to MISO high-Z state
s
10
250
SROM download and tLOAD
frame capture
byte-to-byte delay
10
s
(see Figure 23 and 24)
NCS to burst mode
exit
tBEXIT
4
s
Time NCS must be held high to exit burst mode
Transient Supply
Current
IDDT
mA
Max supply current during a VDD3 ramp from 0 to
3.6V
85
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DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz.
Parameter
Symbol
Minimum
Typical
Maximum
Units
Notes
DC Supply
Current
IDD_AVG
52
mA
DC average at 6469 fps.
No DC load on LED_CTRL, MISO.
Power Down
Supply Current
IDDPD
90
A
NPD=GND; SCLK, MOSI, NCS=GND or VDD3;
RESET=GND
Input Low
Voltage
VIL
0.8
V
SCLK, MOSI, NPD, NCS, RESE
Input High
Voltage
VIH
V
SCLK, MOSI, NPD, NCS, RESET
Input hysteresis
VI_HYS
200
mV
SCLK, MOSI, NPD, NCS, RESET
Input current,
pull-up disabled
IIH_DPU
0
±10
A
Vin=0.8*VDD3, SCLK, MOSI, NCS
Input current,
CMOS inputs
IIH
0
±10
A
NPD, RESET, Vin=0.8*VDD3
Output current,
pulled-up inputs
IOH_PU
300
600
A
Vin=0.2V, SCLK, MOSI, NCS
Output Low
Voltage
LED_CTRL
VOL,LED
0.5
V
Iout=2mA, LED_CTRL
Output High
voltage,
LED_CTRL
VOH_LED
V
Iout=-2mA, LED_CTRL
Output Low
Voltage, MISO
VOL
V
Iout=2mA, MISO
Output High
Voltage, MISO
VOH
V
Iout=-2mA, MISO
Input
Capacitance
CIN
pF
OSC_IN, OSC_OUT
5
0.7 * VDD3
150
0.8*VDD3
0.5
0.8*VDD3
14-22
Detail of NPD rising edge timing
NPD
Reset
Count
Oscillator Start
250 μs
340 μs
Frame
2
Frame
1
Frame
3
Frame
4
Frame
5
LED CURRENT
(shutter mode)
SCLK
590 μs
Optional SPI transactions
with old image data
“Motion” bit set if
motion was detected.
First read dX = dY = 0
t COMPUTE = 590 μs + 5 Frame Periods
Figure 10. NPD Rising Edge Timing Detail
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Typical Performance Characteristics
Mean Resolution vs. Z (White Paper)
2000
White Paper
1800
Manila
1600
Burl
Resolution (counts/inch)
1400
Z
1200
Black Walnut
DOF
Black Copy
1000
DOF
800
600
OPERATING REGION
400
200
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.
6
-0.
5
-0.
4
-0.
3
-0.
2
-0.
1
-0.
8
-0.
7
0
Distance from Nominal Focus (mm)
Figure 11. Mean Resolution vs. Z (White Paper)
Typical Path Deviation
Largest Single Perpendicular Deviation From A Straight Line At 45 Degrees
Path length = 4 inches; Speed = 6 ips; Resolution = 1600 cpi
Maximum Distance (Mouse Count)
50
45
White Paper
40
Manila
35
Burl
30
Black Walnut
Black Copy
25
20
15
10
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Distance From Lens Reference Plane To Navigation Surface (mm)
Relationship of mouse count to distance = m (mouse count) / n (cpi)
eg: Deviation of 7 mouse count = 7/1600 = 0.004375 inch ~ 0.004 inch
where m = 7, n = 1600
Figure 12. Average error vs. Distance (mm)
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1
0.9
Relative responsivity
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
500
400
600
700
wavelength (nm)
800
900
1000
Figure 13. Relative responsivity
Average Supply Current vs Frame Rate VDD=3.6V
120%
100%
100%
88%
Relative Current
80%
72%
60%
51%
55%
40%
20%
0%
0
2000
4000
Frame Rate (Hz)
6000
8000
Figure 14. Idd vs. Frame Rate
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Synchronous Serial Port
Chip Select Operation
The synchronous serial port is used to set and read parameters in the ADNS-3080, and to read out the motion
information. The serial port is also used to load SROM
data into the ADNS-3080.
The serial port is activated after NCS goes low. If NCS
is raised during a transaction, the entire transaction is
aborted and the serial port will be reset. This is true
for all transactions including SROM download. After a
transaction is aborted, the normal address-to-data or
transaction-to-transaction delay is still required before
beginning the next transaction. To improve communication reliability, all serial transactions should be framed by
NCS. In other words, the port should not remain enabled
during periods of non-use because ESD and EFT/B events
could be interpreted as serial communication and put
the chip into an unknown state. In addition, NCS must
be raised after each burst-mode transaction is complete
to terminate burst-mode. The port is not available for
further use until burst-mode is terminated.
The port is a four-wire, serial port. The host micro-controller always initiates communication; the ADNS-3080
never initiates data transfers. The serial port cannot be
activated while the chip is in power down mode (NPD
low) or reset (RESET high). SCLK, MOSI, and NCS may be
driven directly by a 3.3V output from a micro-controller,
or they may be placed in an open drain configuration by
enabling on-chip pull-up current sources. The open drain
drive allows the use of a 5V micro-controller without any
level shifting components. The port pins may be shared
with other SPI slave devices. When the NCS pin is high,
the inputs are ignored and the output is tri-stated.
The lines which comprise the SPI port are:
SCLK: Clock input. It is always generated by the master
(the micro- controller).
MOSI: Input data (Master Out/Slave In).
MISO: Output data (Master In/Slave Out).
NCS: Chip select input (active low).
NCS needs to be low to activate the serial port; otherwise,
MISO will be high-Z, and MOSI & SCLK will be ignored.
NCS can also be used to reset the serial port in case of
an error.
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Write Operation
Read Operation
Write operation, defined as data going from the microcontroller to the ADNS-3080, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address (seven bits) and has a “1” as its MSB
to indicate data direction. The second byte contains
the data. The ADNS-3080 reads MOSI on rising edges
of SCLK.
A read operation, defined as data going from the ADNS3080 to the micro-controller, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address, is sent by the micro-controller over
MOSI, and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-3080 over MISO. The sensor outputs MISO bits on
falling edges of SCLK and samples MOSI bits on every
rising edge of SCLK.
NOTE:
The 250 ns minimum high state of SCLK is also the minimum
MISO data hold time of the ADNS-3080. Since the falling
edge of SCLK is actually the start of the next read or write
command, the ADNS-3080 will hold the state of data on
MISO until the falling edge of SCLK.
SCLK
SCLK
MOSI
tHOLD-MISO
tDLY-MISO
tHold,MOSI
D0
MISO
tSetup, MOSI
Figure 15. MOSI setup and hold time
Figure 18. MISO delay and hold time
NCS
1
2
1
A
3
4
5
6
7
8
9
10
12
11
13
15
14
16
1
2
1
A
SCLK
MOSI
6
A
5
A
4
A
A
3
A
2
A
1
0
D
7
D
D
6
5
D
4
D
3
D
2
D
D
1
0
MISO
MOSI Driven by Micro-Controller
Figure 16. Write Operation
NCS
SCLK
Cycle #
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
8
9
10
D7
D6
11
12
13
14
D4
D3
D2
15
16
SCLK
MOSI
0
MISO
A0
D5
D1
tSRAD delay
Figure 17. Read operation
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D0
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Required timing between Read and Write Commands (tsxx)
There are minimum timing requirements between read and write commands on the serial port.
tSWW ≥ 50μs
SCLK
Address
Data
Address
Write Operation
Data
Write Operation
Figure 19. Timing between two write commands
If the rising edge of the SCLK for the last data bit of the second write command occurs before the 50 microsecond
required delay, then the first write command may not complete correctly.
tSWR ≥ 50μs
SCLK
Address
Data
Address
Next Read
Operation
Write Operation
Figure 20. Timing between write and read commands
If the rising edge of SCLK for the last address bit of the read command occurs before the 50 microsecond required
delay, the write command may not complete correctly.
tSRW & tSRR > 250 ns
tSRAD ≥ 50 μs for non-motion read
tSRAD-MOT ≥ 75 μs for register 0x02
SCLK
Address
Data
Read Operation
Address
Next Read or
Write Operation
Figure 21. Timing between read and either write or subsequent read commands
The falling edge of SCLK for the first address bit of either the read or write command must be at least 250 ns after
the last SCLK rising edge of the last data bit of the previous read operation. In addition, during a read operation SCLK
should be delayed after the last address bit to ensure that the ADNS-3080 has time to prepare the requested data.
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Burst Mode Operation
Motion Read
Burst mode is a special serial port operation mode which
may be used to reduce the serial transaction time for
three predefined operations: motion read and SROM
download and frame capture. The speed improvement is
achieved by continuous data clocking to or from multiple
registers without the need to specify the register address,
and by not requiring the normal delay period between
data bytes.
This mode is activated by reading the Motion_Burst
register. The ADNS-3080 will respond with the contents
of the Motion, Delta_X, Delta_Y, SQUAL, Shutter_Upper,
Shutter_Lower and Maximum_Pixel registers in that
order. After sending the register address, the microcontroller must wait tSRAD-MOT and then begin reading
data. All 56 data bits can be read with no delay between
bytes by driving SCLK at the normal rate. The data are
latched into the output buffer after the last address bit
is received. After the burst transmission is complete, the
micro-controller must raise the NCS line for at least tBEXIT
to terminate burst mode. The serial port is not available
for use until it is reset with NCS, even for a second burst
transmission.
tSRAD-MOT ≥ 75 μs
SCLK
Motion_Burst Register Address
Read First Byte
First Read Operation
Read Second Byte
Read Third Byte
Figure 22. Motion burst timing
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SROM Download
This function is used to load the PixArt Imaging
supplied firmware file contents into the ADNS-3080. The
firmware file is an ASCII text file with each 2-character
byte (hexadecimal representation) on a single line.
This mode is activated by the following steps:
1. Perform hardware reset by toggling the RESET pin
2. Write 0x44 to register 0x20
3. Write 0x07 to register 0x23
4. Write 0x88 to register 0x24
5. Wait at least 1 frame period
6. Write 0x18 to register 0x14 (SROM_Enable register)
7. Begin burst mode write of data file to register 0x60
(SROM_Load register)
After the first data byte is complete, the SROM or microcontroller must write subsequent bytes by presenting
the data on the MOSI line and driving SCLK at the normal
rate. A delay of at least tLOAD must exist between data
bytes as shown. After the download is complete, the
micro-controller must raise the NCS line for at least tBEXIT
to terminate burst mode. The serial port is not available
for use until it is reset with NCS, even for a second burst
transmission.
PixArt Imaging recommends reading the SROM_ID
register to verify that the download was successful. In
addition, a self-test may be executed, which performs a
CRC on the SROM contents and reports the results in a
register. The test is initiated by writing a particular value
to the SROM_Enable register; the result is placed in the
Data_Out register. See those register descriptions for
more details.
PixArt Imaging provides the data file for download;
the file size is 1986 data bytes. The chip will ignore any
additional bytes written to the SROM_Load register after
the SROM file.
exit burst mode
tBEXIT ≥4μs
NCS
SROM_Enable reg write
3 reg writes, see text
address
MOSI
SCLK
key data
SROM_Load reg write
address
byte 0
byte 1
byte 1985
address
enter burst
mode
≥1 frame
period
tNCS -SCLK
>120ns
≥40μs
tLOAD
≥10μs
tLOAD
≥10μs
≥10μs
soonest to read SROM_ID
Figure 23. SROM download burst mode
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Frame Capture
This is a fast way to download a full array of pixel values
from a single frame. This mode disables navigation and
overwrites any downloaded firmware. A hardware reset
is required to restore navigation, and the firmware must
be reloaded afterwards if required.
To trigger the capture, write to the Frame_Capture
register. The next available complete 1 2/3 frames (1536
values) will be stored to memory. The data are is retrieved
by reading the Pixel_Burst register once using the normal
read method, after which the remaining bytes are clocked
out by driving SCLK at the normal rate. The byte time
must be at least tLOAD. If the Pixel_ Burst register is read
before the data is ready, it will return all zeros.
To read a single frame, read a total of 900 bytes. The next
636 bytes will be approximately 2/3 of the next frame.
The first pixel of the first frame (1st read) has bit 6 set to
1 as a start-of-frame marker. The first pixel of the second
partial frame (901st read) will also have bit 6 set to 1. All
other bytes have bit 6 set to zero. The MSB of all bytes is
set to 1. If the Pixel_Burst register is read past the end
of the data (1537 reads and on) , the data returned will
be zeros.
After the download is complete, the micro-controller
must raise the NCS line for at least tBEXIT to terminate
burst mode. The read may be aborted at any time by
raising NCS.
Alternatively, the frame data can also be read one byte at
a time from the Frame_Capture register. See the register
description for more information.
exit burst mode
tBEXIT ≥4μs
NCS
pixel dump reg read
frame capture reg write
MOSI
address
data
frame capture reg
address
address
enter burst
mode
≥10μs
soonest to begin again
SCLK
t NCS-SCLK
>120ns
t CAPTURE
tSRAD ≥50μs
MISO
P0 bit 6 set to 1
tLOAD
≥10μs
tLOAD
≥10μs
P0
P1
P899
all MSB = 1
see note 2
Notes:
1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker.
2. Reading beyond pixel 899 will return the first pixel of the second partial frame.
3. t CAPTURE ≥10μs + 3 frame periods.
4. This figure illustrates reading a single complete frame of 900 pixels. An additional 636 pixels from the next frame are available.
Figure 24. Frame capture burst mode timing
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The pixel output order as related to the surface is shown below.
Cable
Top Xray View of Mouse
Positive Y
LB
RB
Positive X
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
expanded view of the
surface as viewed
through the lens
last output
899 898 897 896 895 894 893 892 891 890 889 888 887 886 885 884 883 882 881 880 879 878 877 876 875 874 873 872 871 870
869 868 867 866 865 864 863 862 861 860 859 858 857 856 855 854 853 852 851 850 849 848 847 846 845 844 843 842 841 840
~ ~
839 838 ~
etc.
~
~
~
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
first output
Figure 25. Pixel address map (surface referenced)
Error detection and recovery
1. The ADNS-3080 and the micro-controller might get out
of synchronization due to ESD events, power supply
droops or micro-controller firmware flaws. In such a
case, the micro-controller should pulse NCS high for
at least 1 ms. The ADNS-3080 will reset the serial port
(but not the control registers) and will be prepared for
the beginning of a new transmission after the normal
transaction delay.
2. Invalid addresses: Writing to an invalid address will
have no effect. Reading from an invalid address will
return all zeros.
4. The micro-controller can verify success of write operations by issuing a read command to the same address
and comparing written data to read data.
5. The micro-controller can verify the synchronization of
the serial port by periodically reading the product ID
and inverse product ID registers.
6. The microcontroller can read the SROM_ID register to
verify that the sensor is running downloaded SROM
code. ESD or similar noise events may cause the sensor
to revert to native ROM execution. If this should happen, pulse RESET and reload the SROM instructions.
3. Termination of a transmission by the micro-controller
may sometimes be required (for example, due to a
USB suspend interrupt during a read operation). To
accomplish this the micro-controller should raise NCS.
The ADNS-3080 will not write to any register and will
reset the serial port (but not the control registers) and
be prepared for the beginning of future transmissions
after NCS goes low. The normal delays between reads
or writes (tSWW, tswr, tSRAD, tSRAD-mot) are still required
after aborted transmissions.
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Notes on Power-up and the serial port
The chip is put into the power down (PD) mode by
lowering the NPD input. When in PD mode, the oscillator is stopped but all register contents are retained. To
achieve the lowest current state, all inputs must be held
externally within 200mV of a rail, either ground or VDD3.
The chip outputs are driven low or hi-Z during PD to
prevent current consumption by an external load.
Reset Circuit
The ADNS-3080 does not perform an internal power up
self-reset. The reset pin must be raised and lowered to
reset the chip. This should be done every time power is
applied. During power-up there will be a period of time
after the power supply is high but before any clocks are
available. The table below shows the state of the various
pins during power-up and reset when the RESET pin is
driven high by a micro-controller.
LED Drive Mode
The LED has 2 modes of operation: DC and Shutter. In
DC mode it is on at all times the chip is powered except
when in the power down mode via the NPD pin. In
shutter mode the LED is on only during the portion of
the frame that light is required. The LED_MODE bit in the
Configuration_bits register sets the LED mode.
Power Down Circuit
The following table lists the pin states during power
down.
State of Signal Pins After VDD is Valid
Pin
Before Reset
During Reset
After Reset
SPI pullups
Undefined
Off
On (default)
NCS
Hi-Z control functional
Hi-Z control functional
Functional
MISO
Driven or hi-Z
(per NCS)
Driven or hi-Z
(per NCS)
Low or hi-Z
(per NCS)
SCLK
Undefined
Ignored
Functional
MOSI
Undefined
Ignored
Functional
LED_CTRL
Undefined
Low
High
RESET
Functional
High
(externally driven)
Functional
NPD
Undefined
Ignored
Functional
State of Signal Pins During Power Down
Pin
NPD low
After wake from PD
SPI pullups
off
pre-PD state
NCS
hi-Z control functional
functional
MISO
low or hi-Z (per NCS)
pre-PD state or hi-Z
SCLK
ignored
functional
MOSI
ignored
functional
LED_CTRL
low
high
RESET
functional
functional
NPD
low (driven externally)
functional
REFC
VDD3
REFC
OSC_IN
low
OSC_IN
OSC_OUT
high
OSC_OUT
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Registers
The ADNS-3080 registers are accessible via the serial port. The registers are used to read motion data and status as
well as to set the device configuration.
Address
Register
Read/Write
SROM Default Value
0x00
Product_ID
R
0x17
0x01
Revision_ID
R
0xNN
0x02
Motion
R
0x00
0x03
Delta_X
R
0x00
0x04
Delta_Y
R
0x00
0x05
SQUAL
R
0x00
0x06
Pixel_Sum
R
0x00
0x07
Maximum_Pixel
R
0x00
0x08
Reserved
0x09
Reserved
0x0a
Configuration_bits
R/W
0x09
0x0b
Extended_Config
R/W
0x00
0x0c
Data_Out_Lower
R
Any
0x0d
Data_Out_Upper
R
Any
0x0e
Shutter_Lower
R
0x85
0x0f
Shutter_Upper
R
0x00
0x10
Frame_Period_Lower
R
Any
0x11
Frame_Period_Upper
R
Any
0x12
Motion_Clear
W
Any
0x13
Frame_Capture
R/W
0x00
0x14
SROM_Enable
W
0x00
0x15
Reserved
0x16
Reserved
0x17
Reserved
0x18
Reserved
0x19
Frame_Period_Max_Bound Lower
R/W
0xE0
0x1a
Frame_Period_Max_Bound_Upper
R/W
0x2E
0x1b
Frame_Period_Min_Bound_Lower
R/W
0x7E
0x1c
Frame_Period_Min_Bound_Upper
R/W
0x0E
0x1d
Shutter_Max_Bound_Lower
R/W
0x00
0x1e
Shutter_Max_Bound_Upper
R/W
0x20
0x1f
SROM_ID
R
0x00
0x20-0x3c
Reserved
0x3d
Observation
R/W
0x00
0x3e
Reserved
0x3f
Inverse Product ID
R
0xF8
0x40
Pixel_Burst
R
0x00
0x50
Motion_Burst
R
0x00
0x60
SROM_Load
W
Any
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Product_ID
Address: 0x00
Access: Read
Reset Value: 0x17
Bit
7
6
5
4
3
2
1
0
Field
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
Data Type: 8-Bit unsigned integer
USAGE: This register contains a unique identification assigned to the ADNS-3080. The value in this register does not
change; it can be used to verify that the serial communications link is functional.
Revision_ID
Address: 0x01
Access: Read
Reset Value: 0xNN
Bit
7
6
5
4
3
2
1
0
Field
RID7
RID6
RID5
RID4
RID3
RID2
RID1
RID0
Data Type: 8-Bit unsigned integer.
USAGE: This register contains the IC revision. It is subject to change when new IC versions are released.
NOTE: The downloaded SROM firmware revision is a separate value and is available in the SROM_ID register.
Motion
Address: 0x02
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
MOT
Reserved
Reserved
OVF
Reserved
Reserved
Reserved
RES
Data Type: Bit field.
USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then
the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have
overflowed, and the current resolution setting.
Field Name
Description
MOT
Motion since last report or PD
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
Reserved
Reserved
Reserved
Reserved
OVF
Motion overflow, Delta_Y and/or Delta_X buffer has overflowed since last report
0 = no overflow
1 = Overflow has occurred
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RES
Resolution in counts per inch
0 = 400
1 = 1600
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Notes for Motion:
1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If
Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost.
2. PixArt Imaging RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. See Motion burst mode also.
3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data
is lost and the OVF bit is set. This bit is cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buffers are
not at full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated
until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale.
If the motion register has not been read for long time, at 400 cpi it may take up to 16 read cycles to clear the buffers, at 1600 cpi, up to 64 cycles.
Alternatively, writing to the Motion_Clear register (register 0x12) will clear all stored motion at once.
Delta_X
Address: 0x03
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type: Eight bit 2’s complement number.
USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the
register.
Motion
Delta_X
-128
-127
-2
-1
0
+1
+2
+126
+127
80
81
FE
FF
00
01
02
7E
7F
Delta_Y
Address: 0x04
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type: Eight bit 2’s complement number.
USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the
register.
Motion
Delta_Y
-128
-127
-2
-1
0
+1
+2
+126
+127
80
81
FE
FF
00
01
02
7E
7F
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SQUAL
Address: 0x05
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type: Upper 8 bits of a 10-bit unsigned integer.
USAGE: SQUAL (Surface Quality) is a measure of ¼ of the number of valid* features visible by the sensor in the current
frame. Use the following formula to find the total number of valid features.
Number of features = SQUAL register value *4
The maximum SQUAL register value is 169. Since small changes in the current frame can result in changes in SQUAL,
variations in SQUAL when looking at a surface are expected. The graph below shows 250 sequentially acquired SQUAL
values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is no surface below
the sensor. SQUAL is typically maximized when the navigation surface is at the optimum distance from the imaging
lens (the nominal Z-height).
Squal Values (White Paper)
85
SQUAL Value
80
75
70
65
60
0
25
50
75
100
125
150
175
200
225
250
Figure 26. Squal values (white paper)
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Mean SQUAL vs Z (White Paper)
90
Avg
Avg - 3sigma
Avg + 3sigma
80
70
SQUAL
60
50
40
30
20
10
0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Delta from Nominal Focus (mm)
Figure 27. Mean squal vs. Z (white paper)
Pixel_Sum
Address: 0x06
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP0
Data Type: High 8 bits of an unsigned 16-bit integer.
USAGE: This register is used to find the average pixel value. It reports the upper byte of a 16-bit counter which sums
all 900 pixels in the current frame. It may be described as the full sum divided by 256. To find the average pixel value,
use the following formula:
Average Pixel = Register Value * 256 / 900 = Register Value/3.51
The maximum register value is 221 (63 * 900/256 truncated to an integer). The minimum is 0. The pixel sum value
can change on every frame.
Maximum_Pixel
Address: 0x07
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
0
0
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Six bit number.
USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The maximum pixel value
can vary with every frame.
Reserved
Address: 0x08
Reserved
Address: 0x09
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Configuration_bits
Address: 0x0a
Access: Read/Write
Reset Value: 0x09
Bit
7
6
5
4
3
2
1
0
Field
0
LED_MODE
Sys Test
RES
Reserved
Reserved
Reserved
Reserved
Data Type: Bit field
USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default
values, and optional values.
Field Name
Description
BIT 7
Must always be zero
LED_MODE
LED Shutter Mode
0 = Shutter mode off (LED always on)
1 = Shutter mode on (LED only on when illumination is required)
Sys Test
System Tests
0 = no tests
1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower
registers.
NOTE: The test will fail if SROM is loaded. Perform a hardware reset before executing this
test. Reload SROM after the test is completed.
NOTE: Since part of the system test is a RAM test, the RAM and SRAM will be overwritten
with the default values when the test is done. If any configuration changes from the default are needed for operation, make the changes AFTER the system test is run. The system
test takes 200ms (@24MHz) to complete.
NOTE: Do not access the Synchronous Serial Port during system test.
RES
Resolution in counts per inch
0 = 400
1 = 1600
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Extended_Config
Address: 0x0b
Access: Read/Write
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Busy
Reserved
Reserved
Reserved
Reserved
Serial_NPU
NAGC
Fixed_FR
Data Type: Bit field
USAGE: Register 0x0b allows the user to change the configuration of the sensor. Shown below are the bits, their default
values, and optional values.
Field Name
Description
Busy
Read-only bit. Indicates if it is safe to write to one or more of the following registers:
Frame_Period_Max_Bound_Upper and Lower
Frame_Period_Min_Bound_Upper and Lower
Shutter_Max_Bound_Upper and Lower
After writing to the Frame_Period_Max_Bound_Upper register, at least two frames must
pass before writing again to any of the above registers. This bit may be used in lieu of a timer
since the actual frame rate may not be known when running in auto mode.
0 = writing to the registers is allowed
1 = do not write to the registers yet
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Serial_NPU
Disable serial port pull-up current sources
0 = no, current sources are on
1 = yes, current sources are off
NAGC
Disable AGC. Shutter will be set to the value in the Shutter_Max_Bound registers.
0 = no, AGC is active
1 = yes, AGC is disabled
Fixed_FR
Fixed frame rate (disable automatic frame rate control). When this bit is set, the frame rate
will be determined by the value in the Frame_Period_Max_Bound registers.
0 = automatic frame rate
1 = fixed frame rate
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Data_Out_Lower
Address: 0x0c
Access: Read
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Data_Out_Upper
Address: 0x0d
Access: Read
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
DO15
DO14
DO13
DO12
DO11
DO10
DO9
DO8
Data Type: Sixteen bit word.
USAGE: Data in these registers come from the system self test or the SROM CRC test. The data can be read out 0x0d,
or 0x0d first, then 0x0c.
Data_Out_Upper
Data_Out_Lower
System test results:
0x1B
0xBF
SROM CRC Test Result:
0xBE
0xEF
System Test: This test is initiated via the Configuration_Bits register. It performs several tests to verify that the hardware
is functioning correctly. Perform a hardware reset just prior to running the test. SROM contents and register settings
will be lost.
SROM CRC Test: Performs a CRC on the SROM contents. The test is initiated by writing a particular value to the
SROM_Enable register.
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Shutter_Lower
Address: 0x0e
Access: Read
Reset Value: 0x85
Bit
7
6
5
4
3
2
1
0
Field
S7
S6
S5
S4
S3
S2
S1
S0
Shutter_Lower
Address: 0x0e
Access: Read
Reset Value: 0x85
Bit
7
6
5
4
3
2
1
0
Field
S15
S14
S13
S12
S11
S10
S9
S8
Shutter_Upper
Address: 0x0f
Access: Read
Reset Value: 0x00
Data Type: Sixteen bit unsigned integer.
USAGE: Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The
shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value
is checked and automatically adjusted to a new value if needed on every frame when operating in default mode.
When the shutter adjusts, it changes by ± 1/16 of the current value. The shutter value can be set manually by setting
the AGC mode to Disable using the Extended_Config register and writing to the Shutter_Maximum_Bound registers.
Because the automatic frame rate feature is related to shutter value. It may also be appropriate to enable the Fixed
Frame Rate mode using the Extended_Config register.
Shown below is a graph of 250 sequentially acquired shutter values, while the sensor was moved slowly over white
paper.
Mean Shutter vs Z (White Paper)
120
Shutter value (counts)
100
80
60
40
Avg
20
Avg - 3sigma
Avg + 3sigma
0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Distance from Nominal Focus (mm)
Figure 28. Mean shutter vs. Z (white paper)
The maximum value of the shutter is dependent upon the setting in the Shutter_Max_Bound_Upper and Shutter_
Max_Bound_Lower registers.
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Frame_Period_Lower
Address: 0x10
Access: Read
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Frame_Period_Upper
Address: 0x11
Access: Read
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
Data Type: Sixteen bit unsigned integer.
USAGE: Read these registers to determine the current frame period and to calculate the frame rate. Units are clock
cycles. The formula is
Frame Rate = Clock Frequency/Register value
To read from the registers, read Frame_Period_Upper first followed by Frame_Period Lower.
To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write the
desired count value to the Frame_Period_Maximum_Bound registers.
The following table lists some Frame_Period values for popular frame rates with a 24MHz clock.
Counts
Frame_Period
Frames/second
Decimal
Hex
Upper
Lower
6469
3,710
OE7E
OE
7E
5000
4,800
12C0
12
C0
3000
8,000
1F40
1F
40
2000
12,000
2EE0
2E
E0
Motion_Clear
Address: 0x12
Access: Write
Reset Value: Undefined
Data Type: Any.
USAGE: Writing any value to this register will cause the Delta_X, Delta_Y, and internal motion registers to be cleared.
Use this as a fast way to reset the motion counters to zero without resetting the entire chip.
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Frame_Capture
Address: 0x13
Access: Read/Write
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Data Type: Bit field
USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel values to be stored
to SROM RAM. Writing to this register is required before using the Frame Capture burst mode to read the pixel values
(see the Synchronous Serial Port section for more details). Writing to this register will stop navigation and cause any
firmware loaded in the SROM to be overwritten. A hardware reset is required to restore navigation, and the firmware
must be reloaded using the SROM Download burst method.
This register can also be used to read the frame capture data. The same data available by reading the Pixel_Burst
register using burst mode is available by reading this register in the normal fashion. The data pointer is automatically
incremented after each read so all 1536 pixel values (1 and 2/3 frames) may be obtained by reading this register 1536
times in a row. Both methods share the same pointer such that reading pixel values from this register will increment
the pointer causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to start at
the current pointer location. This register will return all zeros if read before the frame capture data is ready. See the
Frame Capture description in the Synchronous Serial Port section for more information.
This register will not retain the last value written. Reads will return zero or frame capture data.
SROM_Enable
Address: 0x14
Access: Write
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
Data Type: 8-bit number.
USAGE: Write to this register to start either SROM download or SROM CRC test.
Write 0x18 to this register before downloading SROM firmware to the SROM_Load register. The download will not be
successful unless this register contains the correct value.
Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period , then read result from the Data_Out_Lower
and Data_Out_Upper registers. Navigation is halted and the SPI port should not be used during this test.
Reserved
Address: 0x15 – 0x18
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Frame_Period_Max_Bound_Lower
Address: 0x19
Access: Read/Write
Reset Value: 0xE0
Bit
7
6
5
4
3
2
1
0
Field
FBm7
FBm6
FBm5
FBm4
FBm3
FBm2
FBm1
FBm0
Frame_Period_Max_Bound_Upper
Address: 0x1A
Access: Read/Write
Reset Value: 0x2E
Bit
7
6
5
4
3
2
1
0
Field
FBm15
FBm14
FBm13
FBm12
FBm11
FBm10
FBm9
FBm8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the automatic
frame rate control, or sets the actual frame period when operating in manual mode. Units are clock cycles. The formula
is
Frame Rate = Clock Frequency / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by
Upper. To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write
the desired count value to these registers.
Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new values in the following
registers:
• Frame_Period_Max_Bound_Upper and Lower
• Frame_Period_Min_Bound_Upper and Lower
• Shutter_Max_Bound_Upper and Lower
Any data written to these registers will be saved but will not take effect until the write to the Frame_Period_Max_
Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required to
implement the new settings. Writing to any of the above registers before the implementation is complete may put
the chip into an undefined state requiring a reset. The “Busy” bit in the Extended_Config register may be used in lieu
of a timer to determine when it is safe to write. See the Extended_Config register for more details.
The following table lists some Frame_Period values for popular frame rates (clock rate = 24MHz).
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
Counts
Frame_Period
Frames/second
Decimal
Hex
Upper
Lower
6469
3,710
OE7E
OE
7E
5000
4,800
12C0
12
C0
3000
8,000
1F40
1F
40
2000
12,000
2EE0
2E
E0
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Frame_Period_Min_Bound_Lower
Address: 0x1B
Access: Read/Write
Reset Value: 0xAC (before SROM download)
0x7E (after SROM download)
Bit
7
6
5
4
3
2
1
0
Field
FBm7
FBm6
FBm5
FBm4
FBm3
FBm2
FBm1
FBm0
Frame_Period_Min_Bound_Upper
Address: 0x1C
Access: Read/Write
Reset Value: 0x0D (before SROM download)
0x0E (after SROM download)
Bit
7
6
5
4
3
2
1
0
Field
FBm15
FBm14
FBm13
FBm12
FBm11
FBm10
FBm9
FBm8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) that may be selected by the automatic
frame rate control. Units are clock cycles. The formula is
Frame Rate = Clock Rate / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by
Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. The minimum allowed write
value is 0x7E0E; the maximum is 0xFFFF.
Reading this register will return the most recent value that was written to it. However, the value will take effect only
after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_
Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower again. The
“Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the
Extended_Config register for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
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Shutter_Max_Bound_Lower
Address: 0x1D
Access: Read/Write
Reset Value: 0x8C (before SROM download)
0x00 (after SROM download)
Bit
7
6
5
4
3
2
1
0
Field
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
Shutter_Max_Bound_Upper
Address: 0x1E
Access: Read/Write
Reset Value: 0x20
Bit
7
6
5
4
3
2
1
0
Field
SB15
SB14
SB13
SB12
SB11
SB10
SB9
SB8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum allowable shutter value when operating in automatic mode. Units are clock cycles.
Since the automatic frame rate function is based on shutter value, the value in these registers can limit the range of the
frame rate control. To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower
first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. To set the
shutter manually, disable the AGC via the Extended_Config register and write the desired value to these registers.
Reading this register will return the most recent value that was written to it. However, the value will take effect only
after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_Bound_
Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower again. The “Busy” bit in the
Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config
register for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
SROM_ID
Address: 0x1F
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Data Type:8-Bit unsigned integer.
USAGE: Contains the revision of the downloaded Shadow ROM firmware. If the firmware has been successfully downloaded and the chip is operating out of SROM, this register will contain the SROM firmware revision, otherwise it will
contain 0x00.
Note: The IC hardware revision is available by reading the Revision_ID register (register 0x01).
Reserved
Address: 0x20 – 0x3C
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Observation
Address: 0x3D
Access: Read/Write
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
OB7
Reserved
OB5
Reserved
Reserved
Reserved
OB1
OB0
Data Type: Bit field
USAGE: Each bit is set by some process or action at regular intervals, or when the event occurs. The user must clear
the register by writing 0x00, wait an appropriate delay, and read the register. The active processes will have set their
corresponding bit(s). This register may be used as part of a recovery scheme to detect a problem caused by EFT/B or
ESD.
Field Name
Description
OB7
If set, chip is running SROM code
Reserved
Reserved
OB5
NPD pulse was detected
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OB1
Set once per frame
OB0
Set once per frame
Reserved
Address: 0x3E
Inverse_Product_ID
Address: 0x3F
Access: Read
Reset Value: 0xF8
Bit
7
6
5
4
3
2
1
0
Field
NPID7
NPID6
NPID5
NPID4
NPID3
NPID2
NPID1
NPID0
Data Type: Inverse 8-Bit unsigned integer
USAGE: This value is the inverse of the Product_ID, located at the inverse address. It can be used to test the SPI port.
Pixel_Burst
Address: 0x40
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Data Type: Eight bit unsigned integer
USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values from one and 2/3 complete frame.
See the Synchronous Serial Port section for use details.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
37
PixArt Imaging Inc.
E-mail: [email protected]
PixArt Imaging Inc.
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Motion_Burst
Address: 0x50
Access: Read
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
Data Type: Various, depending on data
USAGE: The Motion_Burst register is used for high-speed access to the Motion, Delta_X, and Delta_Y, SQUAL, Shutter_
Upper, and Shutter_Lower and Maximum_Pixel registers. See the Synchronous Serial Port section for use details.
SROM_Load
Address: 0x 60
Access: Write
Rset Value: N/A
Data Type: Eight bit unsigned integer
USAGE: The SROM_Load register is used for high-speed programming of the ADNS-3080 from an external SROM or
microcontroller. See the Synchronous Serial Port section for use details.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]